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authorAndrey Smirnov <andrew.smirnov@gmail.com>2019-02-05 13:54:02 -0800
committerSascha Hauer <s.hauer@pengutronix.de>2019-02-11 10:37:49 +0100
commit4e000b192932a5155cfc35e0eb88599b82bde88b (patch)
treef55a04d2fbb65a03b9888ad3ba5da93e9254df7a /drivers/soc
parentde3bb00bd5883325313875a25caac1e917702169 (diff)
downloadbarebox-4e000b192932a5155cfc35e0eb88599b82bde88b.tar.gz
soc: imx: gpcv2: prefix i.MX7 specific defines
Port of a Linux commit a800f418420d37f60fa471665a156c45d2702437 So we can add i.MX8M support without introducing name clashes. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/imx/gpcv2.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 7bf45d4..24a6b96 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -24,19 +24,19 @@
#define GPC_LPCR_A_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
-#define USB_HSIC_PHY_A_DOMAIN BIT(6)
-#define USB_OTG2_PHY_A_DOMAIN BIT(5)
-#define USB_OTG1_PHY_A_DOMAIN BIT(4)
-#define PCIE_PHY_A_DOMAIN BIT(3)
-#define MIPI_PHY_A_DOMAIN BIT(2)
+#define IMX7_USB_HSIC_PHY_A_DOMAIN BIT(6)
+#define IMX7_USB_OTG2_PHY_A_DOMAIN BIT(5)
+#define IMX7_USB_OTG1_PHY_A_DOMAIN BIT(4)
+#define IMX7_PCIE_PHY_A_DOMAIN BIT(3)
+#define IMX7_MIPI_PHY_A_DOMAIN BIT(2)
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
-#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
-#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
-#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
-#define PCIE_PHY_SW_Pxx_REQ BIT(1)
-#define MIPI_PHY_SW_Pxx_REQ BIT(0)
+#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
+#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
+#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
+#define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
+#define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
#define GPC_M4_PU_PDN_FLG 0x1bc
@@ -46,9 +46,9 @@
* GPC_PGC memory map are incorrect, below offset
* values are from design RTL.
*/
-#define PGC_MIPI 16
-#define PGC_PCIE 17
-#define PGC_USB_HSIC 20
+#define IMX7_PGC_MIPI 16
+#define IMX7_PGC_PCIE 17
+#define IMX7_PGC_USB_HSIC 20
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -166,11 +166,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
.name = "mipi-phy",
},
.bits = {
- .pxx = MIPI_PHY_SW_Pxx_REQ,
- .map = MIPI_PHY_A_DOMAIN,
+ .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
+ .map = IMX7_MIPI_PHY_A_DOMAIN,
},
.voltage = 1000000,
- .pgc = PGC_MIPI,
+ .pgc = IMX7_PGC_MIPI,
},
[IMX7_POWER_DOMAIN_PCIE_PHY] = {
@@ -178,11 +178,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
.name = "pcie-phy",
},
.bits = {
- .pxx = PCIE_PHY_SW_Pxx_REQ,
- .map = PCIE_PHY_A_DOMAIN,
+ .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
+ .map = IMX7_PCIE_PHY_A_DOMAIN,
},
.voltage = 1000000,
- .pgc = PGC_PCIE,
+ .pgc = IMX7_PGC_PCIE,
},
[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
@@ -190,11 +190,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
.name = "usb-hsic-phy",
},
.bits = {
- .pxx = USB_HSIC_PHY_SW_Pxx_REQ,
- .map = USB_HSIC_PHY_A_DOMAIN,
+ .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
+ .map = IMX7_USB_HSIC_PHY_A_DOMAIN,
},
.voltage = 1200000,
- .pgc = PGC_USB_HSIC,
+ .pgc = IMX7_PGC_USB_HSIC,
},
};