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authorSascha Hauer <s.hauer@pengutronix.de>2015-08-31 16:55:52 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2015-08-31 17:12:28 +0200
commitcd4df8f82b77e2599a65b81cfa06f3bc58399e15 (patch)
tree0f61c94c195d173d757d9b354863ce76f94cd1e5 /drivers/spi
parent311f02fbe4f00cafbb365ef76b8ad2231a2934cd (diff)
downloadbarebox-cd4df8f82b77e2599a65b81cfa06f3bc58399e15.tar.gz
barebox-cd4df8f82b77e2599a65b81cfa06f3bc58399e15.tar.xz
spi: i.MX: use start mode control bit
The i.MX SPI controller in version 2.3 can immediately start a transfer when the txfifo is written to. In this mode we no longer have to trigger the transfer with the xch bit which makes the code a bit simpler. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/imx_spi.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index 6805d22a75..81fa3b02ab 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -230,14 +230,8 @@ static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data)
{
void __iomem *base = imx->regs;
- unsigned int cfg_reg = readl(base + CSPI_2_3_CTRL);
-
writel(data, base + CSPI_2_3_TXDATA);
- cfg_reg |= CSPI_2_3_CTRL_XCH;
-
- writel(cfg_reg, base + CSPI_2_3_CTRL);
-
while (!(readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR));
return readl(base + CSPI_2_3_RXDATA);
@@ -306,6 +300,8 @@ static void cspi_2_3_chipselect(struct spi_device *spi, int is_active)
ctrl |= (spi->bits_per_word - 1) << CSPI_2_3_CTRL_BL_OFFSET;
+ ctrl |= CSPI_2_3_CTRL_SMC;
+
cfg |= CSPI_2_3_CONFIG_SBBCTRL(cs);
if (spi->mode & SPI_CPHA)