Merge branch 'for-next/imx'

Conflicts:
	arch/arm/configs/tx25stk5_defconfig

2 files changed, 59 insertions, 1 deletions

diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c
index bbdbe40339..70429eb5d8 100644
--- a/drivers/video/imx-ipu-v3/imx-ldb.c
+++ b/drivers/video/imx-ipu-v3/imx-ldb.c
@@ -190,7 +190,36 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
 
 static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
 {
-	return -ENOSYS;
+	struct clk *diclk, *ldbclk;
+	struct imx_ldb *ldb = imx_ldb_ch->ldb;
+	int ret, dino;
+	char *clkname;
+
+	dino = di & 0x1;
+
+	clkname = asprintf("ipu_di%d_sel", dino);
+	diclk = clk_lookup(clkname);
+	free(clkname);
+	if (IS_ERR(diclk)) {
+		dev_err(ldb->dev, "failed to get di clk: %s\n", strerror(PTR_ERR(diclk)));
+		return PTR_ERR(diclk);
+	}
+
+	clkname = asprintf("ldb_di%d_div", imx_ldb_ch->chno);
+	ldbclk = clk_lookup(clkname);
+	free(clkname);
+	if (IS_ERR(ldbclk)) {
+		dev_err(ldb->dev, "failed to get ldb clk: %s\n", strerror(PTR_ERR(ldbclk)));
+		return PTR_ERR(ldbclk);
+	}
+
+	ret = clk_set_parent(diclk, ldbclk);
+	if (ret) {
+		dev_err(ldb->dev, "failed to set display clock parent: %s\n", strerror(-ret));
+		return ret;
+	}
+
+	return 0;
 }
 
 static struct imx_ldb_data imx_ldb_data_imx6q = {
diff --git a/drivers/video/imx-ipu-v3/ipu-common.c b/drivers/video/imx-ipu-v3/ipu-common.c
index 5f3b0bb66d..c60236343a 100644
--- a/drivers/video/imx-ipu-v3/ipu-common.c
+++ b/drivers/video/imx-ipu-v3/ipu-common.c
@@ -22,6 +22,8 @@
 #include <asm/mmu.h>
 #include <mach/generic.h>
 #include <mach/imx6-regs.h>
+#include <mach/imx53-regs.h>
+#include <mach/imx51-regs.h>
 
 #include "imx-ipu-v3.h"
 #include "ipu-prv.h"
@@ -529,6 +531,31 @@ static int imx6_ipu_reset(struct ipu_soc *ipu)
 
 }
 
+static int imx5_ipu_reset(void __iomem *src_base)
+{
+	uint32_t val;
+	int ret;
+
+	val = ipureadl(src_base);
+	val |= (1 << 3);
+	ipuwritel("reset", val, src_base);
+
+	ret = wait_on_timeout(100 * MSECOND, !(readl(src_base) & (1 << 3)));
+
+	return ret;
+
+}
+
+static int imx51_ipu_reset(struct ipu_soc *ipu)
+{
+	return imx5_ipu_reset((void *)MX51_SRC_BASE_ADDR);
+}
+
+static int imx53_ipu_reset(struct ipu_soc *ipu)
+{
+	return imx5_ipu_reset((void *)MX53_SRC_BASE_ADDR);
+}
+
 struct ipu_devtype {
 	const char *name;
 	unsigned long cm_ofs;
@@ -554,6 +581,7 @@ static struct ipu_devtype ipu_type_imx51 = {
 	.dc_tmpl_ofs = 0x1f080000,
 	.vdi_ofs = 0x1e068000,
 	.type = IPUV3EX,
+	.reset = imx51_ipu_reset,
 };
 
 static struct ipu_devtype ipu_type_imx53 = {
@@ -567,6 +595,7 @@ static struct ipu_devtype ipu_type_imx53 = {
 	.dc_tmpl_ofs = 0x07080000,
 	.vdi_ofs = 0x06068000,
 	.type = IPUV3M,
+	.reset = imx53_ipu_reset,
 };
 
 static struct ipu_devtype ipu_type_imx6q = {