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authorJuergen Beisert <jbe@pengutronix.de>2013-04-05 14:04:31 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2013-04-09 08:44:06 +0200
commit0c8b031eada30761c0adf6dfce799283f449bfe7 (patch)
tree2c0eaac73cd5c47f39c6f19bc2ac35b79c8af4d1 /drivers/watchdog
parentc3995e85d2b6efdfd665ee420bc49c7436f11bed (diff)
downloadbarebox-0c8b031eada30761c0adf6dfce799283f449bfe7.tar.gz
ARM/MXS: add more ROM code related documentation
Commit 17176c2e2bba606190d9ae51943acb5701063573 adds a test of a new RTC register flag to distinguish a system reset and a wake up event. Shame on me, I have forgotten to define the newly used flag yet. While already here, I also try to document the other flags the RTC provides. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/watchdog')
-rw-r--r--drivers/watchdog/im28wd.c75
1 files changed, 74 insertions, 1 deletions
diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index 96cfe9a..6ae4cf8 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -33,16 +33,89 @@
#define MXS_RTC_WATCHDOG 0x50
+/* HW_RTC_PERSISTENT0 - holds bits used to configure various hardware settings */
#define MXS_RTC_PERSISTENT0 0x60
+
+/* FIXME */
+# define MXS_RTC_PERSISTENT0_SPARE_ANALOG (1 << 22)
/* dubious meaning from inside the SoC's firmware ROM */
# define MXS_RTC_PERSISTENT0_EXT_RST (1 << 21)
/* dubious meaning from inside the SoC's firmware ROM */
# define MXS_RTC_PERSISTENT0_THM_RST (1 << 20)
-
+/* reserved on i.MX28 */
+# define MXS_RTC_PERSISTENT0_RELEASE_GND (1 << 19)
+# define MXS_RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
+# define MXS_RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
+# define MXS_RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
+# define MXS_RTC_PERSISTENT0_LOWERBIAS (1 << 14)
+# define MXS_RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
+# define MXS_RTC_PERSISTENT0_MSEC_RES (1 << 8)
+# define MXS_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
+# define MXS_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
+# define MXS_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
+# define MXS_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
+# define MXS_RTC_PERSISTENT0_LCK_SECS (1 << 3)
+# define MXS_RTC_PERSISTENT0_ALARM_EN (1 << 2)
+# define MXS_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
+# define MXS_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
+
+/* HW_RTC_PERSISTENT1 - holds bits related to the ROM and redundant boot handling */
#define MXS_RTC_PERSISTENT1 0x70
+
+
+/*
+ * some of the following bits are for error reporting from ROM to the chained
+ * firmware. It seems, if the error reporting bits are not cleared when the
+ * chained firmware is running, the next time the following rule is active:
+ * "Loader enters recovery mode if any non-USB boot mode has an error.
+ * Which results into a system that seems not to start anymore.
+ */
+
/* dubious meaning from inside the SoC's firmware ROM */
# define MXS_RTC_PERSISTENT1_FORCE_UPDATER (1 << 31)
+/* names are from the i.MX28 datasheet. Undocumented behaviour */
+# define MXS_RTC_PERSISTENT1_ENUMERATE_500MA_TWICE (1 << 12)
+# define MXS_RTC_PERSISTENT1_USB_BOOT_PLAYER_MODE (1 << 11)
+# define MXS_RTC_PERSISTENT1_SKIP_CHECKDISK (1 << 10)
+# define MXS_RTC_PERSISTENT1_USB_LOW_POWER_MODE (1 << 9)
+# define MXS_RTC_PERSISTENT1_OTG_HNP_BIT (1 << 8)
+# define MXS_RTC_PERSISTENT1_OTG_ATL_ROLE_BIT (1 << 7)
+/*
+ * a few undocumented bits
+ */
+# define MXS_RTC_PERSISTENT1_SD_INIT_SEQ_2_ENABLE (1 << 6)
+# define MXS_RTC_PERSISTENT1_SD_CMD0_DISABLE (1 << 5)
+# define MXS_RTC_PERSISTENT1_SD_INIT_SEQ_1_DISABLE (1 << 4)
+/*
+ * If this bit is set, ROM puts the SD/MMC card in high-speed mode.
+ * If this bit is set, the ROM driver will use a maximum speed based on the
+ * results of device identification and limited by choices available in the
+ * SSP clock index.
+ */
+# define MXS_RTC_PERSISTENT1_SD_SPEED_ENABLE (1 << 3)
+/*
+ * The NAND driver sets this bit to indicate to the SDK that the boot image
+ * has ECC errors that reached the warning threshold. The SDK regenerates the
+ * firmware by copying it from the backup image. The SDK clears this bit.
+ * This bit had change its meaning from i.XM23 to i.MX28. Refer section
+ * 35.8 "NAND Boot Mode" for further details in the i.MX23 RM.
+ */
+# define MXS_RTC_PERSISTENT1_NAND_SDK_BLOCK_REWRITE (1 << 2)
+/*
+ * When this bit is set, ROM attempts to boot from the secondary image if the
+ * boot driver supports it. This bit is set by the ROM boot driver and cleared
+ * by the SDK after repair.
+ * If not reset, the ROM seems to continue to start from the secondary image
+ * which will fail forever if there is no secondary image
+ */
+# define MXS_RTC_PERSISTENT1_NAND_SECONDARY_BOOT (1 << 1)
+/*
+ * When this bit is set, the ROM code forces the system to boot in recovery
+ * mode, regardless of the selected mode. The ROM clears the bit.
+ */
+# define MXS_RTC_PERSISTENT1_FORCE_RECOVERY (1 << 0)
+
#define MXS_RTC_DEBUG 0xc0
#define WDOG_TICK_RATE 1000 /* the watchdog uses a 1 kHz clock rate */