remove unported includes and drivers

60 files changed, 0 insertions, 28880 deletions

diff --git a/drivers/net/3c589.c b/drivers/net/3c589.c
deleted file mode 100644
index 080b686e21..0000000000
--- a/drivers/net/3c589.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/*------------------------------------------------------------------------
- . 3c589.c
- . This is a driver for 3Com's 3C589 (Etherlink III) PCMCIA Ethernet device.
- .
- . (C) Copyright 2002
- . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- . Rolf Offermanns <rof@sysgo.de>
- .
- . This program is free software; you can redistribute it and/or modify
- . it under the terms of the GNU General Public License as published by
- . the Free Software Foundation; either version 2 of the License, or
- . (at your option) any later version.
- .
- . This program is distributed in the hope that it will be useful,
- . but WITHOUT ANY WARRANTY; without even the implied warranty of
- . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- . GNU General Public License for more details.
- .
- . You should have received a copy of the GNU General Public License
- . along with this program; if not, write to the Free Software
- . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- .
- ----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-
-#ifdef CONFIG_DRIVER_3C589
-
-#include "3c589.h"
-
-
-/* Use power-down feature of the chip */
-#define POWER_DOWN	0
-
-#define NO_AUTOPROBE
-
-static const char version[] =
-	"Your ad here! :P\n";
-
-
-#undef EL_DEBUG
-
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long int dword;
-/*------------------------------------------------------------------------
- .
- . Configuration options, for the experienced user to change.
- .
- -------------------------------------------------------------------------*/
-
-/*
- . Wait time for memory to be free.  This probably shouldn't be
- . tuned that much, as waiting for this means nothing else happens
- . in the system
-*/
-#define MEMORY_WAIT_TIME 16
-
-
-#if (EL_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if EL_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef EL_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-#define outb(args...)	mmio_outb(args)
-#define mmio_outb(value, addr)	(*((volatile byte *)(addr)) = value)
-
-#define inb(args...)	mmio_inb(args)
-#define mmio_inb(addr) (*((volatile byte *)(addr)))
-
-#define outw(args...)	mmio_outw(args)
-#define mmio_outw(value, addr)	(*((volatile word *)(addr)) = value)
-
-#define inw(args...)	mmio_inw(args)
-#define mmio_inw(addr) (*((volatile word *)(addr)))
-
-#define outsw(args...)	mmio_outsw(args)
-#define mmio_outsw(r,b,l)	({	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    mmio_outw( *(__b2 + __i), r); \
-					} \
-				})
-
-#define insw(args...)	mmio_insw(args)
-#define mmio_insw(r,b,l) 	({	int __i ;  \
-					word *__b2;  \
-					__b2 = (word *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = mmio_inw(r);  \
-					  mmio_inw(0);  \
-					};  \
-				})
-
-/*------------------------------------------------------------------------
- .
- . The internal workings of the driver.  If you are changing anything
- . here with the 3Com stuff, you should have the datasheet and know
- . what you are doing.
- .
- -------------------------------------------------------------------------*/
-#define EL_BASE_ADDR	0x20000000
-
-
-/* Offsets from base I/O address. */
-#define EL3_DATA	0x00
-#define EL3_TIMER	0x0a
-#define EL3_CMD		0x0e
-#define EL3_STATUS	0x0e
-
-#define EEPROM_READ	0x0080
-
-#define EL3WINDOW(win_num) mmio_outw(SelectWindow + (win_num), EL_BASE_ADDR + EL3_CMD)
-
-/* The top five bits written to EL3_CMD are a command, the lower
-   11 bits are the parameter, if applicable. */
-enum c509cmd {
-    TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
-    RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11,
-    TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
-    FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
-    SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
-    SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11,
-    StatsDisable = 22<<11, StopCoax = 23<<11,
-};
-
-enum c509status {
-    IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
-    TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
-    IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000
-};
-
-/* The SetRxFilter command accepts the following classes: */
-enum RxFilter {
-    RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
-};
-
-/* Register window 1 offsets, the window used in normal operation. */
-#define TX_FIFO		0x00
-#define RX_FIFO		0x00
-#define RX_STATUS 	0x08
-#define TX_STATUS 	0x0B
-#define TX_FREE		0x0C	/* Remaining free bytes in Tx buffer. */
-
-
-/*
-  Read a word from the EEPROM using the regular EEPROM access register.
-  Assume that we are in register window zero.
-*/
-static word read_eeprom(dword ioaddr, int index)
-{
-    int i;
-    outw(EEPROM_READ + index, ioaddr + 0xa);
-    /* Reading the eeprom takes 162 us */
-    for (i = 1620; i >= 0; i--)
-	if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0)
-	    break;
-    return inw(ioaddr + 0xc);
-}
-
-static void el_get_mac_addr( unsigned char *mac_addr )
-{
-	int i;
-	union
-	{
-		word w;
-		unsigned char b[2];
-	} wrd;
-	unsigned char old_window = inw( EL_BASE_ADDR + EL3_STATUS ) >> 13;
-	GO_WINDOW(0);
-	VX_BUSY_WAIT;
-	for (i = 0; i < 3; i++)
-	{
-		wrd.w = read_eeprom(EL_BASE_ADDR, 0xa+i);
-#ifdef __BIG_ENDIAN
-		mac_addr[2*i]   = wrd.b[0];
-		mac_addr[2*i+1] = wrd.b[1];
-#else
-		mac_addr[2*i]   = wrd.b[1];
-		mac_addr[2*i+1] = wrd.b[0];
-#endif
-	}
-	GO_WINDOW(old_window);
-	VX_BUSY_WAIT;
-}
-
-
-#if EL_DEBUG > 1
-static void print_packet( byte * buf, int length )
-{
-	int i;
-	int remainder;
-	int lines;
-
-	PRINTK2("Packet of length %d \n", length );
-
-	lines = length / 16;
-	remainder = length % 16;
-
-	for ( i = 0; i < lines ; i ++ ) {
-		int cur;
-
-		for ( cur = 0; cur < 8; cur ++ ) {
-			byte a, b;
-
-			a = *(buf ++ );
-			b = *(buf ++ );
-			PRINTK2("%02x%02x ", a, b );
-		}
-		PRINTK2("\n");
-	}
-	for ( i = 0; i < remainder/2 ; i++ ) {
-		byte a, b;
-
-		a = *(buf ++ );
-		b = *(buf ++ );
-		PRINTK2("%02x%02x ", a, b );
-	}
-	PRINTK2("\n");
-}
-#endif /* EL_DEBUG > 1 */
-
-
-/**************************************************************************
-ETH_RESET - Reset adapter
-***************************************************************************/
-static void el_reset(bd_t *bd)
-{
-	/***********************************************************
-			Reset 3Com 595 card
-	*************************************************************/
-	/* QUICK HACK
-	 * - adjust timing for 3c589
-	 * - enable io for PCMCIA */
-	outw(0x0004, 0xa0000018);
-	udelay(100);
-	outw(0x0041, 0x28010000);
-	udelay(100);
-
-	/* issue global reset */
-	outw(GLOBAL_RESET, BASE + VX_COMMAND);
-
-	/* must wait for at least 1ms */
-	udelay(100000000);
-
-	/* set mac addr */
-	{
-		unsigned char *mac_addr = bd->bi_enetaddr;
-		int i;
-
-		el_get_mac_addr( mac_addr );
-
-		GO_WINDOW(2);
-		VX_BUSY_WAIT;
-
-		printf("3C589 MAC Addr.: ");
-		for (i = 0; i < 6; i++)
-		{
-			printf("%02x", mac_addr[i]);
-			outb(mac_addr[i], BASE + VX_W2_ADDR_0 + i);
-			VX_BUSY_WAIT;
-		}
-		printf("\n\n");
-	}
-
-	/* set RX filter */
-	outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + VX_COMMAND);
-	VX_BUSY_WAIT;
-
-
-	/* set irq mask and read_zero */
-	outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
-		S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
-	VX_BUSY_WAIT;
-
-	outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
-		S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
-	VX_BUSY_WAIT;
-
-	/* enable TP Linkbeat */
-	GO_WINDOW(4);
-	VX_BUSY_WAIT;
-
-	outw( ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
-	VX_BUSY_WAIT;
-
-
-/*
- * Attempt to get rid of any stray interrupts that occured during
- * configuration.  On the i386 this isn't possible because one may
- * already be queued.  However, a single stray interrupt is
- * unimportant.
- */
-
-	outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
-	VX_BUSY_WAIT;
-
-	/* enable TX and RX */
-	outw( RX_ENABLE, BASE + VX_COMMAND );
-	VX_BUSY_WAIT;
-
-	outw( TX_ENABLE, BASE + VX_COMMAND );
-	VX_BUSY_WAIT;
-
-
-	/* print the diag. regs. */
-	PRINTK2("Diag. Regs\n");
-	PRINTK2("--> MEDIA_TYPE:   %04x\n", inw(BASE + VX_W4_MEDIA_TYPE));
-	PRINTK2("--> NET_DIAG:     %04x\n", inw(BASE + VX_W4_NET_DIAG));
-	PRINTK2("--> FIFO_DIAG:    %04x\n", inw(BASE + VX_W4_FIFO_DIAG));
-	PRINTK2("--> CTRLR_STATUS: %04x\n", inw(BASE + VX_W4_CTRLR_STATUS));
-	PRINTK2("\n\n");
-
-	/* enter working mode */
-	GO_WINDOW(1);
-	VX_BUSY_WAIT;
-
-	/* wait for another 1ms */
-	udelay(100000000);
-}
-
-
-/*-----------------------------------------------------------------
- .
- .  The driver can be entered at any of the following entry points.
- .
- .------------------------------------------------------------------  */
-
-extern int eth_init(bd_t *bd);
-extern void eth_halt(void);
-extern int eth_rx(void);
-extern int eth_send(volatile void *packet, int length);
-
-
-/*
- ------------------------------------------------------------
- .
- . Internal routines
- .
- ------------------------------------------------------------
-*/
-
-int eth_init(bd_t *bd)
-{
-	el_reset(bd);
-	return 0;
-}
-
-void eth_halt() {
-	return;
-}
-
-#define EDEBUG 1
-
-
-/**************************************************************************
-ETH_POLL - Wait for a frame
-***************************************************************************/
-
-int eth_rx()
-{
-	word status, rx_status, packet_size;
-
-	VX_BUSY_WAIT;
-
-	status = inw( BASE + VX_STATUS );
-
-	if ( (status & S_RX_COMPLETE) == 0 ) return 0; /* nothing to do */
-
-	/* Packet waiting -> check RX_STATUS */
-	rx_status = inw( BASE + VX_W1_RX_STATUS );
-
-	if ( rx_status & ERR_RX )
-	{
-		/* error in packet -> discard */
-		PRINTK("[ERROR] Invalid packet -> discarding\n");
-		PRINTK("-- error code 0x%02x\n", rx_status & ERR_MASK);
-		PRINTK("-- rx bytes 0x%04d\n", rx_status & ((1<<11) - 1));
-		PRINTK("[ERROR] Invalid packet -> discarding\n");
-		outw( RX_DISCARD_TOP_PACK, BASE + VX_COMMAND );
-		return 0;
-	}
-
-	/* correct pack. waiting in fifo */
-	packet_size = rx_status & RX_BYTES_MASK;
-
-	PRINTK("Correct packet waiting in fifo, size: %d\n", packet_size);
-
-	{
-		volatile word *packet_start = (word *)(BASE + VX_W1_RX_PIO_RD_1);
-		word *RcvBuffer = (word *)(NetRxPackets[0]);
-		int wcount = 0;
-
-		for (wcount = 0; wcount < (packet_size >> 1); wcount++)
-		{
-			*RcvBuffer++ = *(packet_start);
-		}
-
-		/* handle odd packets */
-		if ( packet_size & 1 )
-		{
-			*RcvBuffer++ = *(packet_start);
-		}
-	}
-
-	/* fifo should now be empty (besides the padding bytes) */
-	if ( ((*((word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK) > 3 )
-	{
-		PRINTK("[ERROR] Fifo not empty after packet read (remaining pkts: %d)\n",
-			(((*(word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK));
-	}
-
-	/* discard packet */
-	*((word *)(BASE + VX_COMMAND)) = RX_DISCARD_TOP_PACK;
-
-	/* Pass Packets to upper Layer */
-	NetReceive(NetRxPackets[0], packet_size);
-	return packet_size;
-}
-
-
-/**************************************************************************
-ETH_TRANSMIT - Transmit a frame
-***************************************************************************/
-static char padmap[] = {
-	0, 3, 2, 1};
-
-
-int eth_send(volatile void *packet, int length) {
-	int pad;
-	int status;
-	volatile word *buf = (word *)packet;
-	int dummy = 0;
-
-	/* padding stuff */
-	pad = padmap[length & 3];
-
-	PRINTK("eth_send(), length: %d\n", length);
-	/* drop acknowledgements */
-	while(( status=inb(EL_BASE_ADDR + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
-		if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) {
-			outw(TX_RESET, EL_BASE_ADDR + VX_COMMAND);
-			outw(TX_ENABLE, EL_BASE_ADDR + VX_COMMAND);
-			PRINTK("Bad status, resetting and reenabling transmitter\n");
-		}
-
-		outb(0x0, EL_BASE_ADDR + VX_W1_TX_STATUS);
-	}
-
-
-	while (inw(EL_BASE_ADDR + VX_W1_FREE_TX) < length + pad + 4) {
-		/* no room in FIFO */
-		if (dummy == 0)
-		{
-			PRINTK("No room in FIFO, waiting...\n");
-			dummy++;
-		}
-
-	}
-
-	PRINTK("    ---> FIFO ready\n");
-
-
-	outw(length, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
-
-	/* Second dword meaningless */
-	outw(0x0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
-
-#if EL_DEBUG > 1
-	print_packet((byte *)buf, length);
-#endif
-
-	/* write packet */
-	{
-		unsigned int i, totw;
-
-		totw = ((length + 1) >> 1);
-		PRINTK("Buffer: (totw = %d)\n", totw);
-		for (i = 0; i < totw; i++) {
-			outw( *(buf+i), EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
-			udelay(10);
-		}
-		if(totw & 1)
-		{	/* pad to double word length */
-			outw( 0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
-			udelay(10);
-		}
-		PRINTK("\n\n");
-	}
-
-	/* wait for Tx complete */
-	PRINTK("Waiting for Tx to complete...\n");
-	while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0)
-	{
-		udelay(10);
-	}
-	PRINTK("   ---> Tx completed, status = 0x%04x\n", status);
-
-	return length;
-}
-
-
-#endif /* CONFIG_DRIVER_3C589 */
diff --git a/drivers/net/3c589.h b/drivers/net/3c589.h
deleted file mode 100644
index 6735bf9f63..0000000000
--- a/drivers/net/3c589.h
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer. 2. The name
- * of the author may not be used to endorse or promote products derived from
- * this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- October 2, 1994
-
- Modified by: Andres Vega Garcia
-
- INRIA - Sophia Antipolis, France
- e-mail: avega@sophia.inria.fr
- finger: avega@pax.inria.fr
-
- */
-
-/*
- * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
- * 3c590 family.
- */
-
-/*
- * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp>
- * for etherboot
- * Mar. 14, 2000
-*/
-
-/*
- * Ethernet software status per interface.
- */
-
-/*
- * Some global constants
- */
-
-#define TX_INIT_RATE         16
-#define TX_INIT_MAX_RATE     64
-#define RX_INIT_LATENCY      64
-#define RX_INIT_EARLY_THRESH 64
-#define MIN_RX_EARLY_THRESHF   16 /* not less than ether_header */
-#define MIN_RX_EARLY_THRESHL   4
-
-#define EEPROMSIZE      0x40
-#define MAX_EEPROMBUSY  1000
-#define VX_LAST_TAG     0xd7
-#define VX_MAX_BOARDS   16
-#define VX_ID_PORT      0x100
-
-/*
- * some macros to acces long named fields
- */
-#define BASE 	(EL_BASE_ADDR)
-
-/*
- * Commands to read/write EEPROM trough EEPROM command register (Window 0,
- * Offset 0xa)
- */
-#define EEPROM_CMD_RD    0x0080	/* Read:  Address required (5 bits) */
-#define EEPROM_CMD_WR    0x0040	/* Write: Address required (5 bits) */
-#define EEPROM_CMD_ERASE 0x00c0	/* Erase: Address required (5 bits) */
-#define EEPROM_CMD_EWEN  0x0030	/* Erase/Write Enable: No data required */
-
-#define EEPROM_BUSY		(1<<15)
-
-/*
- * Some short functions, worth to let them be a macro
- */
-
-/**************************************************************************
- *									  *
- * These define the EEPROM data structure.  They are used in the probe
- * function to verify the existence of the adapter after having sent
- * the ID_Sequence.
- *
- * There are others but only the ones we use are defined here.
- *
- **************************************************************************/
-
-#define EEPROM_NODE_ADDR_0	0x0	/* Word */
-#define EEPROM_NODE_ADDR_1	0x1	/* Word */
-#define EEPROM_NODE_ADDR_2	0x2	/* Word */
-#define EEPROM_PROD_ID		0x3	/* 0x9[0-f]50 */
-#define EEPROM_MFG_ID		0x7	/* 0x6d50 */
-#define EEPROM_ADDR_CFG		0x8	/* Base addr */
-#define EEPROM_RESOURCE_CFG	0x9	/* IRQ. Bits 12-15 */
-#define EEPROM_OEM_ADDR_0	0xa	/* Word */
-#define EEPROM_OEM_ADDR_1	0xb	/* Word */
-#define EEPROM_OEM_ADDR_2	0xc	/* Word */
-#define EEPROM_SOFT_INFO_2	0xf     /* Software information 2 */
-
-#define NO_RX_OVN_ANOMALY       (1<<5)
-
-/**************************************************************************
- *										  *
- * These are the registers for the 3Com 3c509 and their bit patterns when *
- * applicable.  They have been taken out the the "EtherLink III Parallel  *
- * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
- * from 3com.								  *
- *										  *
- **************************************************************************/
-
-#define VX_COMMAND		0x0e	/* Write. BASE+0x0e is always a
-					 * command reg. */
-#define VX_STATUS		0x0e	/* Read. BASE+0x0e is always status
-					 * reg. */
-#define VX_WINDOW		0x0f	/* Read. BASE+0x0f is always window
-					 * reg. */
-/*
- * Window 0 registers. Setup.
- */
-/* Write */
-#define VX_W0_EEPROM_DATA	0x0c
-#define VX_W0_EEPROM_COMMAND	0x0a
-#define VX_W0_RESOURCE_CFG	0x08
-#define VX_W0_ADDRESS_CFG	0x06
-#define VX_W0_CONFIG_CTRL	0x04
-	/* Read */
-#define VX_W0_PRODUCT_ID	0x02
-#define VX_W0_MFG_ID		0x00
-
-
-/*
- * Window 1 registers. Operating Set.
- */
-/* Write */
-#define VX_W1_TX_PIO_WR_2	0x02
-#define VX_W1_TX_PIO_WR_1	0x00
-/* Read */
-#define VX_W1_FREE_TX		0x0c
-#define VX_W1_TX_STATUS		0x0b	/* byte */
-#define VX_W1_TIMER		0x0a	/* byte */
-#define VX_W1_RX_STATUS		0x08
-#define VX_W1_RX_PIO_RD_2	0x02
-#define VX_W1_RX_PIO_RD_1	0x00
-
-/*
- * Window 2 registers. Station Address Setup/Read
- */
-/* Read/Write */
-#define VX_W2_ADDR_5		0x05
-#define VX_W2_ADDR_4		0x04
-#define VX_W2_ADDR_3		0x03
-#define VX_W2_ADDR_2		0x02
-#define VX_W2_ADDR_1		0x01
-#define VX_W2_ADDR_0		0x00
-
-/*
- * Window 3 registers. FIFO Management.
- */
-/* Read */
-#define VX_W3_INTERNAL_CFG	0x00
-#define VX_W3_RESET_OPT		0x08
-#define VX_W3_FREE_TX		0x0c
-#define VX_W3_FREE_RX		0x0a
-
-/*
- * Window 4 registers. Diagnostics.
- */
-/* Read/Write */
-#define VX_W4_MEDIA_TYPE	0x0a
-#define VX_W4_CTRLR_STATUS	0x08
-#define VX_W4_NET_DIAG		0x06
-#define VX_W4_FIFO_DIAG		0x04
-#define VX_W4_HOST_DIAG		0x02
-#define VX_W4_TX_DIAG		0x00
-
-/*
- * Window 5 Registers.  Results and Internal status.
- */
-/* Read */
-#define VX_W5_READ_0_MASK	0x0c
-#define VX_W5_INTR_MASK		0x0a
-#define VX_W5_RX_FILTER		0x08
-#define VX_W5_RX_EARLY_THRESH	0x06
-#define VX_W5_TX_AVAIL_THRESH	0x02
-#define VX_W5_TX_START_THRESH	0x00
-
-/*
- * Window 6 registers. Statistics.
- */
-/* Read/Write */
-#define TX_TOTAL_OK		0x0c
-#define RX_TOTAL_OK		0x0a
-#define TX_DEFERRALS		0x08
-#define RX_FRAMES_OK		0x07
-#define TX_FRAMES_OK		0x06
-#define RX_OVERRUNS		0x05
-#define TX_COLLISIONS		0x04
-#define TX_AFTER_1_COLLISION	0x03
-#define TX_AFTER_X_COLLISIONS	0x02
-#define TX_NO_SQE		0x01
-#define TX_CD_LOST		0x00
-
-/****************************************
- *
- * Register definitions.
- *
- ****************************************/
-
-/*
- * Command register. All windows.
- *
- * 16 bit register.
- *     15-11:  5-bit code for command to be executed.
- *     10-0:   11-bit arg if any. For commands with no args;
- *	      this can be set to anything.
- */
-#define GLOBAL_RESET		(unsigned short) 0x0000	/* Wait at least 1ms
-							 * after issuing */
-#define WINDOW_SELECT		(unsigned short) (0x1<<11)
-#define START_TRANSCEIVER	(unsigned short) (0x2<<11)	/* Read ADDR_CFG reg to
-							 * determine whether
-							 * this is needed. If
-							 * so; wait 800 uSec
-							 * before using trans-
-							 * ceiver. */
-#define RX_DISABLE		(unsigned short) (0x3<<11)	/* state disabled on
-							 * power-up */
-#define RX_ENABLE		(unsigned short) (0x4<<11)
-#define RX_RESET		(unsigned short) (0x5<<11)
-#define RX_DISCARD_TOP_PACK	(unsigned short) (0x8<<11)
-#define TX_ENABLE		(unsigned short) (0x9<<11)
-#define TX_DISABLE		(unsigned short) (0xa<<11)
-#define TX_RESET		(unsigned short) (0xb<<11)
-#define REQ_INTR		(unsigned short) (0xc<<11)
-/*
- * The following C_* acknowledge the various interrupts. Some of them don't
- * do anything.  See the manual.
- */
-#define ACK_INTR		(unsigned short) (0x6800)
-#	define C_INTR_LATCH	(unsigned short) (ACK_INTR|0x1)
-#	define C_CARD_FAILURE	(unsigned short) (ACK_INTR|0x2)
-#	define C_TX_COMPLETE	(unsigned short) (ACK_INTR|0x4)
-#	define C_TX_AVAIL	(unsigned short) (ACK_INTR|0x8)
-#	define C_RX_COMPLETE	(unsigned short) (ACK_INTR|0x10)
-#	define C_RX_EARLY	(unsigned short) (ACK_INTR|0x20)
-#	define C_INT_RQD		(unsigned short) (ACK_INTR|0x40)
-#	define C_UPD_STATS	(unsigned short) (ACK_INTR|0x80)
-#define SET_INTR_MASK		(unsigned short) (0xe<<11)
-#define SET_RD_0_MASK		(unsigned short) (0xf<<11)
-#define SET_RX_FILTER		(unsigned short) (0x10<<11)
-#	define FIL_INDIVIDUAL	(unsigned short) (0x1)
-#	define FIL_MULTICAST     (unsigned short) (0x02)
-#	define FIL_BRDCST        (unsigned short) (0x04)
-#	define FIL_PROMISC       (unsigned short) (0x08)
-#define SET_RX_EARLY_THRESH	(unsigned short) (0x11<<11)
-#define SET_TX_AVAIL_THRESH	(unsigned short) (0x12<<11)
-#define SET_TX_START_THRESH	(unsigned short) (0x13<<11)
-#define STATS_ENABLE		(unsigned short) (0x15<<11)
-#define STATS_DISABLE		(unsigned short) (0x16<<11)
-#define STOP_TRANSCEIVER	(unsigned short) (0x17<<11)
-
-/*
- * Status register. All windows.
- *
- *     15-13:  Window number(0-7).
- *     12:     Command_in_progress.
- *     11:     reserved.
- *     10:     reserved.
- *     9:      reserved.
- *     8:      reserved.
- *     7:      Update Statistics.
- *     6:      Interrupt Requested.
- *     5:      RX Early.
- *     4:      RX Complete.
- *     3:      TX Available.
- *     2:      TX Complete.
- *     1:      Adapter Failure.
- *     0:      Interrupt Latch.
- */
-#define S_INTR_LATCH		(unsigned short) (0x1)
-#define S_CARD_FAILURE		(unsigned short) (0x2)
-#define S_TX_COMPLETE		(unsigned short) (0x4)
-#define S_TX_AVAIL		(unsigned short) (0x8)
-#define S_RX_COMPLETE		(unsigned short) (0x10)
-#define S_RX_EARLY		(unsigned short) (0x20)
-#define S_INT_RQD		(unsigned short) (0x40)
-#define S_UPD_STATS		(unsigned short) (0x80)
-#define S_COMMAND_IN_PROGRESS	(unsigned short) (0x1000)
-
-#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
-
-/* Address Config. Register.
- * Window 0/Port 06
- */
-
-#define ACF_CONNECTOR_BITS	14
-#define ACF_CONNECTOR_UTP	0
-#define ACF_CONNECTOR_AUI	1
-#define ACF_CONNECTOR_BNC	3
-
-#define INTERNAL_CONNECTOR_BITS 20
-#define INTERNAL_CONNECTOR_MASK 0x01700000
-
-/*
- * FIFO Registers. RX Status.
- *
- *     15:     Incomplete or FIFO empty.
- *     14:     1: Error in RX Packet   0: Incomplete or no error.
- *     13-11:  Type of error.
- *	      1000 = Overrun.
- *	      1011 = Run Packet Error.
- *	      1100 = Alignment Error.
- *	      1101 = CRC Error.
- *	      1001 = Oversize Packet Error (>1514 bytes)
- *	      0010 = Dribble Bits.
- *	      (all other error codes, no errors.)
- *
- *     10-0:   RX Bytes (0-1514)
- */
-#define ERR_INCOMPLETE  (unsigned short) (0x8000)
-#define ERR_RX          (unsigned short) (0x4000)
-#define ERR_MASK        (unsigned short) (0x7800)
-#define ERR_OVERRUN     (unsigned short) (0x4000)
-#define ERR_RUNT        (unsigned short) (0x5800)
-#define ERR_ALIGNMENT   (unsigned short) (0x6000)
-#define ERR_CRC         (unsigned short) (0x6800)
-#define ERR_OVERSIZE    (unsigned short) (0x4800)
-#define ERR_DRIBBLE     (unsigned short) (0x1000)
-
-/*
- * TX Status.
- *
- *   Reports the transmit status of a completed transmission. Writing this
- *   register pops the transmit completion stack.
- *
- *   Window 1/Port 0x0b.
- *
- *     7:      Complete
- *     6:      Interrupt on successful transmission requested.
- *     5:      Jabber Error (TP Only, TX Reset required. )
- *     4:      Underrun (TX Reset required. )
- *     3:      Maximum Collisions.
- *     2:      TX Status Overflow.
- *     1-0:    Undefined.
- *
- */
-#define TXS_COMPLETE		0x80
-#define TXS_INTR_REQ		0x40
-#define TXS_JABBER		0x20
-#define TXS_UNDERRUN		0x10
-#define TXS_MAX_COLLISION	0x8
-#define TXS_STATUS_OVERFLOW	0x4
-
-#define RS_AUI			(1<<5)
-#define RS_BNC			(1<<4)
-#define RS_UTP			(1<<3)
-#define	RS_T4			(1<<0)
-#define	RS_TX			(1<<1)
-#define	RS_FX			(1<<2)
-#define	RS_MII			(1<<6)
-
-
-/*
- * FIFO Status (Window 4)
- *
- *   Supports FIFO diagnostics
- *
- *   Window 4/Port 0x04.1
- *
- *     15:	1=RX receiving (RO). Set when a packet is being received
- *		into the RX FIFO.
- *     14:	Reserved
- *     13:	1=RX underrun (RO). Generates Adapter Failure interrupt.
- *		Requires RX Reset or Global Reset command to recover.
- *		It is generated when you read past the end of a packet -
- *		reading past what has been received so far will give bad
- *		data.
- *     12:	1=RX status overrun (RO). Set when there are already 8
- *		packets in the RX FIFO. While this bit is set, no additional
- *		packets are received. Requires no action on the part of
- *		the host. The condition is cleared once a packet has been
- *		read out of the RX FIFO.
- *     11:	1=RX overrun (RO). Set when the RX FIFO is full (there
- *		may not be an overrun packet yet). While this bit is set,
- *		no additional packets will be received (some additional
- *		bytes can still be pending between the wire and the RX
- *		FIFO). Requires no action on the part of the host. The
- *		condition is cleared once a few bytes have been read out
- *		from the RX FIFO.
- *     10:	1=TX overrun (RO). Generates adapter failure interrupt.
- *		Requires TX Reset or Global Reset command to recover.
- *		Disables Transmitter.
- *     9-8:	Unassigned.
- *     7-0:	Built in self test bits for the RX and TX FIFO's.
- */
-#define FIFOS_RX_RECEIVING	(unsigned short) 0x8000
-#define FIFOS_RX_UNDERRUN	(unsigned short) 0x2000
-#define FIFOS_RX_STATUS_OVERRUN	(unsigned short) 0x1000
-#define FIFOS_RX_OVERRUN	(unsigned short) 0x0800
-#define FIFOS_TX_OVERRUN	(unsigned short) 0x0400
-
-/*
- * Misc defines for various things.
- */
-#define TAG_ADAPTER                     0xd0
-#define ACTIVATE_ADAPTER_TO_CONFIG      0xff
-#define ENABLE_DRQ_IRQ                  0x0001
-#define MFG_ID                          0x506d  /* `TCM' */
-#define PROD_ID                         0x5090
-#define GO_WINDOW(x)		outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
-#define JABBER_GUARD_ENABLE	0x40
-#define LINKBEAT_ENABLE		0x80
-#define	ENABLE_UTP		(JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
-#define DISABLE_UTP		0x0
-#define RX_BYTES_MASK		(unsigned short) (0x07ff)
-#define RX_ERROR        0x4000
-#define RX_INCOMPLETE   0x8000
-#define TX_INDICATE		1<<15
-#define is_eeprom_busy(b)	(inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY)
-
-#define	VX_IOSIZE	0x20
-
-#define VX_CONNECTORS 8
-
-/*
- * Local variables:
- *  c-basic-offset: 8
- * End:
- */
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
deleted file mode 100644
index f8284093e0..0000000000
--- a/drivers/net/4xx_enet.c
+++ /dev/null
@@ -1,1701 +0,0 @@
-/*-----------------------------------------------------------------------------+
- *
- *	 This source code has been made available to you by IBM on an AS-IS
- *	 basis.	 Anyone receiving this source is licensed under IBM
- *	 copyrights to use it in any way he or she deems fit, including
- *	 copying it, modifying it, compiling it, and redistributing it either
- *	 with or without modifications.	 No license under IBM patents or
- *	 patent applications is to be implied by the copyright license.
- *
- *	 Any user of this software should understand that IBM cannot provide
- *	 technical support for this software and will not be responsible for
- *	 any consequences resulting from the use of this software.
- *
- *	 Any person who transfers this source code or any derivative work
- *	 must include the IBM copyright notice, this paragraph, and the
- *	 preceding two paragraphs in the transferred software.
- *
- *	 COPYRIGHT   I B M   CORPORATION 1995
- *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- *
- *  File Name:	enetemac.c
- *
- *  Function:	Device driver for the ethernet EMAC3 macro on the 405GP.
- *
- *  Author:	Mark Wisner
- *
- *  Change Activity-
- *
- *  Date	Description of Change					    BY
- *  ---------	---------------------					    ---
- *  05-May-99	Created							    MKW
- *  27-Jun-99	Clean up						    JWB
- *  16-Jul-99	Added MAL error recovery and better IP packet handling	    MKW
- *  29-Jul-99	Added Full duplex support				    MKW
- *  06-Aug-99	Changed names for Mal CR reg				    MKW
- *  23-Aug-99	Turned off SYE when running at 10Mbs			    MKW
- *  24-Aug-99	Marked descriptor empty after call_xlc			    MKW
- *  07-Sep-99	Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16	    MCG
- *		to avoid chaining maximum sized packets. Push starting
- *		RX descriptor address up to the next cache line boundary.
- *  16-Jan-00	Added support for booting with IP of 0x0		    MKW
- *  15-Mar-00	Updated enetInit() to enable broadcast addresses in the
- *		EMAC_RXM register.					    JWB
- *  12-Mar-01	anne-sophie.harnois@nextream.fr
- *		 - Variables are compatible with those already defined in
- *		  include/net.h
- *		- Receive buffer descriptor ring is used to send buffers
- *		  to the user
- *		- Info print about send/received/handled packet number if
- *		  INFO_405_ENET is set
- *  17-Apr-01	stefan.roese@esd-electronics.com
- *		- MAL reset in "eth_halt" included
- *		- Enet speed and duplex output now in one line
- *  08-May-01	stefan.roese@esd-electronics.com
- *		- MAL error handling added (eth_init called again)
- *  13-Nov-01	stefan.roese@esd-electronics.com
- *		- Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- *  04-Jan-02	stefan.roese@esd-electronics.com
- *		- Wait for PHY auto negotiation to complete added
- *  06-Feb-02	stefan.roese@esd-electronics.com
- *		- Bug fixed in waiting for auto negotiation to complete
- *  26-Feb-02	stefan.roese@esd-electronics.com
- *		- rx and tx buffer descriptors now allocated (no fixed address
- *		  used anymore)
- *  17-Jun-02	stefan.roese@esd-electronics.com
- *		- MAL error debug printf 'M' removed (rx de interrupt may
- *		  occur upon many incoming packets with only 4 rx buffers).
- *-----------------------------------------------------------------------------*
- *  17-Nov-03	travis.sawyer@sandburst.com
- *		- ported from 405gp_enet.c to utilized upto 4 EMAC ports
- *		  in the 440GX.	 This port should work with the 440GP
- *		  (2 EMACs) also
- *  15-Aug-05	sr@denx.de
- *		- merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
-		  now handling all 4xx cpu's.
- *-----------------------------------------------------------------------------*/
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <commproc.h>
-#include <ppc4xx.h>
-#include <ppc4xx_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include "vecnum.h"
-
-/*
- * Only compile for platform with AMCC EMAC ethernet controller and
- * network support enabled.
- * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
- */
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
-
-#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
-#error "CONFIG_NET_MULTI has to be defined for NetConsole"
-#endif
-
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
-
-/* Ethernet Transmit and Receive Buffers */
-/* AS.HARNOIS
- * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-#define ENET_MAX_MTU	       PKTSIZE
-#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
-
-/*-----------------------------------------------------------------------------+
- * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
- * Interrupt Controller).
- *-----------------------------------------------------------------------------*/
-#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE  | UIC_MAL_RXDE)
-#define MAL_UIC_DEF  (UIC_MAL_RXEOB | MAL_UIC_ERR)
-#define EMAC_UIC_DEF UIC_ENET
-#define EMAC_UIC_DEF1 UIC_ENET1
-#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
-
-#undef INFO_4XX_ENET
-
-#define BI_PHYMODE_NONE	 0
-#define BI_PHYMODE_ZMII	 1
-#define BI_PHYMODE_RGMII 2
-#define BI_PHYMODE_GMII  3
-#define BI_PHYMODE_RTBI  4
-#define BI_PHYMODE_TBI   5
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define BI_PHYMODE_SMII  6
-#define BI_PHYMODE_MII   7
-#endif
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Global variables. TX and RX descriptors and buffers.
- *-----------------------------------------------------------------------------*/
-/* IER globals */
-static uint32_t mal_ier;
-
-#if !defined(CONFIG_NET_MULTI)
-struct eth_device *emac0_dev = NULL;
-#endif
-
-/*
- * Get count of EMAC devices (doesn't have to be the max. possible number
- * supported by the cpu)
- */
-#if defined(CONFIG_HAS_ETH3)
-#define LAST_EMAC_NUM	4
-#elif defined(CONFIG_HAS_ETH2)
-#define LAST_EMAC_NUM	3
-#elif defined(CONFIG_HAS_ETH1)
-#define LAST_EMAC_NUM	2
-#else
-#define LAST_EMAC_NUM	1
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes and externals.
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
-
-int enetInt (struct eth_device *dev);
-static void mal_err (struct eth_device *dev, unsigned long isr,
-		     unsigned long uic, unsigned long maldef,
-		     unsigned long mal_errr);
-static void emac_err (struct eth_device *dev, unsigned long isr);
-
-extern int phy_setup_aneg (char *devname, unsigned char addr);
-extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short *value);
-extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value);
-
-/*-----------------------------------------------------------------------------+
-| ppc_4xx_eth_halt
-| Disable MAL channel, and EMACn
-+-----------------------------------------------------------------------------*/
-static void ppc_4xx_eth_halt (struct eth_device *dev)
-{
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-	uint32_t failsafe = 10000;
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	unsigned long mfr;
-#endif
-
-	out32 (EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */
-
-	/* 1st reset MAL channel */
-	/* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
-#else
-	mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-#endif
-	mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-
-	/* wait for reset */
-	while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
-		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
-		failsafe--;
-		if (failsafe == 0)
-			break;
-	}
-
-	/* EMAC RESET */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	/* provide clocks for EMAC internal loopback  */
-	mfsdr (sdr_mfr, mfr);
-	mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
-	mtsdr(sdr_mfr, mfr);
-#endif
-
-	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	/* remove clocks for EMAC internal loopback  */
-	mfsdr (sdr_mfr, mfr);
-	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
-	mtsdr(sdr_mfr, mfr);
-#endif
-
-
-#ifndef CONFIG_NETCONSOLE
-	hw_p->print_speed = 1;	/* print speed message again next time */
-#endif
-
-	return;
-}
-
-#if defined (CONFIG_440GX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
-	unsigned long pfc1;
-	unsigned long zmiifer;
-	unsigned long rmiifer;
-
-	mfsdr(sdr_pfc1, pfc1);
-	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
-
-	zmiifer = 0;
-	rmiifer = 0;
-
-	switch (pfc1) {
-	case 1:
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
-		break;
-	case 2:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
-		break;
-	case 3:
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 4:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
-		break;
-	case 5:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
-		break;
-	case 6:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		break;
-	case 0:
-	default:
-		zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
-		break;
-	}
-
-	/* Ensure we setup mdio for this devnum and ONLY this devnum */
-	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-
-	out32 (ZMII_FER, zmiifer);
-	out32 (RGMII_FER, rmiifer);
-
-	return ((int)pfc1);
-}
-#endif	/* CONFIG_440_GX */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
-	unsigned long zmiifer=0x0;
-
-	/*
-	 * Right now only 2*RGMII is supported. Please extend when needed.
-	 * sr - 2006-08-29
-	 */
-	switch (1) {
-	case 0:
-		/* 1 x GMII port */
-		out32 (ZMII_FER, 0x00);
-		out32 (RGMII_FER, 0x00000037);
-		bis->bi_phymode[0] = BI_PHYMODE_GMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	case 1:
-		/* 2 x RGMII ports */
-		out32 (ZMII_FER, 0x00);
-		out32 (RGMII_FER, 0x00000055);
-		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
-		break;
-	case 2:
-		/* 2 x SMII ports */
-
-		break;
-	default:
-		break;
-	}
-
-	/* Ensure we setup mdio for this devnum and ONLY this devnum */
-	zmiifer = in32 (ZMII_FER);
-	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-	out32 (ZMII_FER, zmiifer);
-
-	return ((int)0x0);
-}
-#endif	/* CONFIG_440EPX */
-
-static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
-{
-	int i, j;
-	unsigned long reg = 0;
-	unsigned long msr;
-	unsigned long speed;
-	unsigned long duplex;
-	unsigned long failsafe;
-	unsigned mode_reg;
-	unsigned short devnum;
-	unsigned short reg_short;
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-	sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	int ethgroup = -1;
-#endif
-#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
-	unsigned long mfr;
-#endif
-
-
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	/* before doing anything, figure out if we have a MAC address */
-	/* if not, bail */
-	if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
-		printf("ERROR: ethaddr not set!\n");
-		return -1;
-	}
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-	/* Need to get the OPB frequency so we can access the PHY */
-	get_sys_info (&sysinfo);
-#endif
-
-	msr = mfmsr ();
-	mtmsr (msr & ~(MSR_EE));	/* disable interrupts */
-
-	devnum = hw_p->devnum;
-
-#ifdef INFO_4XX_ENET
-	/* AS.HARNOIS
-	 * We should have :
-	 * hw_p->stats.pkts_handled <=	hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
-	 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
-	 * is possible that new packets (without relationship with
-	 * current transfer) have got the time to arrived before
-	 * netloop calls eth_halt
-	 */
-	printf ("About preceeding transfer (eth%d):\n"
-		"- Sent packet number %d\n"
-		"- Received packet number %d\n"
-		"- Handled packet number %d\n",
-		hw_p->devnum,
-		hw_p->stats.pkts_tx,
-		hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
-
-	hw_p->stats.pkts_tx = 0;
-	hw_p->stats.pkts_rx = 0;
-	hw_p->stats.pkts_handled = 0;
-	hw_p->print_speed = 1;	/* print speed message again next time */
-#endif
-
-	hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
-	hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
-
-	hw_p->rx_slot = 0;	/* MAL Receive Slot */
-	hw_p->rx_i_index = 0;	/* Receive Interrupt Queue Index */
-	hw_p->rx_u_index = 0;	/* Receive User Queue Index */
-
-	hw_p->tx_slot = 0;	/* MAL Transmit Slot */
-	hw_p->tx_i_index = 0;	/* Transmit Interrupt Queue Index */
-	hw_p->tx_u_index = 0;	/* Transmit User Queue Index */
-
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
-	/* set RMII mode */
-	/* NOTE: 440GX spec states that mode is mutually exclusive */
-	/* NOTE: Therefore, disable all other EMACS, since we handle */
-	/* NOTE: only one emac at a time */
-	reg = 0;
-	out32 (ZMII_FER, 0);
-	udelay (100);
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#elif defined(CONFIG_440GP)
-	/* set RMII mode */
-	out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
-#else
-	if ((devnum == 0) || (devnum == 1)) {
-		out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-	} else { /* ((devnum == 2) || (devnum == 3)) */
-		out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
-		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
-				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
-	}
-#endif
-
-	out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-
-	__asm__ volatile ("eieio");
-
-	/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	/* provide clocks for EMAC internal loopback  */
-	mfsdr (sdr_mfr, mfr);
-	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
-	mtsdr(sdr_mfr, mfr);
-#endif
-
-	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-	__asm__ volatile ("eieio");
-
-	failsafe = 1000;
-	while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
-		udelay (1000);
-		failsafe--;
-	}
-	if (failsafe <= 0)
-		printf("\nProblem resetting EMAC!\n");
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	/* remove clocks for EMAC internal loopback  */
-	mfsdr (sdr_mfr, mfr);
-	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
-	mtsdr(sdr_mfr, mfr);
-#endif
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-	/* Whack the M1 register */
-	mode_reg = 0x0;
-	mode_reg &= ~0x00000038;
-	if (sysinfo.freqOPB <= 50000000);
-	else if (sysinfo.freqOPB <= 66666667)
-		mode_reg |= EMAC_M1_OBCI_66;
-	else if (sysinfo.freqOPB <= 83333333)
-		mode_reg |= EMAC_M1_OBCI_83;
-	else if (sysinfo.freqOPB <= 100000000)
-		mode_reg |= EMAC_M1_OBCI_100;
-	else
-		mode_reg |= EMAC_M1_OBCI_GT100;
-
-	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-
-	/* wait for PHY to complete auto negotiation */
-	reg_short = 0;
-#ifndef CONFIG_CS8952_PHY
-	switch (devnum) {
-	case 0:
-		reg = CONFIG_PHY_ADDR;
-		break;
-#if defined (CONFIG_PHY1_ADDR)
-	case 1:
-		reg = CONFIG_PHY1_ADDR;
-		break;
-#endif
-#if defined (CONFIG_440GX)
-	case 2:
-		reg = CONFIG_PHY2_ADDR;
-		break;
-	case 3:
-		reg = CONFIG_PHY3_ADDR;
-		break;
-#endif
-	default:
-		reg = CONFIG_PHY_ADDR;
-		break;
-	}
-
-	bis->bi_phynum[devnum] = reg;
-
-#if defined(CONFIG_PHY_RESET)
-	/*
-	 * Reset the phy, only if its the first time through
-	 * otherwise, just check the speeds & feeds
-	 */
-	if (hw_p->first_init == 0) {
-#if defined(CONFIG_M88E1111_PHY)
-		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
-		miiphy_write (dev->name, reg, 0x18, 0x4101);
-		miiphy_write (dev->name, reg, 0x09, 0x0e00);
-		miiphy_write (dev->name, reg, 0x04, 0x01e1);
-#endif
-		miiphy_reset (dev->name, reg);
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-
-#if defined(CONFIG_CIS8201_PHY)
-		/*
-		 * Cicada 8201 PHY needs to have an extended register whacked
-		 * for RGMII mode.
-		 */
-		if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
-#if defined(CONFIG_CIS8201_SHORT_ETCH)
-			miiphy_write (dev->name, reg, 23, 0x1300);
-#else
-			miiphy_write (dev->name, reg, 23, 0x1000);
-#endif
-			/*
-			 * Vitesse VSC8201/Cicada CIS8201 errata:
-			 * Interoperability problem with Intel 82547EI phys
-			 * This work around (provided by Vitesse) changes
-			 * the default timer convergence from 8ms to 12ms
-			 */
-			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
-			miiphy_write (dev->name, reg, 0x08, 0x0200);
-			miiphy_write (dev->name, reg, 0x1f, 0x52b5);
-			miiphy_write (dev->name, reg, 0x02, 0x0004);
-			miiphy_write (dev->name, reg, 0x01, 0x0671);
-			miiphy_write (dev->name, reg, 0x00, 0x8fae);
-			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
-			miiphy_write (dev->name, reg, 0x08, 0x0000);
-			miiphy_write (dev->name, reg, 0x1f, 0x0000);
-			/* end Vitesse/Cicada errata */
-		}
-#endif
-#endif
-		/* Start/Restart autonegotiation */
-		phy_setup_aneg (dev->name, reg);
-		udelay (1000);
-	}
-#endif /* defined(CONFIG_PHY_RESET) */
-
-	miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
-
-	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
-	 */
-	if ((reg_short & PHY_BMSR_AUTN_ABLE)
-	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
-		puts ("Waiting for PHY auto negotiation to complete");
-		i = 0;
-		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
-			/*
-			 * Timeout reached ?
-			 */
-			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-				puts (" TIMEOUT !\n");
-				break;
-			}
-
-			if ((i++ % 1000) == 0) {
-				putc ('.');
-			}
-			udelay (1000);	/* 1 ms */
-			miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
-
-		}
-		puts (" done\n");
-		udelay (500000);	/* another 500 ms (results in faster booting) */
-	}
-#endif /* #ifndef CONFIG_CS8952_PHY */
-
-	speed = miiphy_speed (dev->name, reg);
-	duplex = miiphy_duplex (dev->name, reg);
-
-	if (hw_p->print_speed) {
-		hw_p->print_speed = 0;
-		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
-			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
-	}
-
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
-    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	mfsdr(sdr_mfr, reg);
-	if (speed == 100) {
-		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
-	} else {
-		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
-	}
-	mtsdr(sdr_mfr, reg);
-#endif
-
-	/* Set ZMII/RGMII speed according to the phy link speed */
-	reg = in32 (ZMII_SSR);
-	if ( (speed == 100) || (speed == 1000) )
-		out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
-	else
-		out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
-
-	if ((devnum == 2) || (devnum == 3)) {
-		if (speed == 1000)
-			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
-		else if (speed == 100)
-			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
-		else if (speed == 10)
-			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
-		else {
-			printf("Error in RGMII Speed\n");
-			return -1;
-		}
-		out32 (RGMII_SSR, reg);
-	}
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	if (speed == 1000)
-		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
-	else if (speed == 100)
-		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
-	else if (speed == 10)
-		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
-	else {
-		printf("Error in RGMII Speed\n");
-		return -1;
-	}
-	out32 (RGMII_SSR, reg);
-#endif
-
-	/* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
-	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
-#else
-	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
-	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
-	if (get_pvr() == PVR_440GP_RB) {
-		mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
-	}
-#endif
-
-	/* Free "old" buffers */
-	if (hw_p->alloc_tx_buf)
-		free (hw_p->alloc_tx_buf);
-	if (hw_p->alloc_rx_buf)
-		free (hw_p->alloc_rx_buf);
-
-	/*
-	 * Malloc MAL buffer desciptors, make sure they are
-	 * aligned on cache line boundary size
-	 * (401/403/IOP480 = 16, 405 = 32)
-	 * and doesn't cross cache block boundaries.
-	 */
-	hw_p->alloc_tx_buf =
-		(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
-				       ((2 * CONFIG_CACHELINE_SIZE) - 2));
-	if (NULL == hw_p->alloc_tx_buf)
-		return -1;
-	if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
-		hw_p->tx =
-			(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
-					CONFIG_CACHELINE_SIZE -
-					((int) hw_p->
-					 alloc_tx_buf & CACHELINE_MASK));
-	} else {
-		hw_p->tx = hw_p->alloc_tx_buf;
-	}
-
-	hw_p->alloc_rx_buf =
-		(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
-				       ((2 * CONFIG_CACHELINE_SIZE) - 2));
-	if (NULL == hw_p->alloc_rx_buf) {
-		free(hw_p->alloc_tx_buf);
-		hw_p->alloc_tx_buf = NULL;
-		return -1;
-	}
-
-	if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
-		hw_p->rx =
-			(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
-					CONFIG_CACHELINE_SIZE -
-					((int) hw_p->
-					 alloc_rx_buf & CACHELINE_MASK));
-	} else {
-		hw_p->rx = hw_p->alloc_rx_buf;
-	}
-
-	for (i = 0; i < NUM_TX_BUFF; i++) {
-		hw_p->tx[i].ctrl = 0;
-		hw_p->tx[i].data_len = 0;
-		if (hw_p->first_init == 0) {
-			hw_p->txbuf_ptr =
-				(char *) malloc (ENET_MAX_MTU_ALIGNED);
-			if (NULL == hw_p->txbuf_ptr) {
-				free(hw_p->alloc_rx_buf);
-				free(hw_p->alloc_tx_buf);
-				hw_p->alloc_rx_buf = NULL;
-				hw_p->alloc_tx_buf = NULL;
-				for(j = 0; j < i; j++) {
-					free(hw_p->tx[i].data_ptr);
-					hw_p->tx[i].data_ptr = NULL;
-				}
-			}
-		}
-		hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
-		if ((NUM_TX_BUFF - 1) == i)
-			hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
-		hw_p->tx_run[i] = -1;
-	}
-
-	for (i = 0; i < NUM_RX_BUFF; i++) {
-		hw_p->rx[i].ctrl = 0;
-		hw_p->rx[i].data_len = 0;
-		/*	 rx[i].data_ptr = (char *) &rx_buff[i]; */
-		hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
-		if ((NUM_RX_BUFF - 1) == i)
-			hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
-		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
-		hw_p->rx_ready[i] = -1;
-	}
-
-	reg = 0x00000000;
-
-	reg |= dev->enetaddr[0];	/* set high address */
-	reg = reg << 8;
-	reg |= dev->enetaddr[1];
-
-	out32 (EMAC_IAH + hw_p->hw_addr, reg);
-
-	reg = 0x00000000;
-	reg |= dev->enetaddr[2];	/* set low address  */
-	reg = reg << 8;
-	reg |= dev->enetaddr[3];
-	reg = reg << 8;
-	reg |= dev->enetaddr[4];
-	reg = reg << 8;
-	reg |= dev->enetaddr[5];
-
-	out32 (EMAC_IAL + hw_p->hw_addr, reg);
-
-	switch (devnum) {
-	case 1:
-		/* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
-		mtdcr (maltxctp2r, hw_p->tx);
-#else
-		mtdcr (maltxctp1r, hw_p->tx);
-#endif
-#if defined(CONFIG_440)
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-#endif
-		mtdcr (malrxctp1r, hw_p->rx);
-		/* set RX buffer size */
-		mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-#if defined (CONFIG_440GX)
-	case 2:
-		/* setup MAL tx & rx channel pointers */
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-		mtdcr (maltxctp2r, hw_p->tx);
-		mtdcr (malrxctp2r, hw_p->rx);
-		/* set RX buffer size */
-		mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-	case 3:
-		/* setup MAL tx & rx channel pointers */
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (maltxctp3r, hw_p->tx);
-		mtdcr (malrxbattr, 0x0);
-		mtdcr (malrxctp3r, hw_p->rx);
-		/* set RX buffer size */
-		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-#endif /* CONFIG_440GX */
-	case 0:
-	default:
-		/* setup MAL tx & rx channel pointers */
-#if defined(CONFIG_440)
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-#endif
-		mtdcr (maltxctp0r, hw_p->tx);
-		mtdcr (malrxctp0r, hw_p->rx);
-		/* set RX buffer size */
-		mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-	}
-
-	/* Enable MAL transmit and receive channels */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
-#else
-	mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-#endif
-	mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-
-	/* set transmit enable & receive enable */
-	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
-
-	/* set receive fifo to 4k and tx fifo to 2k */
-	mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
-	mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
-
-	/* set speed */
-	if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-		unsigned long pfc1;
-
-		mfsdr (sdr_pfc1, pfc1);
-		pfc1 |= SDR0_PFC1_EM_1000;
-		mtsdr (sdr_pfc1, pfc1);
-#endif
-		mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
-	} else if (speed == _100BASET)
-		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
-	else
-		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
-	if (duplex == FULL)
-		mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
-
-	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-
-	/* Enable broadcast and indvidual address */
-	/* TBS: enabling runts as some misbehaved nics will send runts */
-	out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
-
-	/* we probably need to set the tx mode1 reg? maybe at tx time */
-
-	/* set transmit request threshold register */
-	out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000);	/* 256 byte threshold */
-
-	/* set receive	low/high water mark register */
-#if defined(CONFIG_440)
-	/* 440s has a 64 byte burst length */
-	out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
-#else
-	/* 405s have a 16 byte burst length */
-	out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
-#endif /* defined(CONFIG_440) */
-	out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
-
-	/* Set fifo limit entry in tx mode 0 */
-	out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
-	/* Frame gap set */
-	out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
-
-	/* Set EMAC IER */
-	hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
-	if (speed == _100BASET)
-		hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
-
-	out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff);	/* clear pending interrupts */
-	out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
-
-	if (hw_p->first_init == 0) {
-		/*
-		 * Connect interrupt service routines
-		 */
-		irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
-				     (interrupt_handler_t *) enetInt, dev);
-	}
-
-	mtmsr (msr);		/* enable interrupts again */
-
-	hw_p->bis = bis;
-	hw_p->first_init = 1;
-
-	return (1);
-}
-
-
-static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
-			      int len)
-{
-	struct enet_frame *ef_ptr;
-	ulong time_start, time_now;
-	unsigned long temp_txm0;
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	ef_ptr = (struct enet_frame *) ptr;
-
-	/*-----------------------------------------------------------------------+
-	 *  Copy in our address into the frame.
-	 *-----------------------------------------------------------------------*/
-	(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
-
-	/*-----------------------------------------------------------------------+
-	 * If frame is too long or too short, modify length.
-	 *-----------------------------------------------------------------------*/
-	/* TBS: where does the fragment go???? */
-	if (len > ENET_MAX_MTU)
-		len = ENET_MAX_MTU;
-
-	/*   memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
-	memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
-
-	/*-----------------------------------------------------------------------+
-	 * set TX Buffer busy, and send it
-	 *-----------------------------------------------------------------------*/
-	hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
-					EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
-		~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
-	if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
-		hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
-
-	hw_p->tx[hw_p->tx_slot].data_len = (short) len;
-	hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
-
-	__asm__ volatile ("eieio");
-
-	out32 (EMAC_TXM0 + hw_p->hw_addr,
-	       in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_4XX_ENET
-	hw_p->stats.pkts_tx++;
-#endif
-
-	/*-----------------------------------------------------------------------+
-	 * poll unitl the packet is sent and then make sure it is OK
-	 *-----------------------------------------------------------------------*/
-	time_start = get_timer (0);
-	while (1) {
-		temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
-		/* loop until either TINT turns on or 3 seconds elapse */
-		if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
-			/* transmit is done, so now check for errors
-			 * If there is an error, an interrupt should
-			 * happen when we return
-			 */
-			time_now = get_timer (0);
-			if ((time_now - time_start) > 3000) {
-				return (-1);
-			}
-		} else {
-			return (len);
-		}
-	}
-}
-
-
-#if defined (CONFIG_440)
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-/*
- * Hack: On 440SP all enet irq sources are located on UIC1
- * Needs some cleanup. --sr
- */
-#define UIC0MSR		uic1msr
-#define UIC0SR		uic1sr
-#else
-#define UIC0MSR		uic0msr
-#define UIC0SR		uic0sr
-#endif
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define UICMSR_ETHX	uic0msr
-#define UICSR_ETHX	uic0sr
-#else
-#define UICMSR_ETHX	uic1msr
-#define UICSR_ETHX	uic1sr
-#endif
-
-int enetInt (struct eth_device *dev)
-{
-	int serviced;
-	int rc = -1;		/* default to not us */
-	unsigned long mal_isr;
-	unsigned long emac_isr = 0;
-	unsigned long mal_rx_eob;
-	unsigned long my_uic0msr, my_uic1msr;
-	unsigned long my_uicmsr_ethx;
-
-#if defined(CONFIG_440GX)
-	unsigned long my_uic2msr;
-#endif
-	EMAC_4XX_HW_PST hw_p;
-
-	/*
-	 * Because the mal is generic, we need to get the current
-	 * eth device
-	 */
-#if defined(CONFIG_NET_MULTI)
-	dev = eth_get_dev();
-#else
-	dev = emac0_dev;
-#endif
-
-	hw_p = dev->priv;
-
-	/* enter loop that stays in interrupt code until nothing to service */
-	do {
-		serviced = 0;
-
-		my_uic0msr = mfdcr (UIC0MSR);
-		my_uic1msr = mfdcr (uic1msr);
-#if defined(CONFIG_440GX)
-		my_uic2msr = mfdcr (uic2msr);
-#endif
-		my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
-
-		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
-		    && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
-		    && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
-			/* not for us */
-			return (rc);
-		}
-#if defined (CONFIG_440GX)
-		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
-		    && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
-			/* not for us */
-			return (rc);
-		}
-#endif
-		/* get and clear controller status interrupts */
-		/* look at Mal and EMAC interrupts */
-		if ((my_uic0msr & (UIC_MRE | UIC_MTE))
-		    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-			/* we have a MAL interrupt */
-			mal_isr = mfdcr (malesr);
-			/* look for mal error */
-			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
-				mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
-				serviced = 1;
-				rc = 0;
-			}
-		}
-
-		/* port by port dispatch of emac interrupts */
-		if (hw_p->devnum == 0) {
-			if (UIC_ETH0 & my_uicmsr_ethx) {	/* look for EMAC errors */
-				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
-				if ((hw_p->emac_ier & emac_isr) != 0) {
-					emac_err (dev, emac_isr);
-					serviced = 1;
-					rc = 0;
-				}
-			}
-			if ((hw_p->emac_ier & emac_isr)
-			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
-				mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
-				return (rc);	/* we had errors so get out */
-			}
-		}
-
-#if !defined(CONFIG_440SP)
-		if (hw_p->devnum == 1) {
-			if (UIC_ETH1 & my_uicmsr_ethx) {	/* look for EMAC errors */
-				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
-				if ((hw_p->emac_ier & emac_isr) != 0) {
-					emac_err (dev, emac_isr);
-					serviced = 1;
-					rc = 0;
-				}
-			}
-			if ((hw_p->emac_ier & emac_isr)
-			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
-				mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
-				return (rc);	/* we had errors so get out */
-			}
-		}
-#if defined (CONFIG_440GX)
-		if (hw_p->devnum == 2) {
-			if (UIC_ETH2 & my_uic2msr) {	/* look for EMAC errors */
-				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
-				if ((hw_p->emac_ier & emac_isr) != 0) {
-					emac_err (dev, emac_isr);
-					serviced = 1;
-					rc = 0;
-				}
-			}
-			if ((hw_p->emac_ier & emac_isr)
-			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
-				mtdcr (uic2sr, UIC_ETH2);
-				return (rc);	/* we had errors so get out */
-			}
-		}
-
-		if (hw_p->devnum == 3) {
-			if (UIC_ETH3 & my_uic2msr) {	/* look for EMAC errors */
-				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
-				if ((hw_p->emac_ier & emac_isr) != 0) {
-					emac_err (dev, emac_isr);
-					serviced = 1;
-					rc = 0;
-				}
-			}
-			if ((hw_p->emac_ier & emac_isr)
-			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
-				mtdcr (uic2sr, UIC_ETH3);
-				return (rc);	/* we had errors so get out */
-			}
-		}
-#endif /* CONFIG_440GX */
-#endif /* !CONFIG_440SP */
-
-		/* handle MAX TX EOB interrupt from a tx */
-		if (my_uic0msr & UIC_MTE) {
-			mal_rx_eob = mfdcr (maltxeobisr);
-			mtdcr (maltxeobisr, mal_rx_eob);
-			mtdcr (UIC0SR, UIC_MTE);
-		}
-		/* handle MAL RX EOB  interupt from a receive */
-		/* check for EOB on valid channels	      */
-		if (my_uic0msr & UIC_MRE) {
-			mal_rx_eob = mfdcr (malrxeobisr);
-			if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
-				/* clear EOB
-				   mtdcr(malrxeobisr, mal_rx_eob); */
-				enet_rcv (dev, emac_isr);
-				/* indicate that we serviced an interrupt */
-				serviced = 1;
-				rc = 0;
-			}
-		}
-
-		mtdcr (UIC0SR, UIC_MRE);	/* Clear */
-		mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
-		switch (hw_p->devnum) {
-		case 0:
-			mtdcr (UICSR_ETHX, UIC_ETH0);
-			break;
-		case 1:
-			mtdcr (UICSR_ETHX, UIC_ETH1);
-			break;
-#if defined (CONFIG_440GX)
-		case 2:
-			mtdcr (uic2sr, UIC_ETH2);
-			break;
-		case 3:
-			mtdcr (uic2sr, UIC_ETH3);
-			break;
-#endif /* CONFIG_440GX */
-		default:
-			break;
-		}
-	} while (serviced);
-
-	return (rc);
-}
-
-#else /* CONFIG_440 */
-
-int enetInt (struct eth_device *dev)
-{
-	int serviced;
-	int rc = -1;		/* default to not us */
-	unsigned long mal_isr;
-	unsigned long emac_isr = 0;
-	unsigned long mal_rx_eob;
-	unsigned long my_uicmsr;
-
-	EMAC_4XX_HW_PST hw_p;
-
-	/*
-	 * Because the mal is generic, we need to get the current
-	 * eth device
-	 */
-#if defined(CONFIG_NET_MULTI)
-	dev = eth_get_dev();
-#else
-	dev = emac0_dev;
-#endif
-
-	hw_p = dev->priv;
-
-	/* enter loop that stays in interrupt code until nothing to service */
-	do {
-		serviced = 0;
-
-		my_uicmsr = mfdcr (uicmsr);
-
-		if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) {	/* not for us */
-			return (rc);
-		}
-		/* get and clear controller status interrupts */
-		/* look at Mal and EMAC interrupts */
-		if ((MAL_UIC_DEF & my_uicmsr) != 0) {	/* we have a MAL interrupt */
-			mal_isr = mfdcr (malesr);
-			/* look for mal error */
-			if ((my_uicmsr & MAL_UIC_ERR) != 0) {
-				mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
-				serviced = 1;
-				rc = 0;
-			}
-		}
-
-		/* port by port dispatch of emac interrupts */
-
-		if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) {	/* look for EMAC errors */
-			emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
-			if ((hw_p->emac_ier & emac_isr) != 0) {
-				emac_err (dev, emac_isr);
-				serviced = 1;
-				rc = 0;
-			}
-		}
-		if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
-			mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
-			return (rc);		/* we had errors so get out */
-		}
-
-		/* handle MAX TX EOB interrupt from a tx */
-		if (my_uicmsr & UIC_MAL_TXEOB) {
-			mal_rx_eob = mfdcr (maltxeobisr);
-			mtdcr (maltxeobisr, mal_rx_eob);
-			mtdcr (uicsr, UIC_MAL_TXEOB);
-		}
-		/* handle MAL RX EOB  interupt from a receive */
-		/* check for EOB on valid channels	      */
-		if (my_uicmsr & UIC_MAL_RXEOB)
-		{
-			mal_rx_eob = mfdcr (malrxeobisr);
-			if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
-				/* clear EOB
-				 mtdcr(malrxeobisr, mal_rx_eob); */
-				enet_rcv (dev, emac_isr);
-				/* indicate that we serviced an interrupt */
-				serviced = 1;
-				rc = 0;
-			}
-		}
-		mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1);	/* Clear */
-	}
-	while (serviced);
-
-	return (rc);
-}
-
-#endif /* CONFIG_440 */
-
-/*-----------------------------------------------------------------------------+
- *  MAL Error Routine
- *-----------------------------------------------------------------------------*/
-static void mal_err (struct eth_device *dev, unsigned long isr,
-		     unsigned long uic, unsigned long maldef,
-		     unsigned long mal_errr)
-{
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	mtdcr (malesr, isr);	/* clear interrupt */
-
-	/* clear DE interrupt */
-	mtdcr (maltxdeir, 0xC0000000);
-	mtdcr (malrxdeir, 0x80000000);
-
-#ifdef INFO_4XX_ENET
-	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx	MAL_DEF = %lx  MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
-#endif
-
-	eth_init (hw_p->bis);	/* start again... */
-}
-
-/*-----------------------------------------------------------------------------+
- *  EMAC Error Routine
- *-----------------------------------------------------------------------------*/
-static void emac_err (struct eth_device *dev, unsigned long isr)
-{
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
-	out32 (EMAC_ISR + hw_p->hw_addr, isr);
-}
-
-/*-----------------------------------------------------------------------------+
- *  enet_rcv() handles the ethernet receive data
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr)
-{
-	struct enet_frame *ef_ptr;
-	unsigned long data_len;
-	unsigned long rx_eob_isr;
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	int handled = 0;
-	int i;
-	int loop_count = 0;
-
-	rx_eob_isr = mfdcr (malrxeobisr);
-	if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
-		/* clear EOB */
-		mtdcr (malrxeobisr, rx_eob_isr);
-
-		/* EMAC RX done */
-		while (1) {	/* do all */
-			i = hw_p->rx_slot;
-
-			if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
-			    || (loop_count >= NUM_RX_BUFF))
-				break;
-			loop_count++;
-			hw_p->rx_slot++;
-			if (NUM_RX_BUFF == hw_p->rx_slot)
-				hw_p->rx_slot = 0;
-			handled++;
-			data_len = (unsigned long) hw_p->rx[i].data_len;	/* Get len */
-			if (data_len) {
-				if (data_len > ENET_MAX_MTU)	/* Check len */
-					data_len = 0;
-				else {
-					if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) {	/* Check Errors */
-						data_len = 0;
-						hw_p->stats.rx_err_log[hw_p->
-								       rx_err_index]
-							= hw_p->rx[i].ctrl;
-						hw_p->rx_err_index++;
-						if (hw_p->rx_err_index ==
-						    MAX_ERR_LOG)
-							hw_p->rx_err_index =
-								0;
-					}	/* emac_erros */
-				}	/* data_len < max mtu */
-			}	/* if data_len */
-			if (!data_len) {	/* no data */
-				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */
-
-				hw_p->stats.data_len_err++;	/* Error at Rx */
-			}
-
-			/* !data_len */
-			/* AS.HARNOIS */
-			/* Check if user has already eaten buffer */
-			/* if not => ERROR */
-			else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
-				if (hw_p->is_receiving)
-					printf ("ERROR : Receive buffers are full!\n");
-				break;
-			} else {
-				hw_p->stats.rx_frames++;
-				hw_p->stats.rx += data_len;
-				ef_ptr = (struct enet_frame *) hw_p->rx[i].
-					data_ptr;
-#ifdef INFO_4XX_ENET
-				hw_p->stats.pkts_rx++;
-#endif
-				/* AS.HARNOIS
-				 * use ring buffer
-				 */
-				hw_p->rx_ready[hw_p->rx_i_index] = i;
-				hw_p->rx_i_index++;
-				if (NUM_RX_BUFF == hw_p->rx_i_index)
-					hw_p->rx_i_index = 0;
-
-				/*  AS.HARNOIS
-				 * free receive buffer only when
-				 * buffer has been handled (eth_rx)
-				 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
-				 */
-			}	/* if data_len */
-		}		/* while */
-	}			/* if EMACK_RXCHL */
-}
-
-
-static int ppc_4xx_eth_rx (struct eth_device *dev)
-{
-	int length;
-	int user_index;
-	unsigned long msr;
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	hw_p->is_receiving = 1; /* tell driver */
-
-	for (;;) {
-		/* AS.HARNOIS
-		 * use ring buffer and
-		 * get index from rx buffer desciptor queue
-		 */
-		user_index = hw_p->rx_ready[hw_p->rx_u_index];
-		if (user_index == -1) {
-			length = -1;
-			break;	/* nothing received - leave for() loop */
-		}
-
-		msr = mfmsr ();
-		mtmsr (msr & ~(MSR_EE));
-
-		length = hw_p->rx[user_index].data_len;
-
-		/* Pass the packet up to the protocol layers. */
-		/*	 NetReceive(NetRxPackets[rxIdx], length - 4); */
-		/*	 NetReceive(NetRxPackets[i], length); */
-		NetReceive (NetRxPackets[user_index], length - 4);
-		/* Free Recv Buffer */
-		hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
-		/* Free rx buffer descriptor queue */
-		hw_p->rx_ready[hw_p->rx_u_index] = -1;
-		hw_p->rx_u_index++;
-		if (NUM_RX_BUFF == hw_p->rx_u_index)
-			hw_p->rx_u_index = 0;
-
-#ifdef INFO_4XX_ENET
-		hw_p->stats.pkts_handled++;
-#endif
-
-		mtmsr (msr);	/* Enable IRQ's */
-	}
-
-	hw_p->is_receiving = 0; /* tell driver */
-
-	return length;
-}
-
-int ppc_4xx_eth_initialize (bd_t * bis)
-{
-	static int virgin = 0;
-	struct eth_device *dev;
-	int eth_num = 0;
-	EMAC_4XX_HW_PST hw = NULL;
-
-#if defined(CONFIG_440GX)
-	unsigned long pfc1;
-
-	mfsdr (sdr_pfc1, pfc1);
-	pfc1 &= ~(0x01e00000);
-	pfc1 |= 0x01200000;
-	mtsdr (sdr_pfc1, pfc1);
-#endif
-	/* set phy num and mode */
-	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
-	bis->bi_phymode[0] = 0;
-
-#if defined(CONFIG_PHY1_ADDR)
-	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
-	bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
-	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
-	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
-	bis->bi_phymode[2] = 2;
-	bis->bi_phymode[3] = 2;
-
-	ppc_4xx_eth_setup_bridge(0, bis);
-#endif
-
-	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-
-		/* See if we can actually bring up the interface, otherwise, skip it */
-		switch (eth_num) {
-		default:		/* fall through */
-		case 0:
-			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
-			break;
-#ifdef CONFIG_HAS_ETH1
-		case 1:
-			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH2
-		case 2:
-			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH3
-		case 3:
-			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
-			break;
-#endif
-		}
-
-		/* Allocate device structure */
-		dev = (struct eth_device *) malloc (sizeof (*dev));
-		if (dev == NULL) {
-			printf ("ppc_4xx_eth_initialize: "
-				"Cannot allocate eth_device %d\n", eth_num);
-			return (-1);
-		}
-		memset(dev, 0, sizeof(*dev));
-
-		/* Allocate our private use data */
-		hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
-		if (hw == NULL) {
-			printf ("ppc_4xx_eth_initialize: "
-				"Cannot allocate private hw data for eth_device %d",
-				eth_num);
-			free (dev);
-			return (-1);
-		}
-		memset(hw, 0, sizeof(*hw));
-
-		switch (eth_num) {
-		default:		/* fall through */
-		case 0:
-			hw->hw_addr = 0;
-			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
-			break;
-#ifdef CONFIG_HAS_ETH1
-		case 1:
-			hw->hw_addr = 0x100;
-			memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH2
-		case 2:
-			hw->hw_addr = 0x400;
-			memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH3
-		case 3:
-			hw->hw_addr = 0x600;
-			memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
-			break;
-#endif
-		}
-
-		hw->devnum = eth_num;
-		hw->print_speed = 1;
-
-		sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
-		dev->priv = (void *) hw;
-		dev->init = ppc_4xx_eth_init;
-		dev->halt = ppc_4xx_eth_halt;
-		dev->send = ppc_4xx_eth_send;
-		dev->recv = ppc_4xx_eth_rx;
-
-		if (0 == virgin) {
-			/* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-			mal_ier =
-				MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
-				MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
-#else
-			mal_ier =
-				MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
-				MAL_IER_OPBE | MAL_IER_PLBE;
-#endif
-			mtdcr (malesr, 0xffffffff);	/* clear pending interrupts */
-			mtdcr (maltxdeir, 0xffffffff);	/* clear pending interrupts */
-			mtdcr (malrxdeir, 0xffffffff);	/* clear pending interrupts */
-			mtdcr (malier, mal_ier);
-
-			/* install MAL interrupt handler */
-			irq_install_handler (VECNUM_MS,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_MTE,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_MRE,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_TXDE,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_RXDE,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			virgin = 1;
-		}
-
-#if defined(CONFIG_NET_MULTI)
-		eth_register (dev);
-#else
-		emac0_dev = dev;
-#endif
-
-#if defined(CONFIG_NET_MULTI)
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
-		miiphy_register (dev->name,
-				 emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
-#endif
-	}			/* end for each supported device */
-	return (1);
-}
-
-
-#if !defined(CONFIG_NET_MULTI)
-void eth_halt (void) {
-	if (emac0_dev) {
-		ppc_4xx_eth_halt(emac0_dev);
-		free(emac0_dev);
-		emac0_dev = NULL;
-	}
-}
-
-int eth_init (bd_t *bis)
-{
-	ppc_4xx_eth_initialize(bis);
-	if (emac0_dev) {
-		return ppc_4xx_eth_init(emac0_dev, bis);
-	} else {
-		printf("ERROR: ethaddr not set!\n");
-		return -1;
-	}
-}
-
-int eth_send(volatile void *packet, int length)
-{
-	return (ppc_4xx_eth_send(emac0_dev, packet, length));
-}
-
-int eth_rx(void)
-{
-	return (ppc_4xx_eth_rx(emac0_dev));
-}
-
-int emac4xx_miiphy_initialize (bd_t * bis)
-{
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
-	miiphy_register ("ppc_4xx_eth0",
-			 emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
-
-	return 0;
-}
-#endif /* !defined(CONFIG_NET_MULTI) */
-
-#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c
deleted file mode 100644
index 74f57565ff..0000000000
--- a/drivers/net/bcm570x.c
+++ /dev/null
@@ -1,1684 +0,0 @@
-/*
- * Broadcom BCM570x Ethernet Driver for U-Boot.
- * Support 5701, 5702, 5703, and 5704. Single instance driver.
- * Copyright (C) 2002 James F. Dougherty (jfd@broadcom.com)
- */
-
-#include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && (!defined(CONFIG_NET_MULTI)) && \
-	defined(CONFIG_BCM570x)
-
-#ifdef CONFIG_BMW
-#include <mpc824x.h>
-#endif
-#include <net.h>
-#include "bcm570x_mm.h"
-#include "bcm570x_autoneg.h"
-#include <pci.h>
-#include <malloc.h>
-
-
-/*
- * PCI Registers and definitions.
- */
-#define PCI_CMD_MASK	0xffff0000	/* mask to save status bits */
-#define PCI_ANY_ID (~0)
-
-/*
- * PCI memory base for Ethernet device as well as device Interrupt.
- */
-#define BCM570X_MBAR 	0x80100000
-#define BCM570X_ILINE   1
-
-
-#define SECOND_USEC	1000000
-#define MAX_PACKET_SIZE 1600
-#define MAX_UNITS       4
-
-/* Globals to this module */
-int initialized = 0;
-unsigned int ioBase = 0;
-volatile PLM_DEVICE_BLOCK    pDevice = NULL;        /* 570x softc */
-volatile PUM_DEVICE_BLOCK    pUmDevice = NULL;
-
-/* Used to pass the full-duplex flag, etc. */
-int line_speed[MAX_UNITS] = {0,0,0,0};
-static int full_duplex[MAX_UNITS] = {1,1,1,1};
-static int rx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int auto_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_checksum[MAX_UNITS] = {1,1,1,1};
-static int rx_checksum[MAX_UNITS] = {1,1,1,1};
-static int auto_speed[MAX_UNITS] = {1,1,1,1};
-
-#if JUMBO_FRAMES
-/* Jumbo MTU for interfaces. */
-static int mtu[MAX_UNITS] = {0,0,0,0};
-#endif
-
-/* Turn on Wake-on lan for a device unit */
-static int enable_wol[MAX_UNITS] = {0,0,0,0};
-
-#define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
-static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =
-	{TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT};
-
-#define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
-static unsigned int rx_std_desc_cnt[MAX_UNITS] =
-	{RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT};
-
-static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1};
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
-#define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
-static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =
-	{JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT};
-#endif
-#define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
-static unsigned int rx_coalesce_ticks[MAX_UNITS] =
-	{RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK};
-
-#define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
-static unsigned int rx_max_coalesce_frames[MAX_UNITS] =
-	{RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM};
-
-#define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
-static unsigned int tx_coalesce_ticks[MAX_UNITS] =
-	{TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK};
-
-#define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
-static unsigned int tx_max_coalesce_frames[MAX_UNITS] =
-	{TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM};
-
-#define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
-static unsigned int stats_coalesce_ticks[MAX_UNITS] =
-	{ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK};
-
-
-/*
- * Legitimate values for BCM570x device types
- */
-typedef enum {
-	BCM5700VIGIL = 0,
-	BCM5700A6,
-	BCM5700T6,
-	BCM5700A9,
-	BCM5700T9,
-	BCM5700,
-	BCM5701A5,
-	BCM5701T1,
-	BCM5701T8,
-	BCM5701A7,
-	BCM5701A10,
-	BCM5701A12,
-	BCM5701,
-	BCM5702,
-	BCM5703,
-	BCM5703A31,
-	TC996T,
-	TC996ST,
-	TC996SSX,
-	TC996SX,
-	TC996BT,
-	TC997T,
-	TC997SX,
-	TC1000T,
-	TC940BR01,
-	TC942BR01,
-	NC6770,
-	NC7760,
-	NC7770,
-	NC7780
-} board_t;
-
-/* Chip-Rev names for each device-type */
-static struct {
-    char* name;
-} chip_rev[] = {
-       {"BCM5700VIGIL"},
-       {"BCM5700A6"},
-       {"BCM5700T6"},
-       {"BCM5700A9"},
-       {"BCM5700T9"},
-       {"BCM5700"},
-       {"BCM5701A5"},
-       {"BCM5701T1"},
-       {"BCM5701T8"},
-       {"BCM5701A7"},
-       {"BCM5701A10"},
-       {"BCM5701A12"},
-       {"BCM5701"},
-       {"BCM5702"},
-       {"BCM5703"},
-       {"BCM5703A31"},
-       {"TC996T"},
-       {"TC996ST"},
-       {"TC996SSX"},
-       {"TC996SX"},
-       {"TC996BT"},
-       {"TC997T"},
-       {"TC997SX"},
-       {"TC1000T"},
-       {"TC940BR01"},
-       {"TC942BR01"},
-       {"NC6770"},
-       {"NC7760"},
-       {"NC7770"},
-       {"NC7780"},
-       {0}
-};
-
-
-/* indexed by board_t, above */
-static struct {
-    char *name;
-} board_info[] = {
-	{ "Broadcom Vigil B5700 1000Base-T" },
-	{ "Broadcom BCM5700 1000Base-T" },
-	{ "Broadcom BCM5700 1000Base-SX" },
-	{ "Broadcom BCM5700 1000Base-SX" },
-	{ "Broadcom BCM5700 1000Base-T" },
-	{ "Broadcom BCM5700" },
-	{ "Broadcom BCM5701 1000Base-T" },
-	{ "Broadcom BCM5701 1000Base-T" },
-	{ "Broadcom BCM5701 1000Base-T" },
-	{ "Broadcom BCM5701 1000Base-SX" },
-	{ "Broadcom BCM5701 1000Base-T" },
-	{ "Broadcom BCM5701 1000Base-T" },
-	{ "Broadcom BCM5701" },
-	{ "Broadcom BCM5702 1000Base-T" },
-	{ "Broadcom BCM5703 1000Base-T" },
-	{ "Broadcom BCM5703 1000Base-SX" },
-	{ "3Com 3C996 10/100/1000 Server NIC" },
-	{ "3Com 3C996 10/100/1000 Server NIC" },
-	{ "3Com 3C996 Gigabit Fiber-SX Server NIC" },
-	{ "3Com 3C996 Gigabit Fiber-SX Server NIC" },
-	{ "3Com 3C996B Gigabit Server NIC" },
-	{ "3Com 3C997 Gigabit Server NIC" },
-	{ "3Com 3C997 Gigabit Fiber-SX Server NIC" },
-	{ "3Com 3C1000 Gigabit NIC" },
-	{ "3Com 3C940 Gigabit LOM (21X21)" },
-	{ "3Com 3C942 Gigabit LOM (31X31)" },
-	{ "Compaq NC6770 Gigabit Server Adapter" },
-	{ "Compaq NC7760 Gigabit Server Adapter" },
-	{ "Compaq NC7770 Gigabit Server Adapter" },
-	{ "Compaq NC7780 Gigabit Server Adapter" },
-	{ 0 },
-};
-
-/* PCI Devices which use the 570x chipset */
-struct pci_device_table {
-    unsigned short vendor_id, device_id; /* Vendor/DeviceID */
-    unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
-    unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
-    unsigned long board_id;	    /* Data private to the driver */
-    int io_size, min_latency;
-} bcm570xDevices[] = {
-	{0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32},
-	{0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32},
-	{0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32},
-	{0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32},
-	{0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32},
-	{0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32},
-	{0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32},
-	{0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32},
-	{0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32},
-	{0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32},
-	{0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32},
-	{0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32},
-	{0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32},
-	{0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32},
-	{0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32},
-	{0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32},
-	{0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32},
-	{0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32},
-	{0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32},
-	{0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32},
-	{0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32},
-	{0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32},
-	{0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32},
-	{0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32},
-	{0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32},
-	{0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32},
-	{0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32},
-	{0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32},
-	{0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32},
-	{0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32},
-	{0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32},
-	{0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
-	{0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
-	{0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
-	{0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
-	{0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
-	{0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
-	{0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
-	{0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
-	{0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
-	{0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
-	{0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
-	{0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
-	{0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
-	{0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}
-};
-
-#define n570xDevices   (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
-
-
-/*
- * Allocate a packet buffer from the bcm570x packet pool.
- */
-void *
-bcm570xPktAlloc(int u, int pksize)
-{
-    return malloc(pksize);
-}
-
-/*
- * Free a packet previously allocated from the bcm570x packet
- * buffer pool.
- */
-void
-bcm570xPktFree(int u, void *p)
-{
-    free(p);
-}
-
-int
-bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice)
-{
-    PLM_PACKET pPacket;
-    PUM_PACKET pUmPacket;
-    void *skb;
-    int queue_rx = 0;
-    int ret = 0;
-
-    while ((pUmPacket = (PUM_PACKET)
-	    QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
-
-	pPacket = (PLM_PACKET) pUmPacket;
-
-	/* reuse an old skb */
-	if (pUmPacket->skbuff) {
-	    QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-	    queue_rx = 1;
-	    continue;
-	}
-	if ( ( skb = bcm570xPktAlloc(pUmDevice->index,
-				     pPacket->u.Rx.RxBufferSize + 2)) == 0) {
-	    QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket);
-	    printf("NOTICE: Out of RX memory.\n");
-	    ret = 1;
-	    break;
-	}
-
-	pUmPacket->skbuff = skb;
-	QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-	queue_rx = 1;
-    }
-
-    if (queue_rx) {
-	LM_QueueRxPackets(pDevice);
-    }
-
-    return ret;
-}
-
-/*
- * Probe, Map, and Init 570x device.
- */
-int eth_init(bd_t *bis)
-{
-    int i, rv, devFound = FALSE;
-    pci_dev_t  devbusfn;
-    unsigned short status;
-
-    /* Find PCI device, if it exists, configure ...  */
-    for( i = 0; i < n570xDevices; i++){
-	devbusfn = pci_find_device(bcm570xDevices[i].vendor_id,
-				   bcm570xDevices[i].device_id, 0);
-	if(devbusfn == -1) {
-	    continue; /* No device of that vendor/device ID */
-	} else {
-
-	    /* Set ILINE */
-	    pci_write_config_byte(devbusfn,
-				  PCI_INTERRUPT_LINE, BCM570X_ILINE);
-
-	    /*
-	     * 0x10 - 0x14 define one 64-bit MBAR.
-	     * 0x14 is the higher-order address bits of the BAR.
-	     */
-	    pci_write_config_dword(devbusfn,
-				   PCI_BASE_ADDRESS_1, 0);
-
-	    ioBase = BCM570X_MBAR;
-
-	    pci_write_config_dword(devbusfn,
-				   PCI_BASE_ADDRESS_0, ioBase);
-
-	    /*
-	     * Enable PCI memory, IO, and Master -- don't
-	     * reset any status bits in doing so.
-	     */
-	    pci_read_config_word(devbusfn,
-				 PCI_COMMAND, &status);
-
-	    status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
-
-	    pci_write_config_word(devbusfn,
-				  PCI_COMMAND, status);
-
-	    printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
-		   board_info[bcm570xDevices[i].board_id].name,
-		   PCI_BUS(devbusfn),
-		   PCI_DEV(devbusfn),
-		   PCI_FUNC(devbusfn),
-		   ioBase);
-
-	    /* Allocate once, but always clear on init */
-	    if (!pDevice) {
-		pDevice = malloc(sizeof(UM_DEVICE_BLOCK));
-		pUmDevice = (PUM_DEVICE_BLOCK)pDevice;
-		memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK));
-	    }
-
-	    /* Configure pci dev structure */
-	    pUmDevice->pdev = devbusfn;
-	    pUmDevice->index = 0;
-	    pUmDevice->tx_pkt = 0;
-	    pUmDevice->rx_pkt = 0;
-	    devFound = TRUE;
-	    break;
-	}
-    }
-
-    if(!devFound){
-	printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
-	return -1;
-    }
-
-    /* Setup defaults for chip */
-    pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-
-    if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
-	pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-    } else {
-
-	if (rx_checksum[i]) {
-	    pDevice->TaskToOffload |=
-		LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
-		LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
-	}
-
-	if (tx_checksum[i]) {
-	    pDevice->TaskToOffload |=
-		LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
-		LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
-	    pDevice->NoTxPseudoHdrChksum = TRUE;
-	}
-    }
-
-    /* Set Device PCI Memory base address */
-    pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
-
-    /* Pull down adapter info */
-    if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) {
-	printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv );
-	return -2;
-    }
-
-    /* Lock not needed */
-    pUmDevice->do_global_lock = 0;
-
-    if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
-	/* The 5700 chip works best without interleaved register */
-	/* accesses on certain machines. */
-	pUmDevice->do_global_lock = 1;
-    }
-
-    /* Setup timer delays */
-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
-	pDevice->UseTaggedStatus = TRUE;
-	pUmDevice->timer_interval = CFG_HZ;
-    }
-    else {
-	pUmDevice->timer_interval = CFG_HZ / 50;
-    }
-
-    /* Grab name .... */
-    pUmDevice->name =
-	(char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1);
-    strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name);
-
-    memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6);
-    LM_SetMacAddress(pDevice, bis->bi_enetaddr);
-    /* Init queues  .. */
-    QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container,
-		 MAX_RX_PACKET_DESC_COUNT);
-    pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
-
-    /* delay for 4 seconds */
-    pUmDevice->delayed_link_ind =
-	(4 * CFG_HZ) / pUmDevice->timer_interval;
-
-    pUmDevice->adaptive_expiry =
-	CFG_HZ / pUmDevice->timer_interval;
-
-    /* Sometimes we get spurious ints. after reset when link is down. */
-    /* This field tells the isr to service the int. even if there is */
-    /* no status block update. */
-    pUmDevice->adapter_just_inited =
-	(3 * CFG_HZ) / pUmDevice->timer_interval;
-
-    /* Initialize 570x */
-    if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) {
-	printf("ERROR: Adapter initialization failed.\n");
-	return ERROR;
-    }
-
-    /* Enable chip ISR */
-    LM_EnableInterrupt(pDevice);
-
-    /* Clear MC table */
-    LM_MulticastClear(pDevice);
-
-    /* Enable Multicast */
-    LM_SetReceiveMask(pDevice,
-		      pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
-
-    pUmDevice->opened = 1;
-    pUmDevice->tx_full = 0;
-    pUmDevice->tx_pkt = 0;
-    pUmDevice->rx_pkt = 0;
-    printf("eth%d: %s @0x%lx,",
-	   pDevice->index, pUmDevice->name, (unsigned long)ioBase);
-    printf(	"node addr ");
-    for (i = 0; i < 6; i++) {
-	printf("%2.2x", pDevice->NodeAddress[i]);
-    }
-    printf("\n");
-
-    printf("eth%d: ", pDevice->index);
-    printf("%s with ",
-	   chip_rev[bcm570xDevices[i].board_id].name);
-
-    if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
-	printf("Broadcom BCM5400 Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
-	printf("Broadcom BCM5401 Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
-	printf("Broadcom BCM5411 Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
-	printf("Broadcom BCM5701 Integrated Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
-	printf("Broadcom BCM5703 Integrated Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
-	printf("Broadcom BCM8002 SerDes ");
-    else if (pDevice->EnableTbi)
-	printf("Agilent HDMP-1636 SerDes ");
-    else
-	printf("Unknown ");
-    printf("transceiver found\n");
-
-    printf("eth%d: %s, MTU: %d,",
-	   pDevice->index, pDevice->BusSpeedStr, 1500);
-
-    if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) &&
-	rx_checksum[i])
-	printf("Rx Checksum ON\n");
-    else
-	printf("Rx Checksum OFF\n");
-    initialized++;
-
-    return 0;
-}
-
-/* Ethernet Interrupt service routine */
-void
-eth_isr(void)
-{
-    LM_UINT32 oldtag, newtag;
-    int i;
-
-    pUmDevice->interrupt = 1;
-
-    if (pDevice->UseTaggedStatus) {
-	if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
-	    pUmDevice->adapter_just_inited) {
-	    MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
-	    oldtag = pDevice->pStatusBlkVirt->StatusTag;
-
-	    for (i = 0; ; i++) {
-		pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
-		LM_ServiceInterrupts(pDevice);
-		newtag = pDevice->pStatusBlkVirt->StatusTag;
-		if ((newtag == oldtag) || (i > 50)) {
-		    MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24);
-		    if (pDevice->UndiFix) {
-			REG_WR(pDevice, Grc.LocalCtrl,
-			       pDevice->GrcLocalCtrl | 0x2);
-		    }
-		    break;
-		 }
-		oldtag = newtag;
-	    }
-	}
-    }
-    else {
-	while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
-	    unsigned int dummy;
-
-	    pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
-	    pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
-	    LM_ServiceInterrupts(pDevice);
-	    pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
-	    dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
-	}
-    }
-
-    /* Allocate new RX buffers */
-    if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) {
-	bcm570xReplenishRxBuffers(pUmDevice);
-    }
-
-    /* Queue packets */
-    if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) {
-	LM_QueueRxPackets(pDevice);
-    }
-
-    if (pUmDevice->tx_queued) {
-	pUmDevice->tx_queued = 0;
-    }
-
-    if(pUmDevice->tx_full){
-	if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){
-	    printf("NOTICE: tx was previously blocked, restarting MUX\n");
-	    pUmDevice->tx_full = 0;
-	}
-    }
-
-    pUmDevice->interrupt = 0;
-
-}
-
-int
-eth_send(volatile void *packet, int length)
-{
-    int status = 0;
-#if ET_DEBUG
-    unsigned char* ptr = (unsigned char*)packet;
-#endif
-    PLM_PACKET pPacket;
-    PUM_PACKET pUmPacket;
-
-    /* Link down, return */
-    while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
-	eth_isr();
-
-	/* Wait to see link for one-half a second before sending ... */
-	udelay(1500000);
-
-    }
-
-    /* Clear sent flag */
-    pUmDevice->tx_pkt = 0;
-
-    /* Previously blocked */
-    if(pUmDevice->tx_full){
-	printf("eth%d: tx blocked.\n", pUmDevice->index);
-	return 0;
-    }
-
-    pPacket = (PLM_PACKET)
-	QQ_PopHead(&pDevice->TxPacketFreeQ.Container);
-
-    if (pPacket == 0) {
-	pUmDevice->tx_full = 1;
-	printf("bcm570xEndSend: TX full!\n");
-	return 0;
-    }
-
-    if (pDevice->SendBdLeft.counter == 0) {
-	pUmDevice->tx_full = 1;
-	printf("bcm570xEndSend: no more TX descriptors!\n");
-	QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
-	return 0;
-    }
-
-    if (length <= 0){
-	printf("eth: bad packet size: %d\n", length);
-	goto out;
-    }
-
-    /* Get packet buffers and fragment list */
-    pUmPacket = (PUM_PACKET) pPacket;
-    /* Single DMA Descriptor transmit.
-     * Fragments may be provided, but one DMA descriptor max is
-     * used to send the packet.
-     */
-    if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
-	if (pUmPacket->skbuff == NULL){
-	    /* Packet was discarded */
-	    printf("TX: failed (1)\n");
-	    status = 1;
-	} else{
-	    printf("TX: failed (2)\n");
-	    status = 2;
-	}
-	QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
-	return status;
-    }
-
-    /* Copy packet to DMA buffer */
-    memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
-    memcpy((void*)pUmPacket->skbuff, (void*)packet, length);
-    pPacket->PacketSize = length;
-    pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW;
-    pPacket->u.Tx.FragCount = 1;
-    /* We've already provided a frame ready for transmission */
-    pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
-
-    if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){
-	/*
-	 *  A lower level send failure will push the packet descriptor back
-	 *  in the free queue, so just deal with the VxWorks clusters.
-	 */
-	if (pUmPacket->skbuff == NULL){
-	    printf("TX failed (1)!\n");
-	    /* Packet was discarded */
-	    status = 3;
-	} else {
-	    /* A resource problem ... */
-	    printf("TX failed (2)!\n");
-	    status = 4;
-	}
-
-	if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) {
-	    printf("TX: emptyQ!\n");
-	    pUmDevice->tx_full = 1;
-	}
-    }
-
-    while(pUmDevice->tx_pkt == 0){
-	/* Service TX */
-	eth_isr();
-    }
-#if ET_DEBUG
-    printf("eth_send: 0x%x, %d bytes\n"
-	   "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
-	   (int)pPacket, length,
-	   ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5],
-	   ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12],
-	   ptr[13],ptr[14],ptr[15]);
-#endif
-    pUmDevice->tx_pkt = 0;
-    QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
-
-    /* Done with send */
- out:
-    return status;
-}
-
-
-/* Ethernet receive */
-int
-eth_rx(void)
-{
-    PLM_PACKET          pPacket = NULL;
-    PUM_PACKET          pUmPacket = NULL;
-    void *skb;
-    int size=0;
-
-    while(TRUE) {
-
-    bcm570x_service_isr:
-	/* Pull down packet if it is there */
-	eth_isr();
-
-	/* Indicate RX packets called */
-	if(pUmDevice->rx_pkt){
-	    /* printf("eth_rx: got a packet...\n"); */
-	    pUmDevice->rx_pkt = 0;
-	} else {
-	    /* printf("eth_rx: waiting for packet...\n"); */
-	    goto bcm570x_service_isr;
-	}
-
-	pPacket = (PLM_PACKET)
-	    QQ_PopHead(&pDevice->RxPacketReceivedQ.Container);
-
-	if (pPacket == 0){
-	    printf("eth_rx: empty packet!\n");
-	    goto bcm570x_service_isr;
-	}
-
-	pUmPacket = (PUM_PACKET) pPacket;
-#if ET_DEBUG
-	printf("eth_rx: packet @0x%x\n",
-	       (int)pPacket);
-#endif
-	/* If the packet generated an error, reuse buffer */
-	if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
-	    ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
-
-	    /* reuse skb */
-	    QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-	    printf("eth_rx: error in packet dma!\n");
-	    goto bcm570x_service_isr;
-	}
-
-	/* Set size and address */
-	skb = pUmPacket->skbuff;
-	size = pPacket->PacketSize;
-
-	/* Pass the packet up to the protocol
-	 * layers.
-	 */
-	NetReceive(skb, size);
-
-	/* Free packet buffer */
-	bcm570xPktFree (pUmDevice->index, skb);
-	pUmPacket->skbuff = NULL;
-
-	/* Reuse SKB */
-	QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
-	return 0; /* Got a packet, bail ... */
-    }
-    return size;
-}
-
-
-/* Shut down device */
-void
-eth_halt(void)
-{
-    int i;
-    if ( initialized)
-    if (pDevice && pUmDevice && pUmDevice->opened){
-	printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name);
-	printf("HALT,");
-	/* stop device */
-	LM_Halt(pDevice);
-	printf("POWER DOWN,");
-	LM_SetPowerState(pDevice, LM_POWER_STATE_D3);
-
-	/* Free the memory allocated by the device in tigon3 */
-	for (i = 0; i < pUmDevice->mem_list_num; i++)  {
-	    if (pUmDevice->mem_list[i])  {
-		/* sanity check */
-		if (pUmDevice->dma_list[i]) {  /* cache-safe memory */
-		    free(pUmDevice->mem_list[i]);
-		} else {
-		    free(pUmDevice->mem_list[i]);  /* normal memory   */
-		}
-	    }
-	}
-	pUmDevice->opened = 0;
-	free(pDevice);
-	pDevice = NULL;
-	pUmDevice = NULL;
-	initialized = 0;
-	printf("done - offline.\n");
-    }
-}
-
-
-/*
- *
- * Middle Module: Interface between the HW driver (tigon3 modules) and
- * the native (SENS) driver.  These routines implement the system
- * interface for tigon3 on VxWorks.
- */
-
-/* Middle module dependency - size of a packet descriptor */
-int MM_Packet_Desc_Size = sizeof(UM_PACKET);
-
-
-LM_STATUS
-MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice,
-		LM_UINT32 Offset,
-		LM_UINT32 *pValue32)
-{
-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_read_config_dword(pUmDevice->pdev,
-			  Offset, (u32 *) pValue32);
-    return LM_STATUS_SUCCESS;
-}
-
-
-LM_STATUS
-MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice,
-		 LM_UINT32 Offset,
-		 LM_UINT32 Value32)
-{
-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_write_config_dword(pUmDevice->pdev,
-			   Offset, Value32);
-    return LM_STATUS_SUCCESS;
-}
-
-
-LM_STATUS
-MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice,
-		LM_UINT32 Offset,
-		LM_UINT16 *pValue16)
-{
-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_read_config_word(pUmDevice->pdev,
-			 Offset, (u16*) pValue16);
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice,
-		 LM_UINT32 Offset,
-		 LM_UINT16 Value16)
-{
-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_write_config_word(pUmDevice->pdev,
-			  Offset, Value16);
-    return LM_STATUS_SUCCESS;
-}
-
-
-LM_STATUS
-MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
-			PLM_VOID *pMemoryBlockVirt,
-			PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
-			LM_BOOL Cached)
-{
-    PLM_VOID pvirt;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    dma_addr_t mapping;
-
-    pvirt = malloc(BlockSize);
-    mapping = (dma_addr_t)(pvirt);
-    if (!pvirt)
-	return LM_STATUS_FAILURE;
-
-    pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
-    pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
-    pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
-    memset(pvirt, 0, BlockSize);
-
-    *pMemoryBlockVirt = (PLM_VOID) pvirt;
-    MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
-
-    return LM_STATUS_SUCCESS;
-}
-
-
-LM_STATUS
-MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
-	PLM_VOID *pMemoryBlockVirt)
-{
-    PLM_VOID pvirt;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-
-    pvirt = malloc(BlockSize);
-
-    if (!pvirt)
-	return LM_STATUS_FAILURE;
-
-    pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
-    pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
-    pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
-    memset(pvirt, 0, BlockSize);
-    *pMemoryBlockVirt = pvirt;
-
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_MapMemBase(PLM_DEVICE_BLOCK pDevice)
-{
-    printf("BCM570x PCI Memory base address @0x%x\n",
-	   (unsigned int)pDevice->pMappedMemBase);
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice)
-{
-    int i;
-    void* skb;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    PUM_PACKET pUmPacket = NULL;
-    PLM_PACKET pPacket = NULL;
-
-    for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
-	pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
-	pUmPacket = (PUM_PACKET) pPacket;
-
-	if (pPacket == 0) {
-	    printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
-	}
-
-	skb = bcm570xPktAlloc(pUmDevice->index,
-			      pPacket->u.Rx.RxBufferSize + 2);
-
-	if (skb == 0) {
-	    pUmPacket->skbuff = 0;
-	    QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket);
-	    printf("MM_InitializeUmPackets: out of buffer.\n");
-	    continue;
-	}
-
-	pUmPacket->skbuff = skb;
-	QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-    }
-
-    pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
-
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_GetConfig(PLM_DEVICE_BLOCK pDevice)
-{
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    int index = pDevice->index;
-
-    if (auto_speed[index] == 0)
-	pDevice->DisableAutoNeg = TRUE;
-    else
-	pDevice->DisableAutoNeg = FALSE;
-
-    if (line_speed[index] == 0) {
-	pDevice->RequestedMediaType =
-	    LM_REQUESTED_MEDIA_TYPE_AUTO;
-	pDevice->DisableAutoNeg = FALSE;
-    }
-    else {
-	if (line_speed[index] == 1000) {
-	    if (pDevice->EnableTbi) {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
-	    }
-	    else if (full_duplex[index]) {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
-	    }
-	    else {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
-	    }
-	    if (!pDevice->EnableTbi)
-		pDevice->DisableAutoNeg = FALSE;
-	}
-	else if (line_speed[index] == 100) {
-	    if (full_duplex[index]) {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
-	    }
-	    else {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
-	    }
-	}
-	else if (line_speed[index] == 10) {
-	    if (full_duplex[index]) {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
-	    }
-	    else {
-		pDevice->RequestedMediaType =
-		    LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
-	    }
-	}
-	else {
-	    pDevice->RequestedMediaType =
-		LM_REQUESTED_MEDIA_TYPE_AUTO;
-	    pDevice->DisableAutoNeg = FALSE;
-	}
-
-    }
-    pDevice->FlowControlCap = 0;
-    if (rx_flow_control[index] != 0) {
-	pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
-    }
-    if (tx_flow_control[index] != 0) {
-	pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
-    }
-    if ((auto_flow_control[index] != 0) &&
-	(pDevice->DisableAutoNeg == FALSE)) {
-
-	pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
-	if ((tx_flow_control[index] == 0) &&
-	    (rx_flow_control[index] == 0)) {
-	    pDevice->FlowControlCap |=
-		LM_FLOW_CONTROL_TRANSMIT_PAUSE |
-		LM_FLOW_CONTROL_RECEIVE_PAUSE;
-	}
-    }
-
-    /* Default MTU for now */
-    pUmDevice->mtu = 1500;
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
-    if (pUmDevice->mtu > 1500) {
-	pDevice->RxMtu = pUmDevice->mtu;
-	pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
-    }
-    else {
-	pDevice->RxJumboDescCnt = 0;
-    }
-    pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
-#else
-    pDevice->RxMtu = pUmDevice->mtu;
-#endif
-
-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
-	pDevice->UseTaggedStatus = TRUE;
-	pUmDevice->timer_interval = CFG_HZ;
-    }
-    else {
-	pUmDevice->timer_interval = CFG_HZ/50;
-    }
-
-    pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
-    pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
-    /* Note:  adaptive coalescence really isn't adaptive in this driver */
-    pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
-    if (!pUmDevice->rx_adaptive_coalesce) {
-	pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
-	if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
-	    pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
-	pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks;
-
-	pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
-	if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES)
-	    pDevice->RxMaxCoalescedFrames =
-				MAX_RX_MAX_COALESCED_FRAMES;
-	pUmDevice->rx_curr_coalesce_frames =
-	    pDevice->RxMaxCoalescedFrames;
-	pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
-	if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS)
-	    pDevice->StatsCoalescingTicks=
-		MAX_STATS_COALESCING_TICKS;
-	}
-	else {
-	    pUmDevice->rx_curr_coalesce_frames =
-		DEFAULT_RX_MAX_COALESCED_FRAMES;
-	    pUmDevice->rx_curr_coalesce_ticks =
-		DEFAULT_RX_COALESCING_TICKS;
-	}
-    pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
-    if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
-	pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
-    pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
-    if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
-	pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
-
-    if (enable_wol[index]) {
-	pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
-	pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
-    }
-    pDevice->NicSendBd = TRUE;
-
-    /* Don't update status blocks during interrupt */
-    pDevice->RxCoalescingTicksDuringInt = 0;
-    pDevice->TxCoalescingTicksDuringInt = 0;
-
-    return LM_STATUS_SUCCESS;
-
-}
-
-
-LM_STATUS
-MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
-{
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    printf("Start TX DMA: dev=%d packet @0x%x\n",
-	   (int)pUmDevice->index, (unsigned int)pPacket);
-
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
-{
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    printf("Complete TX DMA: dev=%d packet @0x%x\n",
-	   (int)pUmDevice->index, (unsigned int)pPacket);
-    return LM_STATUS_SUCCESS;
-}
-
-
-LM_STATUS
-MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
-{
-    char buf[128];
-    char lcd[4];
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    LM_FLOW_CONTROL flow_control;
-
-    pUmDevice->delayed_link_ind = 0;
-    memset(lcd, 0x0, 4);
-
-    if (Status == LM_STATUS_LINK_DOWN) {
-	sprintf(buf,"eth%d: %s: NIC Link is down\n",
-		pUmDevice->index,pUmDevice->name);
-	lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?';
-    } else if (Status == LM_STATUS_LINK_ACTIVE) {
-	sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name);
-
-	if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){
-	    strcat(buf,"1000 Mbps ");
-	    lcd[0] = '1';lcd[1]='G';lcd[2]='B';
-	} else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){
-	    strcat(buf,"100 Mbps ");
-	    lcd[0] = '1';lcd[1]='0';lcd[2]='0';
-	} else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){
-	    strcat(buf,"10 Mbps ");
-	    lcd[0] = '1';lcd[1]='0';lcd[2]=' ';
-	}
-	if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){
-	    strcat(buf, "full duplex");
-	    lcd[3] = 'F';
-	} else {
-	    strcat(buf, "half duplex");
-	    lcd[3] = 'H';
-	}
-	strcat(buf, " link up");
-
-	flow_control = pDevice->FlowControl &
-	    (LM_FLOW_CONTROL_RECEIVE_PAUSE |
-	     LM_FLOW_CONTROL_TRANSMIT_PAUSE);
-
-	if (flow_control) {
-	    if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
-		strcat(buf,", receive ");
-		if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
-		    strcat(buf," & transmit ");
-	    }
-	    else {
-		strcat(buf,", transmit ");
-	    }
-	    strcat(buf,"flow control ON");
-	} else {
-	    strcat(buf, ", flow control OFF");
-	}
-	strcat(buf,"\n");
-	printf("%s",buf);
-    }
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
-{
-
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    PUM_PACKET pUmPacket;
-    void *skb;
-
-    pUmPacket = (PUM_PACKET) pPacket;
-
-    if ((skb = pUmPacket->skbuff))
-	bcm570xPktFree(pUmDevice->index, skb);
-
-    pUmPacket->skbuff = 0;
-
-    return LM_STATUS_SUCCESS;
-}
-
-unsigned long
-MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
-{
-    return get_timer(0);
-}
-
-/*
- *   Transform an MBUF chain into a single MBUF.
- *   This routine will fail if the amount of data in the
- *   chain overflows a transmit buffer.  In that case,
- *   the incoming MBUF chain will be freed.  This routine can
- *   also fail by not being able to allocate a new MBUF (including
- *   cluster and mbuf headers).  In that case the failure is
- *   non-fatal.  The incoming cluster chain is not freed, giving
- *   the caller the choice of whether to try a retransmit later.
- */
-LM_STATUS
-MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
-{
-    PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    void *skbnew;
-    int len = 0;
-
-    if (len == 0)
-	return (LM_STATUS_SUCCESS);
-
-    if (len > MAX_PACKET_SIZE){
-	printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
-		pUmDevice->index, len);
-	return (LM_STATUS_FAILURE);
-    }
-
-    skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE);
-
-    if (skbnew == NULL) {
-	pUmDevice->tx_full = 1;
-	printf ("eth%d: out of transmit buffers", pUmDevice->index);
-	return (LM_STATUS_FAILURE);
-    }
-
-    /* New packet values */
-    pUmPacket->skbuff = skbnew;
-    pUmPacket->lm_packet.u.Tx.FragCount = 1;
-
-    return (LM_STATUS_SUCCESS);
-}
-
-
-LM_STATUS
-MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice)
-{
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    pUmDevice->rx_pkt = 1;
-    return LM_STATUS_SUCCESS;
-}
-
-LM_STATUS
-MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
-{
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    PLM_PACKET pPacket;
-    PUM_PACKET pUmPacket;
-    void *skb;
-    while ( TRUE ) {
-
-	pPacket = (PLM_PACKET)
-	    QQ_PopHead(&pDevice->TxPacketXmittedQ.Container);
-
-	if (pPacket == 0)
-	    break;
-
-	pUmPacket = (PUM_PACKET) pPacket;
-	skb = (void*)pUmPacket->skbuff;
-
-	/*
-	* Free MBLK if we transmitted a fragmented packet or a
-	* non-fragmented packet straight from the VxWorks
-	* buffer pool. If packet was copied to a local transmit
-	* buffer, then there's no MBUF to free, just free
-	* the transmit buffer back to the cluster pool.
-	*/
-
-	if (skb)
-	    bcm570xPktFree (pUmDevice->index, skb);
-
-	pUmPacket->skbuff = 0;
-	QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
-	pUmDevice->tx_pkt = 1;
-    }
-    if (pUmDevice->tx_full) {
-	if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >=
-	    (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1))
-	    pUmDevice->tx_full = 0;
-    }
-    return LM_STATUS_SUCCESS;
-}
-
-/*
- *  Scan an MBUF chain until we reach fragment number "frag"
- *  Return its length and physical address.
- */
-void MM_MapTxDma
-    (
-    PLM_DEVICE_BLOCK pDevice,
-    struct _LM_PACKET *pPacket,
-    T3_64BIT_HOST_ADDR *paddr,
-    LM_UINT32 *len,
-    int frag)
-{
-    PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
-    *len = pPacket->PacketSize;
-    MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
-}
-
-/*
- *  Convert an mbuf address, a CPU local virtual address,
- *  to a physical address as seen from a PCI device.  Store the
- *  result at paddr.
- */
-void MM_MapRxDma(
-		 PLM_DEVICE_BLOCK pDevice,
-		 struct _LM_PACKET *pPacket,
-		 T3_64BIT_HOST_ADDR *paddr)
-{
-    PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
-    MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
-}
-
-void
-MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr)
-{
-#if (BITS_PER_LONG == 64)
-	paddr->High = ((unsigned long) addr) >> 32;
-	paddr->Low = ((unsigned long) addr) & 0xffffffff;
-#else
-	paddr->High = 0;
-	paddr->Low = (unsigned long) addr;
-#endif
-}
-
-void
-MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
-{
-	unsigned long baddr = (unsigned long) addr;
-#if (BITS_PER_LONG == 64)
-	set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32);
-#else
-	set_64bit_addr(paddr, baddr, 0);
-#endif
-}
-
-/*
- * This combination of `inline' and `extern' has almost the effect of a
- * macro.  The way to use it is to put a function definition in a header
- * file with these keywords, and put another copy of the definition
- * (lacking `inline' and `extern') in a library file.  The definition in
- * the header file will cause most calls to the function to be inlined.
- * If any uses of the function remain, they will refer to the single copy
- * in the library.
- */
-void
-atomic_set(atomic_t* entry, int val)
-{
-    entry->counter = val;
-}
-int
-atomic_read(atomic_t* entry)
-{
-    return entry->counter;
-}
-void
-atomic_inc(atomic_t* entry)
-{
-    if(entry)
-	entry->counter++;
-}
-
-void
-atomic_dec(atomic_t* entry)
-{
-    if(entry)
-	entry->counter--;
-}
-
-void
-atomic_sub(int a, atomic_t* entry)
-{
-    if(entry)
-	entry->counter -= a;
-}
-
-void
-atomic_add(int a, atomic_t* entry)
-{
-    if(entry)
-	entry->counter += a;
-}
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-void
-QQ_InitQueue(
-PQQ_CONTAINER pQueue,
-unsigned int QueueSize) {
-    pQueue->Head = 0;
-    pQueue->Tail = 0;
-    pQueue->Size = QueueSize+1;
-    atomic_set(&pQueue->EntryCnt, 0);
-} /* QQ_InitQueue */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-char
-QQ_Full(
-PQQ_CONTAINER pQueue) {
-    unsigned int NewHead;
-
-    NewHead = (pQueue->Head + 1) % pQueue->Size;
-
-    return(NewHead == pQueue->Tail);
-} /* QQ_Full */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-char
-QQ_Empty(
-PQQ_CONTAINER pQueue) {
-    return(pQueue->Head == pQueue->Tail);
-} /* QQ_Empty */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-unsigned int
-QQ_GetSize(
-PQQ_CONTAINER pQueue) {
-    return pQueue->Size;
-} /* QQ_GetSize */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-unsigned int
-QQ_GetEntryCnt(
-PQQ_CONTAINER pQueue) {
-    return atomic_read(&pQueue->EntryCnt);
-} /* QQ_GetEntryCnt */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/*    TRUE entry was added successfully.                                      */
-/*    FALSE queue is full.                                                    */
-/******************************************************************************/
-char
-QQ_PushHead(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
-    unsigned int Head;
-
-    Head = (pQueue->Head + 1) % pQueue->Size;
-
-#if !defined(QQ_NO_OVERFLOW_CHECK)
-    if(Head == pQueue->Tail) {
-	return 0;
-    } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
-
-    pQueue->Array[pQueue->Head] = pEntry;
-    wmb();
-    pQueue->Head = Head;
-    atomic_inc(&pQueue->EntryCnt);
-
-    return -1;
-} /* QQ_PushHead */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/*    TRUE entry was added successfully.                                      */
-/*    FALSE queue is full.                                                    */
-/******************************************************************************/
-char
-QQ_PushTail(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
-    unsigned int Tail;
-
-    Tail = pQueue->Tail;
-    if(Tail == 0) {
-	Tail = pQueue->Size;
-    } /* if */
-    Tail--;
-
-#if !defined(QQ_NO_OVERFLOW_CHECK)
-    if(Tail == pQueue->Head) {
-	return 0;
-    } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
-
-    pQueue->Array[Tail] = pEntry;
-    wmb();
-    pQueue->Tail = Tail;
-    atomic_inc(&pQueue->EntryCnt);
-
-    return -1;
-} /* QQ_PushTail */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-PQQ_ENTRY
-QQ_PopHead(
-PQQ_CONTAINER pQueue) {
-    unsigned int Head;
-    PQQ_ENTRY Entry;
-
-    Head = pQueue->Head;
-
-#if !defined(QQ_NO_UNDERFLOW_CHECK)
-    if(Head == pQueue->Tail) {
-	return (PQQ_ENTRY) 0;
-    } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
-    if(Head == 0) {
-	Head = pQueue->Size;
-    } /* if */
-    Head--;
-
-    Entry = pQueue->Array[Head];
-    membar();
-
-    pQueue->Head = Head;
-    atomic_dec(&pQueue->EntryCnt);
-
-    return Entry;
-} /* QQ_PopHead */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-PQQ_ENTRY
-QQ_PopTail(
-PQQ_CONTAINER pQueue) {
-    unsigned int Tail;
-    PQQ_ENTRY Entry;
-
-    Tail = pQueue->Tail;
-
-#if !defined(QQ_NO_UNDERFLOW_CHECK)
-    if(Tail == pQueue->Head) {
-	return (PQQ_ENTRY) 0;
-    } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
-    Entry = pQueue->Array[Tail];
-    membar();
-    pQueue->Tail = (Tail + 1) % pQueue->Size;
-    atomic_dec(&pQueue->EntryCnt);
-
-    return Entry;
-} /* QQ_PopTail */
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-PQQ_ENTRY
-QQ_GetHead(
-    PQQ_CONTAINER pQueue,
-    unsigned int Idx)
-{
-    if(Idx >= atomic_read(&pQueue->EntryCnt))
-    {
-	return (PQQ_ENTRY) 0;
-    }
-
-    if(pQueue->Head > Idx)
-    {
-	Idx = pQueue->Head - Idx;
-    }
-    else
-    {
-	Idx = pQueue->Size - (Idx - pQueue->Head);
-    }
-    Idx--;
-
-    return pQueue->Array[Idx];
-}
-
-
-/******************************************************************************/
-/* Description:                                                               */
-/*                                                                            */
-/* Return:                                                                    */
-/******************************************************************************/
-PQQ_ENTRY
-QQ_GetTail(
-    PQQ_CONTAINER pQueue,
-    unsigned int Idx)
-{
-    if(Idx >= atomic_read(&pQueue->EntryCnt))
-    {
-	return (PQQ_ENTRY) 0;
-    }
-
-    Idx += pQueue->Tail;
-    if(Idx >= pQueue->Size)
-    {
-	Idx = Idx - pQueue->Size;
-    }
-
-    return pQueue->Array[Idx];
-}
-
-#endif	/* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */
diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c
deleted file mode 100644
index 78d0149284..0000000000
--- a/drivers/net/cs8900.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Cirrus Logic CS8900A Ethernet
- *
- * (C) 2003 Wolfgang Denk, wd@denx.de
- *     Extension to synchronize ethaddr environment variable
- *     against value in EEPROM
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is loaded into SRAM in bootstrap mode, where it waits
- * for commands on UART1 to read and write memory, jump to code etc.
- * A design goal for this program is to be entirely independent of the
- * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
- * this code in bootstrap mode.  All the board specifics can be handled on
- * the host.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <command.h>
-#include "cs8900.h"
-#include <net.h>
-#include <clock.h>
-
-#ifdef CONFIG_DRIVER_CS8900
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
-
-#undef DEBUG
-
-/* packet page register access functions */
-
-#ifdef CS8900_BUS32
-/* we don't need 16 bit initialisation on 32 bit bus */
-#define get_reg_init_bus(x) get_reg((x))
-#else
-static unsigned short get_reg_init_bus (int regno)
-{
-	/* force 16 bit busmode */
-	volatile unsigned char c;
-
-	c = CS8900_BUS16_0;
-	c = CS8900_BUS16_1;
-	c = CS8900_BUS16_0;
-	c = CS8900_BUS16_1;
-	c = CS8900_BUS16_0;
-
-	CS8900_PPTR = regno;
-	return (unsigned short) CS8900_PDATA;
-}
-#endif
-
-static unsigned short get_reg (int regno)
-{
-	CS8900_PPTR = regno;
-	return (unsigned short) CS8900_PDATA;
-}
-
-
-static void put_reg (int regno, unsigned short val)
-{
-	CS8900_PPTR = regno;
-	CS8900_PDATA = val;
-}
-
-static void eth_reset (void)
-{
-	uint64_t start;
-	unsigned short us;
-
-	/* reset NIC */
-	put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset);
-
-	/* wait for 200ms */
-	udelay (200000);
-	/* Wait until the chip is reset */
-
-	start = get_time_ns();
-	while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
-		   && !is_timeout(start, SECOND))
-		/*NOP*/;
-}
-
-static void eth_reginit (void)
-{
-	/* receive only error free packets addressed to this card */
-	put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
-	/* do not generate any interrupts on receive operations */
-	put_reg (PP_RxCFG, 0);
-	/* do not generate any interrupts on transmit operations */
-	put_reg (PP_TxCFG, 0);
-	/* do not generate any interrupts on buffer operations */
-	put_reg (PP_BufCFG, 0);
-	/* enable transmitter/receiver mode */
-	put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
-}
-
-void cs8900_get_enetaddr (uchar * addr)
-{
-	int i;
-	unsigned char env_enetaddr[6];
-	char *tmp = getenv ("ethaddr");
-	char *end;
-
-	for (i=0; i<6; i++) {
-		env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
-		if (tmp)
-			tmp = (*end) ? end+1 : end;
-	}
-
-	/* verify chip id */
-	if (get_reg_init_bus (PP_ChipID) != 0x630e)
-		return;
-	eth_reset ();
-	if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
-			(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
-
-		/* Load the MAC from EEPROM */
-		for (i = 0; i < 6 / 2; i++) {
-			unsigned int Addr;
-
-			Addr = get_reg (PP_IA + i * 2);
-			addr[i * 2] = Addr & 0xFF;
-			addr[i * 2 + 1] = Addr >> 8;
-		}
-
-		if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
-		    memcmp(env_enetaddr, addr, 6) != 0) {
-			printf ("\nWarning: MAC addresses don't match:\n");
-			printf ("\tHW MAC address:  "
-				"%02X:%02X:%02X:%02X:%02X:%02X\n",
-				addr[0], addr[1],
-				addr[2], addr[3],
-				addr[4], addr[5] );
-			printf ("\t\"ethaddr\" value: "
-				"%02X:%02X:%02X:%02X:%02X:%02X\n",
-				env_enetaddr[0], env_enetaddr[1],
-				env_enetaddr[2], env_enetaddr[3],
-				env_enetaddr[4], env_enetaddr[5]) ;
-			debug ("### Set MAC addr from environment\n");
-			memcpy (addr, env_enetaddr, 6);
-		}
-		if (!tmp) {
-			char ethaddr[20];
-			sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-				 addr[0], addr[1],
-				 addr[2], addr[3],
-				 addr[4], addr[5]) ;
-			debug ("### Set environment from HW MAC addr = \"%s\"\n",				ethaddr);
-			setenv ("ethaddr", ethaddr);
-		}
-
-	}
-}
-
-void eth_halt (void)
-{
-	/* disable transmitter/receiver mode */
-	put_reg (PP_LineCTL, 0);
-
-	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
-	get_reg_init_bus (PP_ChipID);
-}
-
-int eth_init (bd_t * bd)
-{
-
-	/* verify chip id */
-	if (get_reg_init_bus (PP_ChipID) != 0x630e) {
-		printf ("CS8900 Ethernet chip not found?!\n");
-		return 0;
-	}
-
-	eth_reset ();
-	/* set the ethernet address */
-	put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8));
-	put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8));
-	put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8));
-
-	eth_reginit ();
-	return 0;
-}
-
-/* Get a data block via Ethernet */
-extern int eth_rx (void)
-{
-	int i;
-	unsigned short rxlen;
-	unsigned short *addr;
-	unsigned short status;
-
-	status = get_reg (PP_RER);
-
-	if ((status & PP_RER_RxOK) == 0)
-		return 0;
-
-	status = CS8900_RTDATA;		/* stat */
-	rxlen = CS8900_RTDATA;		/* len */
-
-#ifdef DEBUG
-	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
-		printf ("packet too big!\n");
-#endif
-	for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0;
-		 i--)
-		*addr++ = CS8900_RTDATA;
-	if (rxlen & 1)
-		*addr++ = CS8900_RTDATA;
-
-	/* Pass the packet up to the protocol layers. */
-	NetReceive (NetRxPackets[0], rxlen);
-
-	return rxlen;
-}
-
-/* Send a data block via Ethernet. */
-extern int eth_send (volatile void *packet, int length)
-{
-	volatile unsigned short *addr;
-	uint64_t start;
-	unsigned short s;
-
-retry:
-	/* initiate a transmit sequence */
-	CS8900_TxCMD = PP_TxCmd_TxStart_Full;
-	CS8900_TxLEN = length;
-
-	/* Test to see if the chip has allocated memory for the packet */
-	if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
-		/* Oops... this should not happen! */
-#ifdef DEBUG
-		printf ("cs: unable to send packet; retrying...\n");
-#endif
-		/* FIXME */
-		udelay(5000);
-
-		eth_reset ();
-		eth_reginit ();
-		goto retry;
-	}
-
-	/* Write the contents of the packet */
-	/* assume even number of bytes */
-	for (addr = packet; length > 0; length -= 2)
-		CS8900_RTDATA = *addr++;
-
-	/* wait for transfer to succeed */
-	start = get_time_ns();
-	while ((s = get_reg (PP_TER) & ~0x1F) == 0) {
-		if (is_timeout(start, SECOND))
-			break;
-	}
-
-	/* nothing */ ;
-	if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
-#ifdef DEBUG
-		printf ("\ntransmission error %#x\n", s);
-#endif
-	}
-
-	return 0;
-}
-
-static void cs8900_e2prom_ready(void)
-{
-	while(get_reg(PP_SelfST) & SI_BUSY);
-}
-
-/***********************************************************/
-/* read a 16-bit word out of the EEPROM                    */
-/***********************************************************/
-
-int cs8900_e2prom_read(unsigned char addr, unsigned short *value)
-{
-	cs8900_e2prom_ready();
-	put_reg(PP_EECMD, EEPROM_READ_CMD | addr);
-	cs8900_e2prom_ready();
-	*value = get_reg(PP_EEData);
-
-	return 0;
-}
-
-
-/***********************************************************/
-/* write a 16-bit word into the EEPROM                     */
-/***********************************************************/
-
-int cs8900_e2prom_write(unsigned char addr, unsigned short value)
-{
-	cs8900_e2prom_ready();
-	put_reg(PP_EECMD, EEPROM_WRITE_EN);
-	cs8900_e2prom_ready();
-	put_reg(PP_EEData, value);
-	put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr);
-	cs8900_e2prom_ready();
-	put_reg(PP_EECMD, EEPROM_WRITE_DIS);
-	cs8900_e2prom_ready();
-
-	return 0;
-}
-
-#endif	/* COMMANDS & CFG_NET */
-
-#endif	/* CONFIG_DRIVER_CS8900 */
diff --git a/drivers/net/cs8900.h b/drivers/net/cs8900.h
deleted file mode 100644
index f886d103c1..0000000000
--- a/drivers/net/cs8900.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Cirrus Logic CS8900A Ethernet
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is loaded into SRAM in bootstrap mode, where it waits
- * for commands on UART1 to read and write memory, jump to code etc.
- * A design goal for this program is to be entirely independent of the
- * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
- * this code in bootstrap mode.  All the board specifics can be handled on
- * the host.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#ifdef CONFIG_DRIVER_CS8900
-
-/* although the registers are 16 bit, they are 32-bit aligned on the
-   EDB7111. so we have to read them as 32-bit registers and ignore the
-   upper 16-bits. i'm not sure if this holds for the EDB7211. */
-
-#ifdef CS8900_BUS16
-  /* 16 bit aligned registers, 16 bit wide */
-  #define CS8900_REG u16
-  #define CS8900_OFF 0x02
-  #define CS8900_BUS16_0  *(volatile u8 *)(CS8900_BASE+0x00)
-  #define CS8900_BUS16_1  *(volatile u8 *)(CS8900_BASE+0x01)
-#elif  defined(CS8900_BUS32)
-  /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
-  #define CS8900_REG u32
-  #define CS8900_OFF 0x04
-#else
-  #error unknown bussize ...
-#endif
-
-#define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF)
-#define CS8900_TxCMD  *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF)
-#define CS8900_TxLEN  *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF)
-#define CS8900_ISQ    *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF)
-#define CS8900_PPTR   *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF)
-#define CS8900_PDATA  *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF)
-
-
-#define ISQ_RxEvent     0x04
-#define ISQ_TxEvent     0x08
-#define ISQ_BufEvent    0x0C
-#define ISQ_RxMissEvent 0x10
-#define ISQ_TxColEvent  0x12
-#define ISQ_EventMask   0x3F
-
-/* packet page register offsets */
-
-/* bus interface registers */
-#define PP_ChipID    0x0000  /* Chip identifier - must be 0x630E */
-#define PP_ChipRev   0x0002  /* Chip revision, model codes */
-
-#define PP_IntReg    0x0022  /* Interrupt configuration */
-#define PP_IntReg_IRQ0         0x0000  /* Use INTR0 pin */
-#define PP_IntReg_IRQ1         0x0001  /* Use INTR1 pin */
-#define PP_IntReg_IRQ2         0x0002  /* Use INTR2 pin */
-#define PP_IntReg_IRQ3         0x0003  /* Use INTR3 pin */
-
-/* status and control registers */
-
-#define PP_RxCFG     0x0102  /* Receiver configuration */
-#define PP_RxCFG_Skip1         0x0040  /* Skip (i.e. discard) current frame */
-#define PP_RxCFG_Stream        0x0080  /* Enable streaming mode */
-#define PP_RxCFG_RxOK          0x0100  /* RxOK interrupt enable */
-#define PP_RxCFG_RxDMAonly     0x0200  /* Use RxDMA for all frames */
-#define PP_RxCFG_AutoRxDMA     0x0400  /* Select RxDMA automatically */
-#define PP_RxCFG_BufferCRC     0x0800  /* Include CRC characters in frame */
-#define PP_RxCFG_CRC           0x1000  /* Enable interrupt on CRC error */
-#define PP_RxCFG_RUNT          0x2000  /* Enable interrupt on RUNT frames */
-#define PP_RxCFG_EXTRA         0x4000  /* Enable interrupt on frames with extra data */
-
-#define PP_RxCTL     0x0104  /* Receiver control */
-#define PP_RxCTL_IAHash        0x0040  /* Accept frames that match hash */
-#define PP_RxCTL_Promiscuous   0x0080  /* Accept any frame */
-#define PP_RxCTL_RxOK          0x0100  /* Accept well formed frames */
-#define PP_RxCTL_Multicast     0x0200  /* Accept multicast frames */
-#define PP_RxCTL_IA            0x0400  /* Accept frame that matches IA */
-#define PP_RxCTL_Broadcast     0x0800  /* Accept broadcast frames */
-#define PP_RxCTL_CRC           0x1000  /* Accept frames with bad CRC */
-#define PP_RxCTL_RUNT          0x2000  /* Accept runt frames */
-#define PP_RxCTL_EXTRA         0x4000  /* Accept frames that are too long */
-
-#define PP_TxCFG     0x0106  /* Transmit configuration */
-#define PP_TxCFG_CRS           0x0040  /* Enable interrupt on loss of carrier */
-#define PP_TxCFG_SQE           0x0080  /* Enable interrupt on Signal Quality Error */
-#define PP_TxCFG_TxOK          0x0100  /* Enable interrupt on successful xmits */
-#define PP_TxCFG_Late          0x0200  /* Enable interrupt on "out of window" */
-#define PP_TxCFG_Jabber        0x0400  /* Enable interrupt on jabber detect */
-#define PP_TxCFG_Collision     0x0800  /* Enable interrupt if collision */
-#define PP_TxCFG_16Collisions  0x8000  /* Enable interrupt if > 16 collisions */
-
-#define PP_TxCmd     0x0108  /* Transmit command status */
-#define PP_TxCmd_TxStart_5     0x0000  /* Start after 5 bytes in buffer */
-#define PP_TxCmd_TxStart_381   0x0040  /* Start after 381 bytes in buffer */
-#define PP_TxCmd_TxStart_1021  0x0080  /* Start after 1021 bytes in buffer */
-#define PP_TxCmd_TxStart_Full  0x00C0  /* Start after all bytes loaded */
-#define PP_TxCmd_Force         0x0100  /* Discard any pending packets */
-#define PP_TxCmd_OneCollision  0x0200  /* Abort after a single collision */
-#define PP_TxCmd_NoCRC         0x1000  /* Do not add CRC */
-#define PP_TxCmd_NoPad         0x2000  /* Do not pad short packets */
-
-#define PP_BufCFG    0x010A  /* Buffer configuration */
-#define PP_BufCFG_SWI          0x0040  /* Force interrupt via software */
-#define PP_BufCFG_RxDMA        0x0080  /* Enable interrupt on Rx DMA */
-#define PP_BufCFG_TxRDY        0x0100  /* Enable interrupt when ready for Tx */
-#define PP_BufCFG_TxUE         0x0200  /* Enable interrupt in Tx underrun */
-#define PP_BufCFG_RxMiss       0x0400  /* Enable interrupt on missed Rx packets */
-#define PP_BufCFG_Rx128        0x0800  /* Enable Rx interrupt after 128 bytes */
-#define PP_BufCFG_TxCol        0x1000  /* Enable int on Tx collision ctr overflow */
-#define PP_BufCFG_Miss         0x2000  /* Enable int on Rx miss ctr overflow */
-#define PP_BufCFG_RxDest       0x8000  /* Enable int on Rx dest addr match */
-
-#define PP_LineCTL   0x0112  /* Line control */
-#define PP_LineCTL_Rx          0x0040  /* Enable receiver */
-#define PP_LineCTL_Tx          0x0080  /* Enable transmitter */
-#define PP_LineCTL_AUIonly     0x0100  /* AUI interface only */
-#define PP_LineCTL_AutoAUI10BT 0x0200  /* Autodetect AUI or 10BaseT interface */
-#define PP_LineCTL_ModBackoffE 0x0800  /* Enable modified backoff algorithm */
-#define PP_LineCTL_PolarityDis 0x1000  /* Disable Rx polarity autodetect */
-#define PP_LineCTL_2partDefDis 0x2000  /* Disable two-part defferal */
-#define PP_LineCTL_LoRxSquelch 0x4000  /* Reduce receiver squelch threshold */
-
-#define PP_SelfCTL   0x0114  /* Chip self control */
-#define PP_SelfCTL_Reset       0x0040  /* Self-clearing reset */
-#define PP_SelfCTL_SWSuspend   0x0100  /* Initiate suspend mode */
-#define PP_SelfCTL_HWSleepE    0x0200  /* Enable SLEEP input */
-#define PP_SelfCTL_HWStandbyE  0x0400  /* Enable standby mode */
-#define PP_SelfCTL_HC0E        0x1000  /* use HCB0 for LINK LED */
-#define PP_SelfCTL_HC1E        0x2000  /* use HCB1 for BSTATUS LED */
-#define PP_SelfCTL_HCB0        0x4000  /* control LINK LED if HC0E set */
-#define PP_SelfCTL_HCB1        0x8000  /* control BSTATUS LED if HC1E set */
-
-#define PP_BusCTL    0x0116  /* Bus control */
-#define PP_BusCTL_ResetRxDMA   0x0040  /* Reset RxDMA pointer */
-#define PP_BusCTL_DMAextend    0x0100  /* Extend DMA cycle */
-#define PP_BusCTL_UseSA        0x0200  /* Assert MEMCS16 on address decode */
-#define PP_BusCTL_MemoryE      0x0400  /* Enable memory mode */
-#define PP_BusCTL_DMAburst     0x0800  /* Limit DMA access burst */
-#define PP_BusCTL_IOCHRDYE     0x1000  /* Set IOCHRDY high impedence */
-#define PP_BusCTL_RxDMAsize    0x2000  /* Set DMA buffer size 64KB */
-#define PP_BusCTL_EnableIRQ    0x8000  /* Generate interrupt on interrupt event */
-
-#define PP_TestCTL   0x0118  /* Test control */
-#define PP_TestCTL_DisableLT   0x0080  /* Disable link status */
-#define PP_TestCTL_ENDECloop   0x0200  /* Internal loopback */
-#define PP_TestCTL_AUIloop     0x0400  /* AUI loopback */
-#define PP_TestCTL_DisBackoff  0x0800  /* Disable backoff algorithm */
-#define PP_TestCTL_FDX         0x4000  /* Enable full duplex mode */
-
-#define PP_ISQ       0x0120  /* Interrupt Status Queue */
-
-#define PP_RER       0x0124  /* Receive event */
-#define PP_RER_IAHash          0x0040  /* Frame hash match */
-#define PP_RER_Dribble         0x0080  /* Frame had 1-7 extra bits after last byte */
-#define PP_RER_RxOK            0x0100  /* Frame received with no errors */
-#define PP_RER_Hashed          0x0200  /* Frame address hashed OK */
-#define PP_RER_IA              0x0400  /* Frame address matched IA */
-#define PP_RER_Broadcast       0x0800  /* Broadcast frame */
-#define PP_RER_CRC             0x1000  /* Frame had CRC error */
-#define PP_RER_RUNT            0x2000  /* Runt frame */
-#define PP_RER_EXTRA           0x4000  /* Frame was too long */
-
-#define PP_TER       0x0128 /* Transmit event */
-#define PP_TER_CRS             0x0040  /* Carrier lost */
-#define PP_TER_SQE             0x0080  /* Signal Quality Error */
-#define PP_TER_TxOK            0x0100  /* Packet sent without error */
-#define PP_TER_Late            0x0200  /* Out of window */
-#define PP_TER_Jabber          0x0400  /* Stuck transmit? */
-#define PP_TER_NumCollisions   0x7800  /* Number of collisions */
-#define PP_TER_16Collisions    0x8000  /* > 16 collisions */
-
-#define PP_BER       0x012C /* Buffer event */
-#define PP_BER_SWint           0x0040 /* Software interrupt */
-#define PP_BER_RxDMAFrame      0x0080 /* Received framed DMAed */
-#define PP_BER_Rdy4Tx          0x0100 /* Ready for transmission */
-#define PP_BER_TxUnderrun      0x0200 /* Transmit underrun */
-#define PP_BER_RxMiss          0x0400 /* Received frame missed */
-#define PP_BER_Rx128           0x0800 /* 128 bytes received */
-#define PP_BER_RxDest          0x8000 /* Received framed passed address filter */
-
-#define PP_RxMiss    0x0130  /*  Receiver miss counter */
-
-#define PP_TxCol     0x0132  /*  Transmit collision counter */
-
-#define PP_LineSTAT  0x0134  /* Line status */
-#define PP_LineSTAT_LinkOK     0x0080  /* Line is connected and working */
-#define PP_LineSTAT_AUI        0x0100  /* Connected via AUI */
-#define PP_LineSTAT_10BT       0x0200  /* Connected via twisted pair */
-#define PP_LineSTAT_Polarity   0x1000  /* Line polarity OK (10BT only) */
-#define PP_LineSTAT_CRS        0x4000  /* Frame being received */
-
-#define PP_SelfSTAT  0x0136  /* Chip self status */
-#define PP_SelfSTAT_33VActive  0x0040  /* supply voltage is 3.3V */
-#define PP_SelfSTAT_InitD      0x0080  /* Chip initialization complete */
-#define PP_SelfSTAT_SIBSY      0x0100  /* EEPROM is busy */
-#define PP_SelfSTAT_EEPROM     0x0200  /* EEPROM present */
-#define PP_SelfSTAT_EEPROM_OK  0x0400  /* EEPROM checks out */
-#define PP_SelfSTAT_ELPresent  0x0800  /* External address latch logic available */
-#define PP_SelfSTAT_EEsize     0x1000  /* Size of EEPROM */
-
-#define PP_BusSTAT   0x0138  /* Bus status */
-#define PP_BusSTAT_TxBid       0x0080  /* Tx error */
-#define PP_BusSTAT_TxRDY       0x0100  /* Ready for Tx data */
-
-#define PP_TDR       0x013C  /* AUI Time Domain Reflectometer */
-
-/* initiate transmit registers */
-
-#define PP_TxCommand 0x0144  /* Tx Command */
-#define PP_TxLength  0x0146  /* Tx Length */
-
-
-/* address filter registers */
-
-#define PP_LAF       0x0150  /* Logical address filter (6 bytes) */
-#define PP_IA        0x0158  /* Individual address (MAC) */
-
-/* EEPROM Kram */
-#define SI_BUSY 0x0100
-#define PP_SelfST 0x0136	/*  Self State register */
-#define PP_EECMD 0x0040		/*  NVR Interface Command register */
-#define PP_EEData 0x0042	/*  NVR Interface Data Register */
-#define EEPROM_WRITE_EN		0x00F0
-#define EEPROM_WRITE_DIS	0x0000
-#define EEPROM_WRITE_CMD	0x0100
-#define EEPROM_READ_CMD		0x0200
-#define EEPROM_ERASE_CMD	0x0300
-
-extern int cs8900_e2prom_read(uchar, ushort *);
-extern int cs8900_e2prom_write(uchar, ushort);
-
-#endif /* CONFIG_DRIVER_CS8900 */
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
deleted file mode 100644
index 821406ce43..0000000000
--- a/drivers/net/e1000.c
+++ /dev/null
@@ -1,2774 +0,0 @@
-/**************************************************************************
-Inter Pro 1000 for ppcboot/das-u-boot
-Drivers are port from Intel's Linux driver e1000-4.3.15
-and from Etherboot pro 1000 driver by mrakes at vivato dot net
-tested on both gig copper and gig fiber boards
-***************************************************************************/
-/*******************************************************************************
-
-
-  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
-
-  This program is free software; you can redistribute it and/or modify it
-  under the terms of the GNU General Public License as published by the Free
-  Software Foundation; either version 2 of the License, or (at your option)
-  any later version.
-
-  This program is distributed in the hope that it will be useful, but WITHOUT
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-  more details.
-
-  You should have received a copy of the GNU General Public License along with
-  this program; if not, write to the Free Software Foundation, Inc., 59
-  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-
-  The full GNU General Public License is included in this distribution in the
-  file called LICENSE.
-
-  Contact Information:
-  Linux NICS <linux.nics@intel.com>
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-/*
- *  Copyright (C) Archway Digital Solutions.
- *
- *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
- *  2/9/2002
- *
- *  Copyright (C) Linux Networx.
- *  Massive upgrade to work with the new intel gigabit NICs.
- *  <ebiederman at lnxi dot com>
- */
-
-#include "e1000.h"
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
-	defined(CONFIG_E1000)
-
-#define TOUT_LOOP   100000
-
-#undef	virt_to_bus
-#define	virt_to_bus(x)	((unsigned long)x)
-#define bus_to_phys(devno, a)	pci_mem_to_phys(devno, a)
-#define mdelay(n)       udelay((n)*1000)
-
-#define E1000_DEFAULT_PBA    0x00000030
-
-/* NIC specific static variables go here */
-
-static char tx_pool[128 + 16];
-static char rx_pool[128 + 16];
-static char packet[2096];
-
-static struct e1000_tx_desc *tx_base;
-static struct e1000_rx_desc *rx_base;
-
-static int tx_tail;
-static int rx_tail, rx_last;
-
-static struct pci_device_id supported[] = {
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
-};
-
-/* Function forward declarations */
-static int e1000_setup_link(struct eth_device *nic);
-static int e1000_setup_fiber_link(struct eth_device *nic);
-static int e1000_setup_copper_link(struct eth_device *nic);
-static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
-static void e1000_config_collision_dist(struct e1000_hw *hw);
-static int e1000_config_mac_to_phy(struct e1000_hw *hw);
-static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
-static int e1000_check_for_link(struct eth_device *nic);
-static int e1000_wait_autoneg(struct e1000_hw *hw);
-static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
-				       uint16_t * duplex);
-static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
-			      uint16_t * phy_data);
-static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
-			       uint16_t phy_data);
-static void e1000_phy_hw_reset(struct e1000_hw *hw);
-static int e1000_phy_reset(struct e1000_hw *hw);
-static int e1000_detect_gig_phy(struct e1000_hw *hw);
-
-#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
-#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
-			writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
-#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
-	readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
-#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
-
-#ifndef CONFIG_AP1000 /* remove for warnings */
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
-{
-	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
-	 * wait 50 microseconds.
-	 */
-	*eecd = *eecd | E1000_EECD_SK;
-	E1000_WRITE_REG(hw, EECD, *eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(50);
-}
-
-/******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
-{
-	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
-	 * wait 50 microseconds.
-	 */
-	*eecd = *eecd & ~E1000_EECD_SK;
-	E1000_WRITE_REG(hw, EECD, *eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(50);
-}
-
-/******************************************************************************
- * Shift data bits out to the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
- *****************************************************************************/
-static void
-e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
-{
-	uint32_t eecd;
-	uint32_t mask;
-
-	/* We need to shift "count" bits out to the EEPROM. So, value in the
-	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
-	 * In order to do this, "data" must be broken down into bits.
-	 */
-	mask = 0x01 << (count - 1);
-	eecd = E1000_READ_REG(hw, EECD);
-	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-	do {
-		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
-		 * and then raising and then lowering the clock (the SK bit controls
-		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
-		 * by setting "DI" to "0" and then raising and then lowering the clock.
-		 */
-		eecd &= ~E1000_EECD_DI;
-
-		if (data & mask)
-			eecd |= E1000_EECD_DI;
-
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-
-		udelay(50);
-
-		e1000_raise_ee_clk(hw, &eecd);
-		e1000_lower_ee_clk(hw, &eecd);
-
-		mask = mask >> 1;
-
-	} while (mask);
-
-	/* We leave the "DI" bit set to "0" when we leave this routine. */
-	eecd &= ~E1000_EECD_DI;
-	E1000_WRITE_REG(hw, EECD, eecd);
-}
-
-/******************************************************************************
- * Shift data bits in from the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static uint16_t
-e1000_shift_in_ee_bits(struct e1000_hw *hw)
-{
-	uint32_t eecd;
-	uint32_t i;
-	uint16_t data;
-
-	/* In order to read a register from the EEPROM, we need to shift 16 bits
-	 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
-	 * the EEPROM (setting the SK bit), and then reading the value of the "DO"
-	 * bit.  During this "shifting in" process the "DI" bit should always be
-	 * clear..
-	 */
-
-	eecd = E1000_READ_REG(hw, EECD);
-
-	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-	data = 0;
-
-	for (i = 0; i < 16; i++) {
-		data = data << 1;
-		e1000_raise_ee_clk(hw, &eecd);
-
-		eecd = E1000_READ_REG(hw, EECD);
-
-		eecd &= ~(E1000_EECD_DI);
-		if (eecd & E1000_EECD_DO)
-			data |= 1;
-
-		e1000_lower_ee_clk(hw, &eecd);
-	}
-
-	return data;
-}
-
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
- * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
-static void
-e1000_setup_eeprom(struct e1000_hw *hw)
-{
-	uint32_t eecd;
-
-	eecd = E1000_READ_REG(hw, EECD);
-
-	/* Clear SK and DI */
-	eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
-	E1000_WRITE_REG(hw, EECD, eecd);
-
-	/* Set CS */
-	eecd |= E1000_EECD_CS;
-	E1000_WRITE_REG(hw, EECD, eecd);
-}
-
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_standby_eeprom(struct e1000_hw *hw)
-{
-	uint32_t eecd;
-
-	eecd = E1000_READ_REG(hw, EECD);
-
-	/* Deselct EEPROM */
-	eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-	E1000_WRITE_REG(hw, EECD, eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(50);
-
-	/* Clock high */
-	eecd |= E1000_EECD_SK;
-	E1000_WRITE_REG(hw, EECD, eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(50);
-
-	/* Select EEPROM */
-	eecd |= E1000_EECD_CS;
-	E1000_WRITE_REG(hw, EECD, eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(50);
-
-	/* Clock low */
-	eecd &= ~E1000_EECD_SK;
-	E1000_WRITE_REG(hw, EECD, eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(50);
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- *****************************************************************************/
-static int
-e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data)
-{
-	uint32_t eecd;
-	uint32_t i = 0;
-	int large_eeprom = FALSE;
-
-	/* Request EEPROM Access */
-	if (hw->mac_type > e1000_82544) {
-		eecd = E1000_READ_REG(hw, EECD);
-		if (eecd & E1000_EECD_SIZE)
-			large_eeprom = TRUE;
-		eecd |= E1000_EECD_REQ;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		eecd = E1000_READ_REG(hw, EECD);
-		while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
-			i++;
-			udelay(10);
-			eecd = E1000_READ_REG(hw, EECD);
-		}
-		if (!(eecd & E1000_EECD_GNT)) {
-			eecd &= ~E1000_EECD_REQ;
-			E1000_WRITE_REG(hw, EECD, eecd);
-			DEBUGOUT("Could not acquire EEPROM grant\n");
-			return -E1000_ERR_EEPROM;
-		}
-	}
-
-	/*  Prepare the EEPROM for reading  */
-	e1000_setup_eeprom(hw);
-
-	/*  Send the READ command (opcode + addr)  */
-	e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
-	e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6);
-
-	/* Read the data */
-	*data = e1000_shift_in_ee_bits(hw);
-
-	/* End this read operation */
-	e1000_standby_eeprom(hw);
-
-	/* Stop requesting EEPROM access */
-	if (hw->mac_type > e1000_82544) {
-		eecd = E1000_READ_REG(hw, EECD);
-		eecd &= ~E1000_EECD_REQ;
-		E1000_WRITE_REG(hw, EECD, eecd);
-	}
-
-	return 0;
-}
-
-
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Reads the first 64 16 bit words of the EEPROM and sums the values read.
- * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
- * valid.
- *****************************************************************************/
-static int
-e1000_validate_eeprom_checksum(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint16_t checksum = 0;
-	uint16_t i, eeprom_data;
-
-	DEBUGFUNC();
-
-	for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
-		if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
-			DEBUGOUT("EEPROM Read Error\n");
-			return -E1000_ERR_EEPROM;
-		}
-		checksum += eeprom_data;
-	}
-
-	if (checksum == (uint16_t) EEPROM_SUM) {
-		return 0;
-	} else {
-		DEBUGOUT("EEPROM Checksum Invalid\n");
-		return -E1000_ERR_EEPROM;
-	}
-}
-#endif /* #ifndef CONFIG_AP1000 */
-
-/******************************************************************************
- * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
- * second function of dual function devices
- *
- * nic - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int
-e1000_read_mac_addr(struct eth_device *nic)
-{
-#ifndef CONFIG_AP1000
-	struct e1000_hw *hw = nic->priv;
-	uint16_t offset;
-	uint16_t eeprom_data;
-	int i;
-
-	DEBUGFUNC();
-
-	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-		offset = i >> 1;
-		if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
-			DEBUGOUT("EEPROM Read Error\n");
-			return -E1000_ERR_EEPROM;
-		}
-		nic->enetaddr[i] = eeprom_data & 0xff;
-		nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
-	}
-	if ((hw->mac_type == e1000_82546) &&
-	    (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
-		/* Invert the last bit if this is the second device */
-		nic->enetaddr[5] += 1;
-	}
-#else
-	/*
-	 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
-	 * environment variables.  Currently this does not support the addition
-	 * of a PMC e1000 card, which is certainly a possibility, so this should
-	 * be updated to properly use the env variable only for the onboard e1000
-	 */
-
-	int ii;
-	char *s, *e;
-
-	DEBUGFUNC();
-
-	s = getenv ("ethaddr");
-	if (s == NULL){
-		return -E1000_ERR_EEPROM;
-	}
-	else{
-		for(ii = 0; ii < 6; ii++) {
-			nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s){
-				s = (*e) ? e + 1 : e;
-			}
-		}
-	}
-#endif
-	return 0;
-}
-
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- *****************************************************************************/
-static void
-e1000_init_rx_addrs(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint32_t i;
-	uint32_t addr_low;
-	uint32_t addr_high;
-
-	DEBUGFUNC();
-
-	/* Setup the receive address. */
-	DEBUGOUT("Programming MAC Address into RAR[0]\n");
-	addr_low = (nic->enetaddr[0] |
-		    (nic->enetaddr[1] << 8) |
-		    (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
-
-	addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
-
-	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
-	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
-
-	/* Zero out the other 15 receive addresses. */
-	DEBUGOUT("Clearing RAR[1-15]\n");
-	for (i = 1; i < E1000_RAR_ENTRIES; i++) {
-		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
-		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
-	}
-}
-
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_clear_vfta(struct e1000_hw *hw)
-{
-	uint32_t offset;
-
-	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
-		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
-}
-
-/******************************************************************************
- * Set the mac type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int
-e1000_set_mac_type(struct e1000_hw *hw)
-{
-	DEBUGFUNC();
-
-	switch (hw->device_id) {
-	case E1000_DEV_ID_82542:
-		switch (hw->revision_id) {
-		case E1000_82542_2_0_REV_ID:
-			hw->mac_type = e1000_82542_rev2_0;
-			break;
-		case E1000_82542_2_1_REV_ID:
-			hw->mac_type = e1000_82542_rev2_1;
-			break;
-		default:
-			/* Invalid 82542 revision ID */
-			return -E1000_ERR_MAC_TYPE;
-		}
-		break;
-	case E1000_DEV_ID_82543GC_FIBER:
-	case E1000_DEV_ID_82543GC_COPPER:
-		hw->mac_type = e1000_82543;
-		break;
-	case E1000_DEV_ID_82544EI_COPPER:
-	case E1000_DEV_ID_82544EI_FIBER:
-	case E1000_DEV_ID_82544GC_COPPER:
-	case E1000_DEV_ID_82544GC_LOM:
-		hw->mac_type = e1000_82544;
-		break;
-	case E1000_DEV_ID_82540EM:
-	case E1000_DEV_ID_82540EM_LOM:
-		hw->mac_type = e1000_82540;
-		break;
-	case E1000_DEV_ID_82545EM_COPPER:
-	case E1000_DEV_ID_82545EM_FIBER:
-		hw->mac_type = e1000_82545;
-		break;
-	case E1000_DEV_ID_82546EB_COPPER:
-	case E1000_DEV_ID_82546EB_FIBER:
-		hw->mac_type = e1000_82546;
-		break;
-	default:
-		/* Should never have loaded on this device */
-		return -E1000_ERR_MAC_TYPE;
-	}
-	return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Reset the transmit and receive units; mask and clear all interrupts.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-void
-e1000_reset_hw(struct e1000_hw *hw)
-{
-	uint32_t ctrl;
-	uint32_t ctrl_ext;
-	uint32_t icr;
-	uint32_t manc;
-
-	DEBUGFUNC();
-
-	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
-	if (hw->mac_type == e1000_82542_rev2_0) {
-		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-		pci_write_config_word(hw->pdev, PCI_COMMAND,
-				      hw->
-				      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-	}
-
-	/* Clear interrupt mask to stop board from generating interrupts */
-	DEBUGOUT("Masking off all interrupts\n");
-	E1000_WRITE_REG(hw, IMC, 0xffffffff);
-
-	/* Disable the Transmit and Receive units.  Then delay to allow
-	 * any pending transactions to complete before we hit the MAC with
-	 * the global reset.
-	 */
-	E1000_WRITE_REG(hw, RCTL, 0);
-	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
-	E1000_WRITE_FLUSH(hw);
-
-	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
-	hw->tbi_compatibility_on = FALSE;
-
-	/* Delay to allow any outstanding PCI transactions to complete before
-	 * resetting the device
-	 */
-	mdelay(10);
-
-	/* Issue a global reset to the MAC.  This will reset the chip's
-	 * transmit, receive, DMA, and link units.  It will not effect
-	 * the current PCI configuration.  The global reset bit is self-
-	 * clearing, and should clear within a microsecond.
-	 */
-	DEBUGOUT("Issuing a global reset to MAC\n");
-	ctrl = E1000_READ_REG(hw, CTRL);
-
-		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
-
-	/* Force a reload from the EEPROM if necessary */
-	if (hw->mac_type < e1000_82540) {
-		/* Wait for reset to complete */
-		udelay(10);
-		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
-		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-		E1000_WRITE_FLUSH(hw);
-		/* Wait for EEPROM reload */
-		mdelay(2);
-	} else {
-		/* Wait for EEPROM reload (it happens automatically) */
-		mdelay(4);
-		/* Dissable HW ARPs on ASF enabled adapters */
-		manc = E1000_READ_REG(hw, MANC);
-		manc &= ~(E1000_MANC_ARP_EN);
-		E1000_WRITE_REG(hw, MANC, manc);
-	}
-
-	/* Clear interrupt mask to stop board from generating interrupts */
-	DEBUGOUT("Masking off all interrupts\n");
-	E1000_WRITE_REG(hw, IMC, 0xffffffff);
-
-	/* Clear any pending interrupt events. */
-	icr = E1000_READ_REG(hw, ICR);
-
-	/* If MWI was previously enabled, reenable it. */
-	if (hw->mac_type == e1000_82542_rev2_0) {
-		pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-	}
-}
-
-/******************************************************************************
- * Performs basic configuration of the adapter.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Assumes that the controller has previously been reset and is in a
- * post-reset uninitialized state. Initializes the receive address registers,
- * multicast table, and VLAN filter table. Calls routines to setup link
- * configuration and flow control settings. Clears all on-chip counters. Leaves
- * the transmit and receive units disabled and uninitialized.
- *****************************************************************************/
-static int
-e1000_init_hw(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint32_t ctrl, status;
-	uint32_t i;
-	int32_t ret_val;
-	uint16_t pcix_cmd_word;
-	uint16_t pcix_stat_hi_word;
-	uint16_t cmd_mmrbc;
-	uint16_t stat_mmrbc;
-	e1000_bus_type bus_type = e1000_bus_type_unknown;
-
-	DEBUGFUNC();
-	/* Set the Media Type and exit with error if it is not valid. */
-	if (hw->mac_type != e1000_82543) {
-		/* tbi_compatibility is only valid on 82543 */
-		hw->tbi_compatibility_en = FALSE;
-	}
-
-	if (hw->mac_type >= e1000_82543) {
-		status = E1000_READ_REG(hw, STATUS);
-		if (status & E1000_STATUS_TBIMODE) {
-			hw->media_type = e1000_media_type_fiber;
-			/* tbi_compatibility not valid on fiber */
-			hw->tbi_compatibility_en = FALSE;
-		} else {
-			hw->media_type = e1000_media_type_copper;
-		}
-	} else {
-		/* This is an 82542 (fiber only) */
-		hw->media_type = e1000_media_type_fiber;
-	}
-
-	/* Disabling VLAN filtering. */
-	DEBUGOUT("Initializing the IEEE VLAN\n");
-	E1000_WRITE_REG(hw, VET, 0);
-
-	e1000_clear_vfta(hw);
-
-	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
-	if (hw->mac_type == e1000_82542_rev2_0) {
-		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-		pci_write_config_word(hw->pdev, PCI_COMMAND,
-				      hw->
-				      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-		E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
-		E1000_WRITE_FLUSH(hw);
-		mdelay(5);
-	}
-
-	/* Setup the receive address. This involves initializing all of the Receive
-	 * Address Registers (RARs 0 - 15).
-	 */
-	e1000_init_rx_addrs(nic);
-
-	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
-	if (hw->mac_type == e1000_82542_rev2_0) {
-		E1000_WRITE_REG(hw, RCTL, 0);
-		E1000_WRITE_FLUSH(hw);
-		mdelay(1);
-		pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-	}
-
-	/* Zero out the Multicast HASH table */
-	DEBUGOUT("Zeroing the MTA\n");
-	for (i = 0; i < E1000_MC_TBL_SIZE; i++)
-		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
-
-	if (hw->mac_type >= e1000_82543) {
-		status = E1000_READ_REG(hw, STATUS);
-		bus_type = (status & E1000_STATUS_PCIX_MODE) ?
-		    e1000_bus_type_pcix : e1000_bus_type_pci;
-	}
-	/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
-	if (bus_type == e1000_bus_type_pcix) {
-		pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
-				     &pcix_cmd_word);
-		pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
-				     &pcix_stat_hi_word);
-		cmd_mmrbc =
-		    (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
-		    PCIX_COMMAND_MMRBC_SHIFT;
-		stat_mmrbc =
-		    (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
-		    PCIX_STATUS_HI_MMRBC_SHIFT;
-		if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
-			stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
-		if (cmd_mmrbc > stat_mmrbc) {
-			pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
-			pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
-			pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
-					      pcix_cmd_word);
-		}
-	}
-
-	/* Call a subroutine to configure the link and setup flow control. */
-	ret_val = e1000_setup_link(nic);
-
-	/* Set the transmit descriptor write-back policy */
-	if (hw->mac_type > e1000_82544) {
-		ctrl = E1000_READ_REG(hw, TXDCTL);
-		ctrl =
-		    (ctrl & ~E1000_TXDCTL_WTHRESH) |
-		    E1000_TXDCTL_FULL_TX_DESC_WB;
-		E1000_WRITE_REG(hw, TXDCTL, ctrl);
-	}
-
-	return ret_val;
-}
-
-/******************************************************************************
- * Configures flow control and link settings.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Determines which flow control settings to use. Calls the apropriate media-
- * specific link configuration function. Configures the flow control settings.
- * Assuming the adapter has a valid link partner, a valid link should be
- * established. Assumes the hardware has previously been reset and the
- * transmitter and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_link(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint32_t ctrl_ext;
-	int32_t ret_val;
-	uint16_t eeprom_data;
-
-	DEBUGFUNC();
-
-#ifndef CONFIG_AP1000
-	/* Read and store word 0x0F of the EEPROM. This word contains bits
-	 * that determine the hardware's default PAUSE (flow control) mode,
-	 * a bit that determines whether the HW defaults to enabling or
-	 * disabling auto-negotiation, and the direction of the
-	 * SW defined pins. If there is no SW over-ride of the flow
-	 * control setting, then the variable hw->fc will
-	 * be initialized based on a value in the EEPROM.
-	 */
-	if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
-		DEBUGOUT("EEPROM Read Error\n");
-		return -E1000_ERR_EEPROM;
-	}
-#else
-	/* we have to hardcode the proper value for our hardware. */
-	/* this value is for the 82540EM pci card used for prototyping, and it works. */
-	eeprom_data = 0xb220;
-#endif
-
-	if (hw->fc == e1000_fc_default) {
-		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
-			hw->fc = e1000_fc_none;
-		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
-			 EEPROM_WORD0F_ASM_DIR)
-			hw->fc = e1000_fc_tx_pause;
-		else
-			hw->fc = e1000_fc_full;
-	}
-
-	/* We want to save off the original Flow Control configuration just
-	 * in case we get disconnected and then reconnected into a different
-	 * hub or switch with different Flow Control capabilities.
-	 */
-	if (hw->mac_type == e1000_82542_rev2_0)
-		hw->fc &= (~e1000_fc_tx_pause);
-
-	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
-		hw->fc &= (~e1000_fc_rx_pause);
-
-	hw->original_fc = hw->fc;
-
-	DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
-
-	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
-	 * polarity value for the SW controlled pins, and setup the
-	 * Extended Device Control reg with that info.
-	 * This is needed because one of the SW controlled pins is used for
-	 * signal detection.  So this should be done before e1000_setup_pcs_link()
-	 * or e1000_phy_setup() is called.
-	 */
-	if (hw->mac_type == e1000_82543) {
-		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
-			    SWDPIO__EXT_SHIFT);
-		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-	}
-
-	/* Call the necessary subroutine to configure the link. */
-	ret_val = (hw->media_type == e1000_media_type_fiber) ?
-	    e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
-	if (ret_val < 0) {
-		return ret_val;
-	}
-
-	/* Initialize the flow control address, type, and PAUSE timer
-	 * registers to their default values.  This is done even if flow
-	 * control is disabled, because it does not hurt anything to
-	 * initialize these registers.
-	 */
-	DEBUGOUT
-	    ("Initializing the Flow Control address, type and timer regs\n");
-
-	E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
-	E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
-	E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
-	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
-
-	/* Set the flow control receive threshold registers.  Normally,
-	 * these registers will be set to a default threshold that may be
-	 * adjusted later by the driver's runtime code.  However, if the
-	 * ability to transmit pause frames in not enabled, then these
-	 * registers will be set to 0.
-	 */
-	if (!(hw->fc & e1000_fc_tx_pause)) {
-		E1000_WRITE_REG(hw, FCRTL, 0);
-		E1000_WRITE_REG(hw, FCRTH, 0);
-	} else {
-		/* We need to set up the Receive Threshold high and low water marks
-		 * as well as (optionally) enabling the transmission of XON frames.
-		 */
-		if (hw->fc_send_xon) {
-			E1000_WRITE_REG(hw, FCRTL,
-					(hw->fc_low_water | E1000_FCRTL_XONE));
-			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
-		} else {
-			E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
-			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
-		}
-	}
-	return ret_val;
-}
-
-/******************************************************************************
- * Sets up link for a fiber based adapter
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Manipulates Physical Coding Sublayer functions in order to configure
- * link. Assumes the hardware has been previously reset and the transmitter
- * and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_fiber_link(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint32_t ctrl;
-	uint32_t status;
-	uint32_t txcw = 0;
-	uint32_t i;
-	uint32_t signal;
-	int32_t ret_val;
-
-	DEBUGFUNC();
-	/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
-	 * set when the optics detect a signal. On older adapters, it will be
-	 * cleared when there is a signal
-	 */
-	ctrl = E1000_READ_REG(hw, CTRL);
-	if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
-		signal = E1000_CTRL_SWDPIN1;
-	else
-		signal = 0;
-
-	printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
-	       ctrl);
-	/* Take the link out of reset */
-	ctrl &= ~(E1000_CTRL_LRST);
-
-	e1000_config_collision_dist(hw);
-
-	/* Check for a software override of the flow control settings, and setup
-	 * the device accordingly.  If auto-negotiation is enabled, then software
-	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
-	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
-	 * auto-negotiation is disabled, then software will have to manually
-	 * configure the two flow control enable bits in the CTRL register.
-	 *
-	 * The possible values of the "fc" parameter are:
-	 *      0:  Flow control is completely disabled
-	 *      1:  Rx flow control is enabled (we can receive pause frames, but
-	 *          not send pause frames).
-	 *      2:  Tx flow control is enabled (we can send pause frames but we do
-	 *          not support receiving pause frames).
-	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
-	 */
-	switch (hw->fc) {
-	case e1000_fc_none:
-		/* Flow control is completely disabled by a software over-ride. */
-		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
-		break;
-	case e1000_fc_rx_pause:
-		/* RX Flow control is enabled and TX Flow control is disabled by a
-		 * software over-ride. Since there really isn't a way to advertise
-		 * that we are capable of RX Pause ONLY, we will advertise that we
-		 * support both symmetric and asymmetric RX PAUSE. Later, we will
-		 *  disable the adapter's ability to send PAUSE frames.
-		 */
-		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-		break;
-	case e1000_fc_tx_pause:
-		/* TX Flow control is enabled, and RX Flow control is disabled, by a
-		 * software over-ride.
-		 */
-		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
-		break;
-	case e1000_fc_full:
-		/* Flow control (both RX and TX) is enabled by a software over-ride. */
-		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-		break;
-	default:
-		DEBUGOUT("Flow control param set incorrectly\n");
-		return -E1000_ERR_CONFIG;
-		break;
-	}
-
-	/* Since auto-negotiation is enabled, take the link out of reset (the link
-	 * will be in reset, because we previously reset the chip). This will
-	 * restart auto-negotiation.  If auto-neogtiation is successful then the
-	 * link-up status bit will be set and the flow control enable bits (RFCE
-	 * and TFCE) will be set according to their negotiated value.
-	 */
-	DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
-
-	E1000_WRITE_REG(hw, TXCW, txcw);
-	E1000_WRITE_REG(hw, CTRL, ctrl);
-	E1000_WRITE_FLUSH(hw);
-
-	hw->txcw = txcw;
-	mdelay(1);
-
-	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
-	 * indication in the Device Status Register.  Time-out if a link isn't
-	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
-	 * less than 500 milliseconds even if the other end is doing it in SW).
-	 */
-	if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
-		DEBUGOUT("Looking for Link\n");
-		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
-			mdelay(10);
-			status = E1000_READ_REG(hw, STATUS);
-			if (status & E1000_STATUS_LU)
-				break;
-		}
-		if (i == (LINK_UP_TIMEOUT / 10)) {
-			/* AutoNeg failed to achieve a link, so we'll call
-			 * e1000_check_for_link. This routine will force the link up if we
-			 * detect a signal. This will allow us to communicate with
-			 * non-autonegotiating link partners.
-			 */
-			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
-			hw->autoneg_failed = 1;
-			ret_val = e1000_check_for_link(nic);
-			if (ret_val < 0) {
-				DEBUGOUT("Error while checking for link\n");
-				return ret_val;
-			}
-			hw->autoneg_failed = 0;
-		} else {
-			hw->autoneg_failed = 0;
-			DEBUGOUT("Valid Link Found\n");
-		}
-	} else {
-		DEBUGOUT("No Signal Detected\n");
-		return -E1000_ERR_NOLINK;
-	}
-	return 0;
-}
-
-/******************************************************************************
-* Detects which PHY is present and the speed and duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_setup_copper_link(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint32_t ctrl;
-	int32_t ret_val;
-	uint16_t i;
-	uint16_t phy_data;
-
-	DEBUGFUNC();
-
-	ctrl = E1000_READ_REG(hw, CTRL);
-	/* With 82543, we need to force speed and duplex on the MAC equal to what
-	 * the PHY speed and duplex configuration is. In addition, we need to
-	 * perform a hardware reset on the PHY to take it out of reset.
-	 */
-	if (hw->mac_type > e1000_82543) {
-		ctrl |= E1000_CTRL_SLU;
-		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-		E1000_WRITE_REG(hw, CTRL, ctrl);
-	} else {
-		ctrl |=
-		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
-		E1000_WRITE_REG(hw, CTRL, ctrl);
-		e1000_phy_hw_reset(hw);
-	}
-
-	/* Make sure we have a valid PHY */
-	ret_val = e1000_detect_gig_phy(hw);
-	if (ret_val < 0) {
-		DEBUGOUT("Error, did not detect valid phy.\n");
-		return ret_val;
-	}
-	DEBUGOUT("Phy ID = %x \n", hw->phy_id);
-
-	/* Enable CRS on TX. This must be set for half-duplex operation. */
-	if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-
-	phy_data |= M88E1000_PSCR_AUTO_X_MODE;
-
-	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
-	if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
-		DEBUGOUT("PHY Write Error\n");
-		return -E1000_ERR_PHY;
-	}
-
-	/* Force TX_CLK in the Extended PHY Specific Control Register
-	 * to 25MHz clock.
-	 */
-	if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	phy_data |= M88E1000_EPSCR_TX_CLK_25;
-	/* Configure Master and Slave downshift values */
-	phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
-		      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
-	phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
-		     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
-	if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
-		DEBUGOUT("PHY Write Error\n");
-		return -E1000_ERR_PHY;
-	}
-
-	/* SW Reset the PHY so all changes take effect */
-	ret_val = e1000_phy_reset(hw);
-	if (ret_val < 0) {
-		DEBUGOUT("Error Resetting the PHY\n");
-		return ret_val;
-	}
-
-	/* Options:
-	 *   autoneg = 1 (default)
-	 *      PHY will advertise value(s) parsed from
-	 *      autoneg_advertised and fc
-	 *   autoneg = 0
-	 *      PHY will be set to 10H, 10F, 100H, or 100F
-	 *      depending on value parsed from forced_speed_duplex.
-	 */
-
-	/* Is autoneg enabled?  This is enabled by default or by software override.
-	 * If so, call e1000_phy_setup_autoneg routine to parse the
-	 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
-	 * user should have provided a speed/duplex override.  If so, then call
-	 * e1000_phy_force_speed_duplex to parse and set this up.
-	 */
-	/* Perform some bounds checking on the hw->autoneg_advertised
-	 * parameter.  If this variable is zero, then set it to the default.
-	 */
-	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-	/* If autoneg_advertised is zero, we assume it was not defaulted
-	 * by the calling code so we set to advertise full capability.
-	 */
-	if (hw->autoneg_advertised == 0)
-		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
-	ret_val = e1000_phy_setup_autoneg(hw);
-	if (ret_val < 0) {
-		DEBUGOUT("Error Setting up Auto-Negotiation\n");
-		return ret_val;
-	}
-	DEBUGOUT("Restarting Auto-Neg\n");
-
-	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
-	 * the Auto Neg Restart bit in the PHY control register.
-	 */
-	if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
-	if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
-		DEBUGOUT("PHY Write Error\n");
-		return -E1000_ERR_PHY;
-	}
-	/* If we do not wait for autonegtation to complete I
-	 * do not see a valid link status.
-	 */
-	ret_val = e1000_wait_autoneg(hw);
-	if (ret_val < 0) {
-		DEBUGOUT("Error while waiting for autoneg to complete\n");
-		return ret_val;
-	}
-
-	/* Check link status. Wait up to 100 microseconds for link to become
-	 * valid.
-	 */
-	for (i = 0; i < 10; i++) {
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
-			DEBUGOUT("PHY Read Error\n");
-			return -E1000_ERR_PHY;
-		}
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
-			DEBUGOUT("PHY Read Error\n");
-			return -E1000_ERR_PHY;
-		}
-		if (phy_data & MII_SR_LINK_STATUS) {
-			/* We have link, so we need to finish the config process:
-			 *   1) Set up the MAC to the current PHY speed/duplex
-			 *      if we are on 82543.  If we
-			 *      are on newer silicon, we only need to configure
-			 *      collision distance in the Transmit Control Register.
-			 *   2) Set up flow control on the MAC to that established with
-			 *      the link partner.
-			 */
-			if (hw->mac_type >= e1000_82544) {
-				e1000_config_collision_dist(hw);
-			} else {
-				ret_val = e1000_config_mac_to_phy(hw);
-				if (ret_val < 0) {
-					DEBUGOUT
-					    ("Error configuring MAC to PHY settings\n");
-					return ret_val;
-				}
-			}
-			ret_val = e1000_config_fc_after_link_up(hw);
-			if (ret_val < 0) {
-				DEBUGOUT("Error Configuring Flow Control\n");
-				return ret_val;
-			}
-			DEBUGOUT("Valid link established!!!\n");
-			return 0;
-		}
-		udelay(10);
-	}
-
-	DEBUGOUT("Unable to establish link!!!\n");
-	return -E1000_ERR_NOLINK;
-}
-
-/******************************************************************************
-* Configures PHY autoneg and flow control advertisement settings
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_phy_setup_autoneg(struct e1000_hw *hw)
-{
-	uint16_t mii_autoneg_adv_reg;
-	uint16_t mii_1000t_ctrl_reg;
-
-	DEBUGFUNC();
-
-	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
-	if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-
-	/* Read the MII 1000Base-T Control Register (Address 9). */
-	if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-
-	/* Need to parse both autoneg_advertised and fc and set up
-	 * the appropriate PHY registers.  First we will parse for
-	 * autoneg_advertised software override.  Since we can advertise
-	 * a plethora of combinations, we need to check each bit
-	 * individually.
-	 */
-
-	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
-	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
-	 * the  1000Base-T Control Register (Address 9).
-	 */
-	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
-	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
-
-	DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
-
-	/* Do we want to advertise 10 Mb Half Duplex? */
-	if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
-		DEBUGOUT("Advertise 10mb Half duplex\n");
-		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
-	}
-
-	/* Do we want to advertise 10 Mb Full Duplex? */
-	if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
-		DEBUGOUT("Advertise 10mb Full duplex\n");
-		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
-	}
-
-	/* Do we want to advertise 100 Mb Half Duplex? */
-	if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
-		DEBUGOUT("Advertise 100mb Half duplex\n");
-		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
-	}
-
-	/* Do we want to advertise 100 Mb Full Duplex? */
-	if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
-		DEBUGOUT("Advertise 100mb Full duplex\n");
-		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
-	}
-
-	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
-	if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
-		DEBUGOUT
-		    ("Advertise 1000mb Half duplex requested, request denied!\n");
-	}
-
-	/* Do we want to advertise 1000 Mb Full Duplex? */
-	if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
-		DEBUGOUT("Advertise 1000mb Full duplex\n");
-		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
-	}
-
-	/* Check for a software override of the flow control settings, and
-	 * setup the PHY advertisement registers accordingly.  If
-	 * auto-negotiation is enabled, then software will have to set the
-	 * "PAUSE" bits to the correct value in the Auto-Negotiation
-	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
-	 *
-	 * The possible values of the "fc" parameter are:
-	 *      0:  Flow control is completely disabled
-	 *      1:  Rx flow control is enabled (we can receive pause frames
-	 *          but not send pause frames).
-	 *      2:  Tx flow control is enabled (we can send pause frames
-	 *          but we do not support receiving pause frames).
-	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
-	 *  other:  No software override.  The flow control configuration
-	 *          in the EEPROM is used.
-	 */
-	switch (hw->fc) {
-	case e1000_fc_none:	/* 0 */
-		/* Flow control (RX & TX) is completely disabled by a
-		 * software over-ride.
-		 */
-		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-		break;
-	case e1000_fc_rx_pause:	/* 1 */
-		/* RX Flow control is enabled, and TX Flow control is
-		 * disabled, by a software over-ride.
-		 */
-		/* Since there really isn't a way to advertise that we are
-		 * capable of RX Pause ONLY, we will advertise that we
-		 * support both symmetric and asymmetric RX PAUSE.  Later
-		 * (in e1000_config_fc_after_link_up) we will disable the
-		 *hw's ability to send PAUSE frames.
-		 */
-		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-		break;
-	case e1000_fc_tx_pause:	/* 2 */
-		/* TX Flow control is enabled, and RX Flow control is
-		 * disabled, by a software over-ride.
-		 */
-		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
-		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
-		break;
-	case e1000_fc_full:	/* 3 */
-		/* Flow control (both RX and TX) is enabled by a software
-		 * over-ride.
-		 */
-		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-		break;
-	default:
-		DEBUGOUT("Flow control param set incorrectly\n");
-		return -E1000_ERR_CONFIG;
-	}
-
-	if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
-		DEBUGOUT("PHY Write Error\n");
-		return -E1000_ERR_PHY;
-	}
-
-	DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
-
-	if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
-		DEBUGOUT("PHY Write Error\n");
-		return -E1000_ERR_PHY;
-	}
-	return 0;
-}
-
-/******************************************************************************
-* Sets the collision distance in the Transmit Control register
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Link should have been established previously. Reads the speed and duplex
-* information from the Device Status register.
-******************************************************************************/
-static void
-e1000_config_collision_dist(struct e1000_hw *hw)
-{
-	uint32_t tctl;
-
-	tctl = E1000_READ_REG(hw, TCTL);
-
-	tctl &= ~E1000_TCTL_COLD;
-	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
-
-	E1000_WRITE_REG(hw, TCTL, tctl);
-	E1000_WRITE_FLUSH(hw);
-}
-
-/******************************************************************************
-* Sets MAC speed and duplex settings to reflect the those in the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* mii_reg - data to write to the MII control register
-*
-* The contents of the PHY register containing the needed information need to
-* be passed in.
-******************************************************************************/
-static int
-e1000_config_mac_to_phy(struct e1000_hw *hw)
-{
-	uint32_t ctrl;
-	uint16_t phy_data;
-
-	DEBUGFUNC();
-
-	/* Read the Device Control Register and set the bits to Force Speed
-	 * and Duplex.
-	 */
-	ctrl = E1000_READ_REG(hw, CTRL);
-	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
-
-	/* Set up duplex in the Device Control and Transmit Control
-	 * registers depending on negotiated values.
-	 */
-	if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	if (phy_data & M88E1000_PSSR_DPLX)
-		ctrl |= E1000_CTRL_FD;
-	else
-		ctrl &= ~E1000_CTRL_FD;
-
-	e1000_config_collision_dist(hw);
-
-	/* Set up speed in the Device Control register depending on
-	 * negotiated values.
-	 */
-	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
-		ctrl |= E1000_CTRL_SPD_1000;
-	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
-		ctrl |= E1000_CTRL_SPD_100;
-	/* Write the configured values back to the Device Control Reg. */
-	E1000_WRITE_REG(hw, CTRL, ctrl);
-	return 0;
-}
-
-/******************************************************************************
- * Forces the MAC's flow control settings.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Sets the TFCE and RFCE bits in the device control register to reflect
- * the adapter settings. TFCE and RFCE need to be explicitly set by
- * software when a Copper PHY is used because autonegotiation is managed
- * by the PHY rather than the MAC. Software must also configure these
- * bits when link is forced on a fiber connection.
- *****************************************************************************/
-static int
-e1000_force_mac_fc(struct e1000_hw *hw)
-{
-	uint32_t ctrl;
-
-	DEBUGFUNC();
-
-	/* Get the current configuration of the Device Control Register */
-	ctrl = E1000_READ_REG(hw, CTRL);
-
-	/* Because we didn't get link via the internal auto-negotiation
-	 * mechanism (we either forced link or we got link via PHY
-	 * auto-neg), we have to manually enable/disable transmit an
-	 * receive flow control.
-	 *
-	 * The "Case" statement below enables/disable flow control
-	 * according to the "hw->fc" parameter.
-	 *
-	 * The possible values of the "fc" parameter are:
-	 *      0:  Flow control is completely disabled
-	 *      1:  Rx flow control is enabled (we can receive pause
-	 *          frames but not send pause frames).
-	 *      2:  Tx flow control is enabled (we can send pause frames
-	 *          frames but we do not receive pause frames).
-	 *      3:  Both Rx and TX flow control (symmetric) is enabled.
-	 *  other:  No other values should be possible at this point.
-	 */
-
-	switch (hw->fc) {
-	case e1000_fc_none:
-		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
-		break;
-	case e1000_fc_rx_pause:
-		ctrl &= (~E1000_CTRL_TFCE);
-		ctrl |= E1000_CTRL_RFCE;
-		break;
-	case e1000_fc_tx_pause:
-		ctrl &= (~E1000_CTRL_RFCE);
-		ctrl |= E1000_CTRL_TFCE;
-		break;
-	case e1000_fc_full:
-		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
-		break;
-	default:
-		DEBUGOUT("Flow control param set incorrectly\n");
-		return -E1000_ERR_CONFIG;
-	}
-
-	/* Disable TX Flow Control for 82542 (rev 2.0) */
-	if (hw->mac_type == e1000_82542_rev2_0)
-		ctrl &= (~E1000_CTRL_TFCE);
-
-	E1000_WRITE_REG(hw, CTRL, ctrl);
-	return 0;
-}
-
-/******************************************************************************
- * Configures flow control settings after link is established
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Should be called immediately after a valid link has been established.
- * Forces MAC flow control settings if link was forced. When in MII/GMII mode
- * and autonegotiation is enabled, the MAC flow control settings will be set
- * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
- * and RFCE bits will be automaticaly set to the negotiated flow control mode.
- *****************************************************************************/
-static int
-e1000_config_fc_after_link_up(struct e1000_hw *hw)
-{
-	int32_t ret_val;
-	uint16_t mii_status_reg;
-	uint16_t mii_nway_adv_reg;
-	uint16_t mii_nway_lp_ability_reg;
-	uint16_t speed;
-	uint16_t duplex;
-
-	DEBUGFUNC();
-
-	/* Check for the case where we have fiber media and auto-neg failed
-	 * so we had to force link.  In this case, we need to force the
-	 * configuration of the MAC to match the "fc" parameter.
-	 */
-	if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) {
-		ret_val = e1000_force_mac_fc(hw);
-		if (ret_val < 0) {
-			DEBUGOUT("Error forcing flow control settings\n");
-			return ret_val;
-		}
-	}
-
-	/* Check for the case where we have copper media and auto-neg is
-	 * enabled.  In this case, we need to check and see if Auto-Neg
-	 * has completed, and if so, how the PHY and link partner has
-	 * flow control configured.
-	 */
-	if (hw->media_type == e1000_media_type_copper) {
-		/* Read the MII Status Register and check to see if AutoNeg
-		 * has completed.  We read this twice because this reg has
-		 * some "sticky" (latched) bits.
-		 */
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
-			DEBUGOUT("PHY Read Error \n");
-			return -E1000_ERR_PHY;
-		}
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
-			DEBUGOUT("PHY Read Error \n");
-			return -E1000_ERR_PHY;
-		}
-
-		if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
-			/* The AutoNeg process has completed, so we now need to
-			 * read both the Auto Negotiation Advertisement Register
-			 * (Address 4) and the Auto_Negotiation Base Page Ability
-			 * Register (Address 5) to determine how flow control was
-			 * negotiated.
-			 */
-			if (e1000_read_phy_reg
-			    (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
-				DEBUGOUT("PHY Read Error\n");
-				return -E1000_ERR_PHY;
-			}
-			if (e1000_read_phy_reg
-			    (hw, PHY_LP_ABILITY,
-			     &mii_nway_lp_ability_reg) < 0) {
-				DEBUGOUT("PHY Read Error\n");
-				return -E1000_ERR_PHY;
-			}
-
-			/* Two bits in the Auto Negotiation Advertisement Register
-			 * (Address 4) and two bits in the Auto Negotiation Base
-			 * Page Ability Register (Address 5) determine flow control
-			 * for both the PHY and the link partner.  The following
-			 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
-			 * 1999, describes these PAUSE resolution bits and how flow
-			 * control is determined based upon these settings.
-			 * NOTE:  DC = Don't Care
-			 *
-			 *   LOCAL DEVICE  |   LINK PARTNER
-			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
-			 *-------|---------|-------|---------|--------------------
-			 *   0   |    0    |  DC   |   DC    | e1000_fc_none
-			 *   0   |    1    |   0   |   DC    | e1000_fc_none
-			 *   0   |    1    |   1   |    0    | e1000_fc_none
-			 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
-			 *   1   |    0    |   0   |   DC    | e1000_fc_none
-			 *   1   |   DC    |   1   |   DC    | e1000_fc_full
-			 *   1   |    1    |   0   |    0    | e1000_fc_none
-			 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
-			 *
-			 */
-			/* Are both PAUSE bits set to 1?  If so, this implies
-			 * Symmetric Flow Control is enabled at both ends.  The
-			 * ASM_DIR bits are irrelevant per the spec.
-			 *
-			 * For Symmetric Flow Control:
-			 *
-			 *   LOCAL DEVICE  |   LINK PARTNER
-			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-			 *-------|---------|-------|---------|--------------------
-			 *   1   |   DC    |   1   |   DC    | e1000_fc_full
-			 *
-			 */
-			if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-			    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
-				/* Now we need to check if the user selected RX ONLY
-				 * of pause frames.  In this case, we had to advertise
-				 * FULL flow control because we could not advertise RX
-				 * ONLY. Hence, we must now check to see if we need to
-				 * turn OFF  the TRANSMISSION of PAUSE frames.
-				 */
-				if (hw->original_fc == e1000_fc_full) {
-					hw->fc = e1000_fc_full;
-					DEBUGOUT("Flow Control = FULL.\r\n");
-				} else {
-					hw->fc = e1000_fc_rx_pause;
-					DEBUGOUT
-					    ("Flow Control = RX PAUSE frames only.\r\n");
-				}
-			}
-			/* For receiving PAUSE frames ONLY.
-			 *
-			 *   LOCAL DEVICE  |   LINK PARTNER
-			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-			 *-------|---------|-------|---------|--------------------
-			 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
-			 *
-			 */
-			else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-				 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-				 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-				 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
-			{
-				hw->fc = e1000_fc_tx_pause;
-				DEBUGOUT
-				    ("Flow Control = TX PAUSE frames only.\r\n");
-			}
-			/* For transmitting PAUSE frames ONLY.
-			 *
-			 *   LOCAL DEVICE  |   LINK PARTNER
-			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-			 *-------|---------|-------|---------|--------------------
-			 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
-			 *
-			 */
-			else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-				 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-				 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-				 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
-			{
-				hw->fc = e1000_fc_rx_pause;
-				DEBUGOUT
-				    ("Flow Control = RX PAUSE frames only.\r\n");
-			}
-			/* Per the IEEE spec, at this point flow control should be
-			 * disabled.  However, we want to consider that we could
-			 * be connected to a legacy switch that doesn't advertise
-			 * desired flow control, but can be forced on the link
-			 * partner.  So if we advertised no flow control, that is
-			 * what we will resolve to.  If we advertised some kind of
-			 * receive capability (Rx Pause Only or Full Flow Control)
-			 * and the link partner advertised none, we will configure
-			 * ourselves to enable Rx Flow Control only.  We can do
-			 * this safely for two reasons:  If the link partner really
-			 * didn't want flow control enabled, and we enable Rx, no
-			 * harm done since we won't be receiving any PAUSE frames
-			 * anyway.  If the intent on the link partner was to have
-			 * flow control enabled, then by us enabling RX only, we
-			 * can at least receive pause frames and process them.
-			 * This is a good idea because in most cases, since we are
-			 * predominantly a server NIC, more times than not we will
-			 * be asked to delay transmission of packets than asking
-			 * our link partner to pause transmission of frames.
-			 */
-			else if (hw->original_fc == e1000_fc_none ||
-				 hw->original_fc == e1000_fc_tx_pause) {
-				hw->fc = e1000_fc_none;
-				DEBUGOUT("Flow Control = NONE.\r\n");
-			} else {
-				hw->fc = e1000_fc_rx_pause;
-				DEBUGOUT
-				    ("Flow Control = RX PAUSE frames only.\r\n");
-			}
-
-			/* Now we need to do one last check...  If we auto-
-			 * negotiated to HALF DUPLEX, flow control should not be
-			 * enabled per IEEE 802.3 spec.
-			 */
-			e1000_get_speed_and_duplex(hw, &speed, &duplex);
-
-			if (duplex == HALF_DUPLEX)
-				hw->fc = e1000_fc_none;
-
-			/* Now we call a subroutine to actually force the MAC
-			 * controller to use the correct flow control settings.
-			 */
-			ret_val = e1000_force_mac_fc(hw);
-			if (ret_val < 0) {
-				DEBUGOUT
-				    ("Error forcing flow control settings\n");
-				return ret_val;
-			}
-		} else {
-			DEBUGOUT
-			    ("Copper PHY and Auto Neg has not completed.\r\n");
-		}
-	}
-	return 0;
-}
-
-/******************************************************************************
- * Checks to see if the link status of the hardware has changed.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Called by any function that needs to check the link status of the adapter.
- *****************************************************************************/
-static int
-e1000_check_for_link(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	uint32_t rxcw;
-	uint32_t ctrl;
-	uint32_t status;
-	uint32_t rctl;
-	uint32_t signal;
-	int32_t ret_val;
-	uint16_t phy_data;
-	uint16_t lp_capability;
-
-	DEBUGFUNC();
-
-	/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
-	 * set when the optics detect a signal. On older adapters, it will be
-	 * cleared when there is a signal
-	 */
-	ctrl = E1000_READ_REG(hw, CTRL);
-	if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
-		signal = E1000_CTRL_SWDPIN1;
-	else
-		signal = 0;
-
-	status = E1000_READ_REG(hw, STATUS);
-	rxcw = E1000_READ_REG(hw, RXCW);
-	DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
-
-	/* If we have a copper PHY then we only want to go out to the PHY
-	 * registers to see if Auto-Neg has completed and/or if our link
-	 * status has changed.  The get_link_status flag will be set if we
-	 * receive a Link Status Change interrupt or we have Rx Sequence
-	 * Errors.
-	 */
-	if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
-		/* First we want to see if the MII Status Register reports
-		 * link.  If so, then we want to get the current speed/duplex
-		 * of the PHY.
-		 * Read the register twice since the link bit is sticky.
-		 */
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
-			DEBUGOUT("PHY Read Error\n");
-			return -E1000_ERR_PHY;
-		}
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
-			DEBUGOUT("PHY Read Error\n");
-			return -E1000_ERR_PHY;
-		}
-
-		if (phy_data & MII_SR_LINK_STATUS) {
-			hw->get_link_status = FALSE;
-		} else {
-			/* No link detected */
-			return -E1000_ERR_NOLINK;
-		}
-
-		/* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
-		 * have Si on board that is 82544 or newer, Auto
-		 * Speed Detection takes care of MAC speed/duplex
-		 * configuration.  So we only need to configure Collision
-		 * Distance in the MAC.  Otherwise, we need to force
-		 * speed/duplex on the MAC to the current PHY speed/duplex
-		 * settings.
-		 */
-		if (hw->mac_type >= e1000_82544)
-			e1000_config_collision_dist(hw);
-		else {
-			ret_val = e1000_config_mac_to_phy(hw);
-			if (ret_val < 0) {
-				DEBUGOUT
-				    ("Error configuring MAC to PHY settings\n");
-				return ret_val;
-			}
-		}
-
-		/* Configure Flow Control now that Auto-Neg has completed. First, we
-		 * need to restore the desired flow control settings because we may
-		 * have had to re-autoneg with a different link partner.
-		 */
-		ret_val = e1000_config_fc_after_link_up(hw);
-		if (ret_val < 0) {
-			DEBUGOUT("Error configuring flow control\n");
-			return ret_val;
-		}
-
-		/* At this point we know that we are on copper and we have
-		 * auto-negotiated link.  These are conditions for checking the link
-		 * parter capability register.  We use the link partner capability to
-		 * determine if TBI Compatibility needs to be turned on or off.  If
-		 * the link partner advertises any speed in addition to Gigabit, then
-		 * we assume that they are GMII-based, and TBI compatibility is not
-		 * needed. If no other speeds are advertised, we assume the link
-		 * partner is TBI-based, and we turn on TBI Compatibility.
-		 */
-		if (hw->tbi_compatibility_en) {
-			if (e1000_read_phy_reg
-			    (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
-				DEBUGOUT("PHY Read Error\n");
-				return -E1000_ERR_PHY;
-			}
-			if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
-					     NWAY_LPAR_10T_FD_CAPS |
-					     NWAY_LPAR_100TX_HD_CAPS |
-					     NWAY_LPAR_100TX_FD_CAPS |
-					     NWAY_LPAR_100T4_CAPS)) {
-				/* If our link partner advertises anything in addition to
-				 * gigabit, we do not need to enable TBI compatibility.
-				 */
-				if (hw->tbi_compatibility_on) {
-					/* If we previously were in the mode, turn it off. */
-					rctl = E1000_READ_REG(hw, RCTL);
-					rctl &= ~E1000_RCTL_SBP;
-					E1000_WRITE_REG(hw, RCTL, rctl);
-					hw->tbi_compatibility_on = FALSE;
-				}
-			} else {
-				/* If TBI compatibility is was previously off, turn it on. For
-				 * compatibility with a TBI link partner, we will store bad
-				 * packets. Some frames have an additional byte on the end and
-				 * will look like CRC errors to to the hardware.
-				 */
-				if (!hw->tbi_compatibility_on) {
-					hw->tbi_compatibility_on = TRUE;
-					rctl = E1000_READ_REG(hw, RCTL);
-					rctl |= E1000_RCTL_SBP;
-					E1000_WRITE_REG(hw, RCTL, rctl);
-				}
-			}
-		}
-	}
-	/* If we don't have link (auto-negotiation failed or link partner cannot
-	 * auto-negotiate), the cable is plugged in (we have signal), and our
-	 * link partner is not trying to auto-negotiate with us (we are receiving
-	 * idles or data), we need to force link up. We also need to give
-	 * auto-negotiation time to complete, in case the cable was just plugged
-	 * in. The autoneg_failed flag does this.
-	 */
-	else if ((hw->media_type == e1000_media_type_fiber) &&
-		 (!(status & E1000_STATUS_LU)) &&
-		 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
-		 (!(rxcw & E1000_RXCW_C))) {
-		if (hw->autoneg_failed == 0) {
-			hw->autoneg_failed = 1;
-			return 0;
-		}
-		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
-
-		/* Disable auto-negotiation in the TXCW register */
-		E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
-
-		/* Force link-up and also force full-duplex. */
-		ctrl = E1000_READ_REG(hw, CTRL);
-		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
-		E1000_WRITE_REG(hw, CTRL, ctrl);
-
-		/* Configure Flow Control after forcing link up. */
-		ret_val = e1000_config_fc_after_link_up(hw);
-		if (ret_val < 0) {
-			DEBUGOUT("Error configuring flow control\n");
-			return ret_val;
-		}
-	}
-	/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
-	 * auto-negotiation in the TXCW register and disable forced link in the
-	 * Device Control register in an attempt to auto-negotiate with our link
-	 * partner.
-	 */
-	else if ((hw->media_type == e1000_media_type_fiber) &&
-		 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
-		DEBUGOUT
-		    ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
-		E1000_WRITE_REG(hw, TXCW, hw->txcw);
-		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
-	}
-	return 0;
-}
-
-/******************************************************************************
- * Detects the current speed and duplex settings of the hardware.
- *
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- *****************************************************************************/
-static void
-e1000_get_speed_and_duplex(struct e1000_hw *hw,
-			   uint16_t * speed, uint16_t * duplex)
-{
-	uint32_t status;
-
-	DEBUGFUNC();
-
-	if (hw->mac_type >= e1000_82543) {
-		status = E1000_READ_REG(hw, STATUS);
-		if (status & E1000_STATUS_SPEED_1000) {
-			*speed = SPEED_1000;
-			DEBUGOUT("1000 Mbs, ");
-		} else if (status & E1000_STATUS_SPEED_100) {
-			*speed = SPEED_100;
-			DEBUGOUT("100 Mbs, ");
-		} else {
-			*speed = SPEED_10;
-			DEBUGOUT("10 Mbs, ");
-		}
-
-		if (status & E1000_STATUS_FD) {
-			*duplex = FULL_DUPLEX;
-			DEBUGOUT("Full Duplex\r\n");
-		} else {
-			*duplex = HALF_DUPLEX;
-			DEBUGOUT(" Half Duplex\r\n");
-		}
-	} else {
-		DEBUGOUT("1000 Mbs, Full Duplex\r\n");
-		*speed = SPEED_1000;
-		*duplex = FULL_DUPLEX;
-	}
-}
-
-/******************************************************************************
-* Blocks until autoneg completes or times out (~4.5 seconds)
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_wait_autoneg(struct e1000_hw *hw)
-{
-	uint16_t i;
-	uint16_t phy_data;
-
-	DEBUGFUNC();
-	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
-
-	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
-	for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
-		/* Read the MII Status Register and wait for Auto-Neg
-		 * Complete bit to be set.
-		 */
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
-			DEBUGOUT("PHY Read Error\n");
-			return -E1000_ERR_PHY;
-		}
-		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
-			DEBUGOUT("PHY Read Error\n");
-			return -E1000_ERR_PHY;
-		}
-		if (phy_data & MII_SR_AUTONEG_COMPLETE) {
-			DEBUGOUT("Auto-Neg complete.\n");
-			return 0;
-		}
-		mdelay(100);
-	}
-	DEBUGOUT("Auto-Neg timedout.\n");
-	return -E1000_ERR_TIMEOUT;
-}
-
-/******************************************************************************
-* Raises the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
-static void
-e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
-{
-	/* Raise the clock input to the Management Data Clock (by setting the MDC
-	 * bit), and then delay 2 microseconds.
-	 */
-	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
-	E1000_WRITE_FLUSH(hw);
-	udelay(2);
-}
-
-/******************************************************************************
-* Lowers the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
-static void
-e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
-{
-	/* Lower the clock input to the Management Data Clock (by clearing the MDC
-	 * bit), and then delay 2 microseconds.
-	 */
-	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
-	E1000_WRITE_FLUSH(hw);
-	udelay(2);
-}
-
-/******************************************************************************
-* Shifts data bits out to the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* data - Data to send out to the PHY
-* count - Number of bits to shift out
-*
-* Bits are shifted out in MSB to LSB order.
-******************************************************************************/
-static void
-e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
-{
-	uint32_t ctrl;
-	uint32_t mask;
-
-	/* We need to shift "count" number of bits out to the PHY. So, the value
-	 * in the "data" parameter will be shifted out to the PHY one bit at a
-	 * time. In order to do this, "data" must be broken down into bits.
-	 */
-	mask = 0x01;
-	mask <<= (count - 1);
-
-	ctrl = E1000_READ_REG(hw, CTRL);
-
-	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
-	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
-
-	while (mask) {
-		/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
-		 * then raising and lowering the Management Data Clock. A "0" is
-		 * shifted out to the PHY by setting the MDIO bit to "0" and then
-		 * raising and lowering the clock.
-		 */
-		if (data & mask)
-			ctrl |= E1000_CTRL_MDIO;
-		else
-			ctrl &= ~E1000_CTRL_MDIO;
-
-		E1000_WRITE_REG(hw, CTRL, ctrl);
-		E1000_WRITE_FLUSH(hw);
-
-		udelay(2);
-
-		e1000_raise_mdi_clk(hw, &ctrl);
-		e1000_lower_mdi_clk(hw, &ctrl);
-
-		mask = mask >> 1;
-	}
-}
-
-/******************************************************************************
-* Shifts data bits in from the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Bits are shifted in in MSB to LSB order.
-******************************************************************************/
-static uint16_t
-e1000_shift_in_mdi_bits(struct e1000_hw *hw)
-{
-	uint32_t ctrl;
-	uint16_t data = 0;
-	uint8_t i;
-
-	/* In order to read a register from the PHY, we need to shift in a total
-	 * of 18 bits from the PHY. The first two bit (turnaround) times are used
-	 * to avoid contention on the MDIO pin when a read operation is performed.
-	 * These two bits are ignored by us and thrown away. Bits are "shifted in"
-	 * by raising the input to the Management Data Clock (setting the MDC bit),
-	 * and then reading the value of the MDIO bit.
-	 */
-	ctrl = E1000_READ_REG(hw, CTRL);
-
-	/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
-	ctrl &= ~E1000_CTRL_MDIO_DIR;
-	ctrl &= ~E1000_CTRL_MDIO;
-
-	E1000_WRITE_REG(hw, CTRL, ctrl);
-	E1000_WRITE_FLUSH(hw);
-
-	/* Raise and Lower the clock before reading in the data. This accounts for
-	 * the turnaround bits. The first clock occurred when we clocked out the
-	 * last bit of the Register Address.
-	 */
-	e1000_raise_mdi_clk(hw, &ctrl);
-	e1000_lower_mdi_clk(hw, &ctrl);
-
-	for (data = 0, i = 0; i < 16; i++) {
-		data = data << 1;
-		e1000_raise_mdi_clk(hw, &ctrl);
-		ctrl = E1000_READ_REG(hw, CTRL);
-		/* Check to see if we shifted in a "1". */
-		if (ctrl & E1000_CTRL_MDIO)
-			data |= 1;
-		e1000_lower_mdi_clk(hw, &ctrl);
-	}
-
-	e1000_raise_mdi_clk(hw, &ctrl);
-	e1000_lower_mdi_clk(hw, &ctrl);
-
-	return data;
-}
-
-/*****************************************************************************
-* Reads the value from a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to read
-******************************************************************************/
-static int
-e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
-{
-	uint32_t i;
-	uint32_t mdic = 0;
-	const uint32_t phy_addr = 1;
-
-	if (reg_addr > MAX_PHY_REG_ADDRESS) {
-		DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
-		return -E1000_ERR_PARAM;
-	}
-
-	if (hw->mac_type > e1000_82543) {
-		/* Set up Op-code, Phy Address, and register address in the MDI
-		 * Control register.  The MAC will take care of interfacing with the
-		 * PHY to retrieve the desired data.
-		 */
-		mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-			(phy_addr << E1000_MDIC_PHY_SHIFT) |
-			(E1000_MDIC_OP_READ));
-
-		E1000_WRITE_REG(hw, MDIC, mdic);
-
-		/* Poll the ready bit to see if the MDI read completed */
-		for (i = 0; i < 64; i++) {
-			udelay(10);
-			mdic = E1000_READ_REG(hw, MDIC);
-			if (mdic & E1000_MDIC_READY)
-				break;
-		}
-		if (!(mdic & E1000_MDIC_READY)) {
-			DEBUGOUT("MDI Read did not complete\n");
-			return -E1000_ERR_PHY;
-		}
-		if (mdic & E1000_MDIC_ERROR) {
-			DEBUGOUT("MDI Error\n");
-			return -E1000_ERR_PHY;
-		}
-		*phy_data = (uint16_t) mdic;
-	} else {
-		/* We must first send a preamble through the MDIO pin to signal the
-		 * beginning of an MII instruction.  This is done by sending 32
-		 * consecutive "1" bits.
-		 */
-		e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
-		/* Now combine the next few fields that are required for a read
-		 * operation.  We use this method instead of calling the
-		 * e1000_shift_out_mdi_bits routine five different times. The format of
-		 * a MII read instruction consists of a shift out of 14 bits and is
-		 * defined as follows:
-		 *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
-		 * followed by a shift in of 18 bits.  This first two bits shifted in
-		 * are TurnAround bits used to avoid contention on the MDIO pin when a
-		 * READ operation is performed.  These two bits are thrown away
-		 * followed by a shift in of 16 bits which contains the desired data.
-		 */
-		mdic = ((reg_addr) | (phy_addr << 5) |
-			(PHY_OP_READ << 10) | (PHY_SOF << 12));
-
-		e1000_shift_out_mdi_bits(hw, mdic, 14);
-
-		/* Now that we've shifted out the read command to the MII, we need to
-		 * "shift in" the 16-bit value (18 total bits) of the requested PHY
-		 * register address.
-		 */
-		*phy_data = e1000_shift_in_mdi_bits(hw);
-	}
-	return 0;
-}
-
-/******************************************************************************
-* Writes a value to a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to write
-* data - data to write to the PHY
-******************************************************************************/
-static int
-e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
-{
-	uint32_t i;
-	uint32_t mdic = 0;
-	const uint32_t phy_addr = 1;
-
-	if (reg_addr > MAX_PHY_REG_ADDRESS) {
-		DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
-		return -E1000_ERR_PARAM;
-	}
-
-	if (hw->mac_type > e1000_82543) {
-		/* Set up Op-code, Phy Address, register address, and data intended
-		 * for the PHY register in the MDI Control register.  The MAC will take
-		 * care of interfacing with the PHY to send the desired data.
-		 */
-		mdic = (((uint32_t) phy_data) |
-			(reg_addr << E1000_MDIC_REG_SHIFT) |
-			(phy_addr << E1000_MDIC_PHY_SHIFT) |
-			(E1000_MDIC_OP_WRITE));
-
-		E1000_WRITE_REG(hw, MDIC, mdic);
-
-		/* Poll the ready bit to see if the MDI read completed */
-		for (i = 0; i < 64; i++) {
-			udelay(10);
-			mdic = E1000_READ_REG(hw, MDIC);
-			if (mdic & E1000_MDIC_READY)
-				break;
-		}
-		if (!(mdic & E1000_MDIC_READY)) {
-			DEBUGOUT("MDI Write did not complete\n");
-			return -E1000_ERR_PHY;
-		}
-	} else {
-		/* We'll need to use the SW defined pins to shift the write command
-		 * out to the PHY. We first send a preamble to the PHY to signal the
-		 * beginning of the MII instruction.  This is done by sending 32
-		 * consecutive "1" bits.
-		 */
-		e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
-		/* Now combine the remaining required fields that will indicate a
-		 * write operation. We use this method instead of calling the
-		 * e1000_shift_out_mdi_bits routine for each field in the command. The
-		 * format of a MII write instruction is as follows:
-		 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
-		 */
-		mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
-			(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
-		mdic <<= 16;
-		mdic |= (uint32_t) phy_data;
-
-		e1000_shift_out_mdi_bits(hw, mdic, 32);
-	}
-	return 0;
-}
-
-/******************************************************************************
-* Returns the PHY to the power-on reset state
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static void
-e1000_phy_hw_reset(struct e1000_hw *hw)
-{
-	uint32_t ctrl;
-	uint32_t ctrl_ext;
-
-	DEBUGFUNC();
-
-	DEBUGOUT("Resetting Phy...\n");
-
-	if (hw->mac_type > e1000_82543) {
-		/* Read the device control register and assert the E1000_CTRL_PHY_RST
-		 * bit. Then, take it out of reset.
-		 */
-		ctrl = E1000_READ_REG(hw, CTRL);
-		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
-		E1000_WRITE_FLUSH(hw);
-		mdelay(10);
-		E1000_WRITE_REG(hw, CTRL, ctrl);
-		E1000_WRITE_FLUSH(hw);
-	} else {
-		/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
-		 * bit to put the PHY into reset. Then, take it out of reset.
-		 */
-		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
-		ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
-		ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
-		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-		E1000_WRITE_FLUSH(hw);
-		mdelay(10);
-		ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
-		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-		E1000_WRITE_FLUSH(hw);
-	}
-	udelay(150);
-}
-
-/******************************************************************************
-* Resets the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Sets bit 15 of the MII Control regiser
-******************************************************************************/
-static int
-e1000_phy_reset(struct e1000_hw *hw)
-{
-	uint16_t phy_data;
-
-	DEBUGFUNC();
-
-	if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	phy_data |= MII_CR_RESET;
-	if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
-		DEBUGOUT("PHY Write Error\n");
-		return -E1000_ERR_PHY;
-	}
-	udelay(1);
-	return 0;
-}
-
-/******************************************************************************
-* Probes the expected PHY address for known PHY IDs
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_detect_gig_phy(struct e1000_hw *hw)
-{
-	uint16_t phy_id_high, phy_id_low;
-	int match = FALSE;
-
-	DEBUGFUNC();
-
-	/* Read the PHY ID Registers to identify which PHY is onboard. */
-	if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	hw->phy_id = (uint32_t) (phy_id_high << 16);
-	udelay(2);
-	if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
-		DEBUGOUT("PHY Read Error\n");
-		return -E1000_ERR_PHY;
-	}
-	hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
-
-	switch (hw->mac_type) {
-	case e1000_82543:
-		if (hw->phy_id == M88E1000_E_PHY_ID)
-			match = TRUE;
-		break;
-	case e1000_82544:
-		if (hw->phy_id == M88E1000_I_PHY_ID)
-			match = TRUE;
-		break;
-	case e1000_82540:
-	case e1000_82545:
-	case e1000_82546:
-		if (hw->phy_id == M88E1011_I_PHY_ID)
-			match = TRUE;
-		break;
-	default:
-		DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
-		return -E1000_ERR_CONFIG;
-	}
-	if (match) {
-		DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
-		return 0;
-	}
-	DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
-	return -E1000_ERR_PHY;
-}
-
-/**
- * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
- *
- * e1000_sw_init initializes the Adapter private data structure.
- * Fields are initialized based on PCI device information and
- * OS network device settings (MTU size).
- **/
-
-static int
-e1000_sw_init(struct eth_device *nic, int cardnum)
-{
-	struct e1000_hw *hw = (typeof(hw)) nic->priv;
-	int result;
-
-	/* PCI config space info */
-	pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
-	pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
-	pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
-			     &hw->subsystem_vendor_id);
-	pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
-
-	pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
-	pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
-
-	/* identify the MAC */
-	result = e1000_set_mac_type(hw);
-	if (result) {
-		E1000_ERR("Unknown MAC Type\n");
-		return result;
-	}
-
-	/* lan a vs. lan b settings */
-	if (hw->mac_type == e1000_82546)
-		/*this also works w/ multiple 82546 cards */
-		/*but not if they're intermingled /w other e1000s */
-		hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
-	else
-		hw->lan_loc = e1000_lan_a;
-
-	/* flow control settings */
-	hw->fc_high_water = E1000_FC_HIGH_THRESH;
-	hw->fc_low_water = E1000_FC_LOW_THRESH;
-	hw->fc_pause_time = E1000_FC_PAUSE_TIME;
-	hw->fc_send_xon = 1;
-
-	/* Media type - copper or fiber */
-
-	if (hw->mac_type >= e1000_82543) {
-		uint32_t status = E1000_READ_REG(hw, STATUS);
-
-		if (status & E1000_STATUS_TBIMODE) {
-			DEBUGOUT("fiber interface\n");
-			hw->media_type = e1000_media_type_fiber;
-		} else {
-			DEBUGOUT("copper interface\n");
-			hw->media_type = e1000_media_type_copper;
-		}
-	} else {
-		hw->media_type = e1000_media_type_fiber;
-	}
-
-	if (hw->mac_type < e1000_82543)
-		hw->report_tx_early = 0;
-	else
-		hw->report_tx_early = 1;
-
-	hw->tbi_compatibility_en = TRUE;
-	return E1000_SUCCESS;
-}
-
-void
-fill_rx(struct e1000_hw *hw)
-{
-	struct e1000_rx_desc *rd;
-
-	rx_last = rx_tail;
-	rd = rx_base + rx_tail;
-	rx_tail = (rx_tail + 1) % 8;
-	memset(rd, 0, 16);
-	rd->buffer_addr = cpu_to_le64((u32) & packet);
-	E1000_WRITE_REG(hw, RDT, rx_tail);
-}
-
-/**
- * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
- * @adapter: board private structure
- *
- * Configure the Tx unit of the MAC after a reset.
- **/
-
-static void
-e1000_configure_tx(struct e1000_hw *hw)
-{
-	unsigned long ptr;
-	unsigned long tctl;
-	unsigned long tipg;
-
-	ptr = (u32) tx_pool;
-	if (ptr & 0xf)
-		ptr = (ptr + 0x10) & (~0xf);
-
-	tx_base = (typeof(tx_base)) ptr;
-
-	E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
-	E1000_WRITE_REG(hw, TDBAH, 0);
-
-	E1000_WRITE_REG(hw, TDLEN, 128);
-
-	/* Setup the HW Tx Head and Tail descriptor pointers */
-	E1000_WRITE_REG(hw, TDH, 0);
-	E1000_WRITE_REG(hw, TDT, 0);
-	tx_tail = 0;
-
-	/* Set the default values for the Tx Inter Packet Gap timer */
-	switch (hw->mac_type) {
-	case e1000_82542_rev2_0:
-	case e1000_82542_rev2_1:
-		tipg = DEFAULT_82542_TIPG_IPGT;
-		tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
-		tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
-		break;
-	default:
-		if (hw->media_type == e1000_media_type_fiber)
-			tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
-		else
-			tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
-		tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
-		tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
-	}
-	E1000_WRITE_REG(hw, TIPG, tipg);
-	/* Program the Transmit Control Register */
-	tctl = E1000_READ_REG(hw, TCTL);
-	tctl &= ~E1000_TCTL_CT;
-	tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
-	    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
-	E1000_WRITE_REG(hw, TCTL, tctl);
-
-	e1000_config_collision_dist(hw);
-}
-
-/**
- * e1000_setup_rctl - configure the receive control register
- * @adapter: Board private structure
- **/
-static void
-e1000_setup_rctl(struct e1000_hw *hw)
-{
-	uint32_t rctl;
-
-	rctl = E1000_READ_REG(hw, RCTL);
-
-	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
-
-	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF;	/* |
-												   (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
-
-	if (hw->tbi_compatibility_on == 1)
-		rctl |= E1000_RCTL_SBP;
-	else
-		rctl &= ~E1000_RCTL_SBP;
-
-	rctl &= ~(E1000_RCTL_SZ_4096);
-		rctl |= E1000_RCTL_SZ_2048;
-		rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
-	E1000_WRITE_REG(hw, RCTL, rctl);
-}
-
-/**
- * e1000_configure_rx - Configure 8254x Receive Unit after Reset
- * @adapter: board private structure
- *
- * Configure the Rx unit of the MAC after a reset.
- **/
-static void
-e1000_configure_rx(struct e1000_hw *hw)
-{
-	unsigned long ptr;
-	unsigned long rctl;
-	rx_tail = 0;
-	/* make sure receives are disabled while setting up the descriptors */
-	rctl = E1000_READ_REG(hw, RCTL);
-	E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
-	if (hw->mac_type >= e1000_82540) {
-		/* Set the interrupt throttling rate.  Value is calculated
-		 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
-#define MAX_INTS_PER_SEC        8000
-#define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
-		E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
-	}
-
-	/* Setup the Base and Length of the Rx Descriptor Ring */
-	ptr = (u32) rx_pool;
-	if (ptr & 0xf)
-		ptr = (ptr + 0x10) & (~0xf);
-	rx_base = (typeof(rx_base)) ptr;
-	E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
-	E1000_WRITE_REG(hw, RDBAH, 0);
-
-	E1000_WRITE_REG(hw, RDLEN, 128);
-
-	/* Setup the HW Rx Head and Tail Descriptor Pointers */
-	E1000_WRITE_REG(hw, RDH, 0);
-	E1000_WRITE_REG(hw, RDT, 0);
-	/* Enable Receives */
-
-	E1000_WRITE_REG(hw, RCTL, rctl);
-	fill_rx(hw);
-}
-
-/**************************************************************************
-POLL - Wait for a frame
-***************************************************************************/
-static int
-e1000_poll(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-	struct e1000_rx_desc *rd;
-	/* return true if there's an ethernet packet ready to read */
-	rd = rx_base + rx_last;
-	if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
-		return 0;
-	/*DEBUGOUT("recv: packet len=%d \n", rd->length); */
-	NetReceive((uchar *)packet, le32_to_cpu(rd->length));
-	fill_rx(hw);
-	return 1;
-}
-
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-static int
-e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
-{
-	struct e1000_hw *hw = nic->priv;
-	struct e1000_tx_desc *txp;
-	int i = 0;
-
-	txp = tx_base + tx_tail;
-	tx_tail = (tx_tail + 1) % 8;
-
-	txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
-	txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
-				      E1000_TXD_CMD_IFCS | length);
-	txp->upper.data = 0;
-	E1000_WRITE_REG(hw, TDT, tx_tail);
-
-	while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
-		if (i++ > TOUT_LOOP) {
-			DEBUGOUT("e1000: tx timeout\n");
-			return 0;
-		}
-		udelay(10);	/* give the nic a chance to write to the register */
-	}
-	return 1;
-}
-
-/*reset function*/
-static inline int
-e1000_reset(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-
-	e1000_reset_hw(hw);
-	if (hw->mac_type >= e1000_82544) {
-		E1000_WRITE_REG(hw, WUC, 0);
-	}
-	return e1000_init_hw(nic);
-}
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-static void
-e1000_disable(struct eth_device *nic)
-{
-	struct e1000_hw *hw = nic->priv;
-
-	/* Turn off the ethernet interface */
-	E1000_WRITE_REG(hw, RCTL, 0);
-	E1000_WRITE_REG(hw, TCTL, 0);
-
-	/* Clear the transmit ring */
-	E1000_WRITE_REG(hw, TDH, 0);
-	E1000_WRITE_REG(hw, TDT, 0);
-
-	/* Clear the receive ring */
-	E1000_WRITE_REG(hw, RDH, 0);
-	E1000_WRITE_REG(hw, RDT, 0);
-
-	/* put the card in its initial state */
-	mdelay(10);
-
-}
-
-/**************************************************************************
-INIT - set up ethernet interface(s)
-***************************************************************************/
-static int
-e1000_init(struct eth_device *nic, bd_t * bis)
-{
-	struct e1000_hw *hw = nic->priv;
-	int ret_val = 0;
-
-	ret_val = e1000_reset(nic);
-	if (ret_val < 0) {
-		if ((ret_val == -E1000_ERR_NOLINK) ||
-		    (ret_val == -E1000_ERR_TIMEOUT)) {
-			E1000_ERR("Valid Link not detected\n");
-		} else {
-			E1000_ERR("Hardware Initialization Failed\n");
-		}
-		return 0;
-	}
-	e1000_configure_tx(hw);
-	e1000_setup_rctl(hw);
-	e1000_configure_rx(hw);
-	return 1;
-}
-
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-You should omit the last argument struct pci_device * for a non-PCI NIC
-***************************************************************************/
-int
-e1000_initialize(bd_t * bis)
-{
-	pci_dev_t devno;
-	int card_number = 0;
-	struct eth_device *nic = NULL;
-	struct e1000_hw *hw = NULL;
-	u32 iobase;
-	int idx = 0;
-	u32 PciCommandWord;
-
-	while (1) {		/* Find PCI device(s) */
-		if ((devno = pci_find_devices(supported, idx++)) < 0) {
-			break;
-		}
-
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
-		iobase &= ~0xf;	/* Mask the bits that say "this is an io addr" */
-		DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
-
-		pci_write_config_dword(devno, PCI_COMMAND,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-		/* Check if I/O accesses and Bus Mastering are enabled. */
-		pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
-		if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
-			printf("Error: Can not enable MEM access.\n");
-			continue;
-		} else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
-			printf("Error: Can not enable Bus Mastering.\n");
-			continue;
-		}
-
-		nic = (struct eth_device *) malloc(sizeof (*nic));
-		hw = (struct e1000_hw *) malloc(sizeof (*hw));
-		hw->pdev = devno;
-		nic->priv = hw;
-		nic->iobase = bus_to_phys(devno, iobase);
-
-		sprintf(nic->name, "e1000#%d", card_number);
-
-		/* Are these variables needed? */
-		hw->fc = e1000_fc_default;
-		hw->original_fc = e1000_fc_default;
-		hw->autoneg_failed = 0;
-		hw->get_link_status = TRUE;
-		hw->hw_addr = (typeof(hw->hw_addr)) iobase;
-		hw->mac_type = e1000_undefined;
-
-		/* MAC and Phy settings */
-		if (e1000_sw_init(nic, card_number) < 0) {
-			free(hw);
-			free(nic);
-			return 0;
-		}
-#ifndef CONFIG_AP1000
-		if (e1000_validate_eeprom_checksum(nic) < 0) {
-			printf("The EEPROM Checksum Is Not Valid\n");
-			free(hw);
-			free(nic);
-			return 0;
-		}
-#endif
-		e1000_read_mac_addr(nic);
-
-		E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
-
-		printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
-		       nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
-		       nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
-
-		nic->init = e1000_init;
-		nic->recv = e1000_poll;
-		nic->send = e1000_transmit;
-		nic->halt = e1000_disable;
-
-		eth_register(nic);
-
-		card_number++;
-	}
-	return 1;
-}
-
-#endif
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
deleted file mode 100644
index 274c8d7476..0000000000
--- a/drivers/net/e1000.h
+++ /dev/null
@@ -1,1718 +0,0 @@
-/*******************************************************************************
-
-
-  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
-
-  This program is free software; you can redistribute it and/or modify it
-  under the terms of the GNU General Public License as published by the Free
-  Software Foundation; either version 2 of the License, or (at your option)
-  any later version.
-
-  This program is distributed in the hope that it will be useful, but WITHOUT
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-  more details.
-
-  You should have received a copy of the GNU General Public License along with
-  this program; if not, write to the Free Software Foundation, Inc., 59
-  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-
-  The full GNU General Public License is included in this distribution in the
-  file called LICENSE.
-
-  Contact Information:
-  Linux NICS <linux.nics@intel.com>
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-/* e1000_hw.h
- * Structures, enums, and macros for the MAC
- */
-
-#ifndef _E1000_HW_H_
-#define _E1000_HW_H_
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#define E1000_ERR(args...) printf("e1000: " args)
-
-#ifdef E1000_DEBUG
-#define E1000_DBG(args...)	printf("e1000: " args)
-#define DEBUGOUT(fmt,args...) printf(fmt ,##args)
-#define DEBUGFUNC()        printf("%s\n", __FUNCTION__);
-#else
-#define E1000_DBG(args...)
-#define DEBUGFUNC()
-#define DEBUGOUT(fmt,args...)
-#endif
-
-/* Forward declarations of structures used by the shared code */
-struct e1000_hw;
-struct e1000_hw_stats;
-
-typedef enum {
-	FALSE = 0,
-	TRUE = 1
-} boolean_t;
-
-/* Enumerated types specific to the e1000 hardware */
-/* Media Access Controlers */
-typedef enum {
-	e1000_undefined = 0,
-	e1000_82542_rev2_0,
-	e1000_82542_rev2_1,
-	e1000_82543,
-	e1000_82544,
-	e1000_82540,
-	e1000_82545,
-	e1000_82546,
-	e1000_num_macs
-} e1000_mac_type;
-
-/* Media Types */
-typedef enum {
-	e1000_media_type_copper = 0,
-	e1000_media_type_fiber = 1,
-	e1000_num_media_types
-} e1000_media_type;
-
-typedef enum {
-	e1000_10_half = 0,
-	e1000_10_full = 1,
-	e1000_100_half = 2,
-	e1000_100_full = 3
-} e1000_speed_duplex_type;
-
-typedef enum {
-	e1000_lan_a = 0,
-	e1000_lan_b = 1
-} e1000_lan_loc;
-
-/* Flow Control Settings */
-typedef enum {
-	e1000_fc_none = 0,
-	e1000_fc_rx_pause = 1,
-	e1000_fc_tx_pause = 2,
-	e1000_fc_full = 3,
-	e1000_fc_default = 0xFF
-} e1000_fc_type;
-
-/* PCI bus types */
-typedef enum {
-	e1000_bus_type_unknown = 0,
-	e1000_bus_type_pci,
-	e1000_bus_type_pcix
-} e1000_bus_type;
-
-/* PCI bus speeds */
-typedef enum {
-	e1000_bus_speed_unknown = 0,
-	e1000_bus_speed_33,
-	e1000_bus_speed_66,
-	e1000_bus_speed_100,
-	e1000_bus_speed_133,
-	e1000_bus_speed_reserved
-} e1000_bus_speed;
-
-/* PCI bus widths */
-typedef enum {
-	e1000_bus_width_unknown = 0,
-	e1000_bus_width_32,
-	e1000_bus_width_64
-} e1000_bus_width;
-
-/* PHY status info structure and supporting enums */
-typedef enum {
-	e1000_cable_length_50 = 0,
-	e1000_cable_length_50_80,
-	e1000_cable_length_80_110,
-	e1000_cable_length_110_140,
-	e1000_cable_length_140,
-	e1000_cable_length_undefined = 0xFF
-} e1000_cable_length;
-
-typedef enum {
-	e1000_10bt_ext_dist_enable_normal = 0,
-	e1000_10bt_ext_dist_enable_lower,
-	e1000_10bt_ext_dist_enable_undefined = 0xFF
-} e1000_10bt_ext_dist_enable;
-
-typedef enum {
-	e1000_rev_polarity_normal = 0,
-	e1000_rev_polarity_reversed,
-	e1000_rev_polarity_undefined = 0xFF
-} e1000_rev_polarity;
-
-typedef enum {
-	e1000_polarity_reversal_enabled = 0,
-	e1000_polarity_reversal_disabled,
-	e1000_polarity_reversal_undefined = 0xFF
-} e1000_polarity_reversal;
-
-typedef enum {
-	e1000_auto_x_mode_manual_mdi = 0,
-	e1000_auto_x_mode_manual_mdix,
-	e1000_auto_x_mode_auto1,
-	e1000_auto_x_mode_auto2,
-	e1000_auto_x_mode_undefined = 0xFF
-} e1000_auto_x_mode;
-
-typedef enum {
-	e1000_1000t_rx_status_not_ok = 0,
-	e1000_1000t_rx_status_ok,
-	e1000_1000t_rx_status_undefined = 0xFF
-} e1000_1000t_rx_status;
-
-struct e1000_phy_info {
-	e1000_cable_length cable_length;
-	e1000_10bt_ext_dist_enable extended_10bt_distance;
-	e1000_rev_polarity cable_polarity;
-	e1000_polarity_reversal polarity_correction;
-	e1000_auto_x_mode mdix_mode;
-	e1000_1000t_rx_status local_rx;
-	e1000_1000t_rx_status remote_rx;
-};
-
-struct e1000_phy_stats {
-	uint32_t idle_errors;
-	uint32_t receive_errors;
-};
-
-/* Error Codes */
-#define E1000_SUCCESS      0
-#define E1000_ERR_EEPROM   1
-#define E1000_ERR_PHY      2
-#define E1000_ERR_CONFIG   3
-#define E1000_ERR_PARAM    4
-#define E1000_ERR_MAC_TYPE 5
-#define E1000_ERR_NOLINK   6
-#define E1000_ERR_TIMEOUT  7
-
-/* PCI Device IDs */
-#define E1000_DEV_ID_82542          0x1000
-#define E1000_DEV_ID_82543GC_FIBER  0x1001
-#define E1000_DEV_ID_82543GC_COPPER 0x1004
-#define E1000_DEV_ID_82544EI_COPPER 0x1008
-#define E1000_DEV_ID_82544EI_FIBER  0x1009
-#define E1000_DEV_ID_82544GC_COPPER 0x100C
-#define E1000_DEV_ID_82544GC_LOM    0x100D
-#define E1000_DEV_ID_82540EM        0x100E
-#define E1000_DEV_ID_82540EM_LOM    0x1015
-#define E1000_DEV_ID_82545EM_COPPER 0x100F
-#define E1000_DEV_ID_82545EM_FIBER  0x1011
-#define E1000_DEV_ID_82546EB_COPPER 0x1010
-#define E1000_DEV_ID_82546EB_FIBER  0x1012
-#define NUM_DEV_IDS 13
-
-#define NODE_ADDRESS_SIZE 6
-#define ETH_LENGTH_OF_ADDRESS 6
-
-/* MAC decode size is 128K - This is the size of BAR0 */
-#define MAC_DECODE_SIZE (128 * 1024)
-
-#define E1000_82542_2_0_REV_ID 2
-#define E1000_82542_2_1_REV_ID 3
-
-#define SPEED_10    10
-#define SPEED_100   100
-#define SPEED_1000  1000
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
-
-/* The sizes (in bytes) of a ethernet packet */
-#define ENET_HEADER_SIZE             14
-#define MAXIMUM_ETHERNET_FRAME_SIZE  1518	/* With FCS */
-#define MINIMUM_ETHERNET_FRAME_SIZE  64	/* With FCS */
-#define ETHERNET_FCS_SIZE            4
-#define MAXIMUM_ETHERNET_PACKET_SIZE \
-    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
-#define MINIMUM_ETHERNET_PACKET_SIZE \
-    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
-#define CRC_LENGTH                   ETHERNET_FCS_SIZE
-#define MAX_JUMBO_FRAME_SIZE         0x3F00
-
-/* 802.1q VLAN Packet Sizes */
-#define VLAN_TAG_SIZE                     4	/* 802.3ac tag (not DMAed) */
-
-/* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE 0x8100	/* 802.3ac packet */
-#define ETHERNET_IP_TYPE        0x0800	/* IP packets */
-#define ETHERNET_ARP_TYPE       0x0806	/* Address Resolution Protocol (ARP) */
-
-/* Packet Header defines */
-#define IP_PROTOCOL_TCP    6
-#define IP_PROTOCOL_UDP    0x11
-
-/* This defines the bits that are set in the Interrupt Mask
- * Set/Read Register.  Each bit is documented below:
- *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- *   o RXSEQ  = Receive Sequence Error
- */
-#define POLL_IMS_ENABLE_MASK ( \
-    E1000_IMS_RXDMT0 |         \
-    E1000_IMS_RXSEQ)
-
-/* This defines the bits that are set in the Interrupt Mask
- * Set/Read Register.  Each bit is documented below:
- *   o RXT0   = Receiver Timer Interrupt (ring 0)
- *   o TXDW   = Transmit Descriptor Written Back
- *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- *   o RXSEQ  = Receive Sequence Error
- *   o LSC    = Link Status Change
- */
-#define IMS_ENABLE_MASK ( \
-    E1000_IMS_RXT0   |    \
-    E1000_IMS_TXDW   |    \
-    E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ  |    \
-    E1000_IMS_LSC)
-
-/* The number of high/low register pairs in the RAR. The RAR (Receive Address
- * Registers) holds the directed and multicast addresses that we monitor. We
- * reserve one of these spots for our directed address, allowing us room for
- * E1000_RAR_ENTRIES - 1 multicast addresses.
- */
-#define E1000_RAR_ENTRIES 16
-
-#define MIN_NUMBER_OF_DESCRIPTORS 8
-#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
-
-/* Receive Descriptor */
-struct e1000_rx_desc {
-	uint64_t buffer_addr;	/* Address of the descriptor's data buffer */
-	uint16_t length;	/* Length of data DMAed into data buffer */
-	uint16_t csum;		/* Packet checksum */
-	uint8_t status;		/* Descriptor status */
-	uint8_t errors;		/* Descriptor Errors */
-	uint16_t special;
-};
-
-/* Receive Decriptor bit definitions */
-#define E1000_RXD_STAT_DD       0x01	/* Descriptor Done */
-#define E1000_RXD_STAT_EOP      0x02	/* End of Packet */
-#define E1000_RXD_STAT_IXSM     0x04	/* Ignore checksum */
-#define E1000_RXD_STAT_VP       0x08	/* IEEE VLAN Packet */
-#define E1000_RXD_STAT_TCPCS    0x20	/* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS     0x40	/* IP xsum calculated */
-#define E1000_RXD_STAT_PIF      0x80	/* passed in-exact filter */
-#define E1000_RXD_ERR_CE        0x01	/* CRC Error */
-#define E1000_RXD_ERR_SE        0x02	/* Symbol Error */
-#define E1000_RXD_ERR_SEQ       0x04	/* Sequence Error */
-#define E1000_RXD_ERR_CXE       0x10	/* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE      0x20	/* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE       0x40	/* IP Checksum Error */
-#define E1000_RXD_ERR_RXE       0x80	/* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF	/* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK  0xE000	/* Priority is in upper 3 bits */
-#define E1000_RXD_SPC_PRI_SHIFT 0x000D	/* Priority is in upper 3 of 16 */
-#define E1000_RXD_SPC_CFI_MASK  0x1000	/* CFI is bit 12 */
-#define E1000_RXD_SPC_CFI_SHIFT 0x000C	/* CFI is bit 12 */
-
-/* mask to determine if packets should be dropped due to frame errors */
-#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
-    E1000_RXD_ERR_CE  |                \
-    E1000_RXD_ERR_SE  |                \
-    E1000_RXD_ERR_SEQ |                \
-    E1000_RXD_ERR_CXE |                \
-    E1000_RXD_ERR_RXE)
-
-/* Transmit Descriptor */
-struct e1000_tx_desc {
-	uint64_t buffer_addr;	/* Address of the descriptor's data buffer */
-	union {
-		uint32_t data;
-		struct {
-			uint16_t length;	/* Data buffer length */
-			uint8_t cso;	/* Checksum offset */
-			uint8_t cmd;	/* Descriptor control */
-		} flags;
-	} lower;
-	union {
-		uint32_t data;
-		struct {
-			uint8_t status;	/* Descriptor status */
-			uint8_t css;	/* Checksum start */
-			uint16_t special;
-		} fields;
-	} upper;
-};
-
-/* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D     0x00100000	/* Data Descriptor */
-#define E1000_TXD_DTYP_C     0x00000000	/* Context Descriptor */
-#define E1000_TXD_POPTS_IXSM 0x01	/* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM 0x02	/* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP    0x01000000	/* End of Packet */
-#define E1000_TXD_CMD_IFCS   0x02000000	/* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC     0x04000000	/* Insert Checksum */
-#define E1000_TXD_CMD_RS     0x08000000	/* Report Status */
-#define E1000_TXD_CMD_RPS    0x10000000	/* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT   0x20000000	/* Descriptor extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE    0x40000000	/* Add VLAN tag */
-#define E1000_TXD_CMD_IDE    0x80000000	/* Enable Tidv register */
-#define E1000_TXD_STAT_DD    0x00000001	/* Descriptor Done */
-#define E1000_TXD_STAT_EC    0x00000002	/* Excess Collisions */
-#define E1000_TXD_STAT_LC    0x00000004	/* Late Collisions */
-#define E1000_TXD_STAT_TU    0x00000008	/* Transmit underrun */
-#define E1000_TXD_CMD_TCP    0x01000000	/* TCP packet */
-#define E1000_TXD_CMD_IP     0x02000000	/* IP packet */
-#define E1000_TXD_CMD_TSE    0x04000000	/* TCP Seg enable */
-#define E1000_TXD_STAT_TC    0x00000004	/* Tx Underrun */
-
-/* Offload Context Descriptor */
-struct e1000_context_desc {
-	union {
-		uint32_t ip_config;
-		struct {
-			uint8_t ipcss;	/* IP checksum start */
-			uint8_t ipcso;	/* IP checksum offset */
-			uint16_t ipcse;	/* IP checksum end */
-		} ip_fields;
-	} lower_setup;
-	union {
-		uint32_t tcp_config;
-		struct {
-			uint8_t tucss;	/* TCP checksum start */
-			uint8_t tucso;	/* TCP checksum offset */
-			uint16_t tucse;	/* TCP checksum end */
-		} tcp_fields;
-	} upper_setup;
-	uint32_t cmd_and_length;	/* */
-	union {
-		uint32_t data;
-		struct {
-			uint8_t status;	/* Descriptor status */
-			uint8_t hdr_len;	/* Header length */
-			uint16_t mss;	/* Maximum segment size */
-		} fields;
-	} tcp_seg_setup;
-};
-
-/* Offload data descriptor */
-struct e1000_data_desc {
-	uint64_t buffer_addr;	/* Address of the descriptor's buffer address */
-	union {
-		uint32_t data;
-		struct {
-			uint16_t length;	/* Data buffer length */
-			uint8_t typ_len_ext;	/* */
-			uint8_t cmd;	/* */
-		} flags;
-	} lower;
-	union {
-		uint32_t data;
-		struct {
-			uint8_t status;	/* Descriptor status */
-			uint8_t popts;	/* Packet Options */
-			uint16_t special;	/* */
-		} fields;
-	} upper;
-};
-
-/* Filters */
-#define E1000_NUM_UNICAST          16	/* Unicast filter entries */
-#define E1000_MC_TBL_SIZE          128	/* Multicast Filter Table (4096 bits) */
-#define E1000_VLAN_FILTER_TBL_SIZE 128	/* VLAN Filter Table (4096 bits) */
-
-/* Receive Address Register */
-struct e1000_rar {
-	volatile uint32_t low;	/* receive address low */
-	volatile uint32_t high;	/* receive address high */
-};
-
-/* The number of entries in the Multicast Table Array (MTA). */
-#define E1000_NUM_MTA_REGISTERS 128
-
-/* IPv4 Address Table Entry */
-struct e1000_ipv4_at_entry {
-	volatile uint32_t ipv4_addr;	/* IP Address (RW) */
-	volatile uint32_t reserved;
-};
-
-/* Four wakeup IP addresses are supported */
-#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
-#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
-#define E1000_IP6AT_SIZE                  1
-
-/* IPv6 Address Table Entry */
-struct e1000_ipv6_at_entry {
-	volatile uint8_t ipv6_addr[16];
-};
-
-/* Flexible Filter Length Table Entry */
-struct e1000_fflt_entry {
-	volatile uint32_t length;	/* Flexible Filter Length (RW) */
-	volatile uint32_t reserved;
-};
-
-/* Flexible Filter Mask Table Entry */
-struct e1000_ffmt_entry {
-	volatile uint32_t mask;	/* Flexible Filter Mask (RW) */
-	volatile uint32_t reserved;
-};
-
-/* Flexible Filter Value Table Entry */
-struct e1000_ffvt_entry {
-	volatile uint32_t value;	/* Flexible Filter Value (RW) */
-	volatile uint32_t reserved;
-};
-
-/* Four Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
-
-/* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
-
-#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
-#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-
-/* Register Set. (82543, 82544)
- *
- * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
- * These registers are physically located on the NIC, but are mapped into the
- * host memory address space.
- *
- * RW - register is both readable and writable
- * RO - register is read only
- * WO - register is write only
- * R/clr - register is read only and is cleared when read
- * A - register array
- */
-#define E1000_CTRL     0x00000	/* Device Control - RW */
-#define E1000_STATUS   0x00008	/* Device Status - RO */
-#define E1000_EECD     0x00010	/* EEPROM/Flash Control - RW */
-#define E1000_EERD     0x00014	/* EEPROM Read - RW */
-#define E1000_CTRL_EXT 0x00018	/* Extended Device Control - RW */
-#define E1000_MDIC     0x00020	/* MDI Control - RW */
-#define E1000_FCAL     0x00028	/* Flow Control Address Low - RW */
-#define E1000_FCAH     0x0002C	/* Flow Control Address High -RW */
-#define E1000_FCT      0x00030	/* Flow Control Type - RW */
-#define E1000_VET      0x00038	/* VLAN Ether Type - RW */
-#define E1000_ICR      0x000C0	/* Interrupt Cause Read - R/clr */
-#define E1000_ITR      0x000C4	/* Interrupt Throttling Rate - RW */
-#define E1000_ICS      0x000C8	/* Interrupt Cause Set - WO */
-#define E1000_IMS      0x000D0	/* Interrupt Mask Set - RW */
-#define E1000_IMC      0x000D8	/* Interrupt Mask Clear - WO */
-#define E1000_RCTL     0x00100	/* RX Control - RW */
-#define E1000_FCTTV    0x00170	/* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW     0x00178	/* TX Configuration Word - RW */
-#define E1000_RXCW     0x00180	/* RX Configuration Word - RO */
-#define E1000_TCTL     0x00400	/* TX Control - RW */
-#define E1000_TIPG     0x00410	/* TX Inter-packet gap -RW */
-#define E1000_TBT      0x00448	/* TX Burst Timer - RW */
-#define E1000_AIT      0x00458	/* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL   0x00E00	/* LED Control - RW */
-#define E1000_PBA      0x01000	/* Packet Buffer Allocation - RW */
-#define E1000_FCRTL    0x02160	/* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH    0x02168	/* Flow Control Receive Threshold High - RW */
-#define E1000_RDBAL    0x02800	/* RX Descriptor Base Address Low - RW */
-#define E1000_RDBAH    0x02804	/* RX Descriptor Base Address High - RW */
-#define E1000_RDLEN    0x02808	/* RX Descriptor Length - RW */
-#define E1000_RDH      0x02810	/* RX Descriptor Head - RW */
-#define E1000_RDT      0x02818	/* RX Descriptor Tail - RW */
-#define E1000_RDTR     0x02820	/* RX Delay Timer - RW */
-#define E1000_RXDCTL   0x02828	/* RX Descriptor Control - RW */
-#define E1000_RADV     0x0282C	/* RX Interrupt Absolute Delay Timer - RW */
-#define E1000_RSRPD    0x02C00	/* RX Small Packet Detect - RW */
-#define E1000_TXDMAC   0x03000	/* TX DMA Control - RW */
-#define E1000_TDBAL    0x03800	/* TX Descriptor Base Address Low - RW */
-#define E1000_TDBAH    0x03804	/* TX Descriptor Base Address High - RW */
-#define E1000_TDLEN    0x03808	/* TX Descriptor Length - RW */
-#define E1000_TDH      0x03810	/* TX Descriptor Head - RW */
-#define E1000_TDT      0x03818	/* TX Descripotr Tail - RW */
-#define E1000_TIDV     0x03820	/* TX Interrupt Delay Value - RW */
-#define E1000_TXDCTL   0x03828	/* TX Descriptor Control - RW */
-#define E1000_TADV     0x0382C	/* TX Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT    0x03830	/* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_CRCERRS  0x04000	/* CRC Error Count - R/clr */
-#define E1000_ALGNERRC 0x04004	/* Alignment Error Count - R/clr */
-#define E1000_SYMERRS  0x04008	/* Symbol Error Count - R/clr */
-#define E1000_RXERRC   0x0400C	/* Receive Error Count - R/clr */
-#define E1000_MPC      0x04010	/* Missed Packet Count - R/clr */
-#define E1000_SCC      0x04014	/* Single Collision Count - R/clr */
-#define E1000_ECOL     0x04018	/* Excessive Collision Count - R/clr */
-#define E1000_MCC      0x0401C	/* Multiple Collision Count - R/clr */
-#define E1000_LATECOL  0x04020	/* Late Collision Count - R/clr */
-#define E1000_COLC     0x04028	/* Collision Count - R/clr */
-#define E1000_DC       0x04030	/* Defer Count - R/clr */
-#define E1000_TNCRS    0x04034	/* TX-No CRS - R/clr */
-#define E1000_SEC      0x04038	/* Sequence Error Count - R/clr */
-#define E1000_CEXTERR  0x0403C	/* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC     0x04040	/* Receive Length Error Count - R/clr */
-#define E1000_XONRXC   0x04048	/* XON RX Count - R/clr */
-#define E1000_XONTXC   0x0404C	/* XON TX Count - R/clr */
-#define E1000_XOFFRXC  0x04050	/* XOFF RX Count - R/clr */
-#define E1000_XOFFTXC  0x04054	/* XOFF TX Count - R/clr */
-#define E1000_FCRUC    0x04058	/* Flow Control RX Unsupported Count- R/clr */
-#define E1000_PRC64    0x0405C	/* Packets RX (64 bytes) - R/clr */
-#define E1000_PRC127   0x04060	/* Packets RX (65-127 bytes) - R/clr */
-#define E1000_PRC255   0x04064	/* Packets RX (128-255 bytes) - R/clr */
-#define E1000_PRC511   0x04068	/* Packets RX (255-511 bytes) - R/clr */
-#define E1000_PRC1023  0x0406C	/* Packets RX (512-1023 bytes) - R/clr */
-#define E1000_PRC1522  0x04070	/* Packets RX (1024-1522 bytes) - R/clr */
-#define E1000_GPRC     0x04074	/* Good Packets RX Count - R/clr */
-#define E1000_BPRC     0x04078	/* Broadcast Packets RX Count - R/clr */
-#define E1000_MPRC     0x0407C	/* Multicast Packets RX Count - R/clr */
-#define E1000_GPTC     0x04080	/* Good Packets TX Count - R/clr */
-#define E1000_GORCL    0x04088	/* Good Octets RX Count Low - R/clr */
-#define E1000_GORCH    0x0408C	/* Good Octets RX Count High - R/clr */
-#define E1000_GOTCL    0x04090	/* Good Octets TX Count Low - R/clr */
-#define E1000_GOTCH    0x04094	/* Good Octets TX Count High - R/clr */
-#define E1000_RNBC     0x040A0	/* RX No Buffers Count - R/clr */
-#define E1000_RUC      0x040A4	/* RX Undersize Count - R/clr */
-#define E1000_RFC      0x040A8	/* RX Fragment Count - R/clr */
-#define E1000_ROC      0x040AC	/* RX Oversize Count - R/clr */
-#define E1000_RJC      0x040B0	/* RX Jabber Count - R/clr */
-#define E1000_MGTPRC   0x040B4	/* Management Packets RX Count - R/clr */
-#define E1000_MGTPDC   0x040B8	/* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC   0x040BC	/* Management Packets TX Count - R/clr */
-#define E1000_TORL     0x040C0	/* Total Octets RX Low - R/clr */
-#define E1000_TORH     0x040C4	/* Total Octets RX High - R/clr */
-#define E1000_TOTL     0x040C8	/* Total Octets TX Low - R/clr */
-#define E1000_TOTH     0x040CC	/* Total Octets TX High - R/clr */
-#define E1000_TPR      0x040D0	/* Total Packets RX - R/clr */
-#define E1000_TPT      0x040D4	/* Total Packets TX - R/clr */
-#define E1000_PTC64    0x040D8	/* Packets TX (64 bytes) - R/clr */
-#define E1000_PTC127   0x040DC	/* Packets TX (65-127 bytes) - R/clr */
-#define E1000_PTC255   0x040E0	/* Packets TX (128-255 bytes) - R/clr */
-#define E1000_PTC511   0x040E4	/* Packets TX (256-511 bytes) - R/clr */
-#define E1000_PTC1023  0x040E8	/* Packets TX (512-1023 bytes) - R/clr */
-#define E1000_PTC1522  0x040EC	/* Packets TX (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC     0x040F0	/* Multicast Packets TX Count - R/clr */
-#define E1000_BPTC     0x040F4	/* Broadcast Packets TX Count - R/clr */
-#define E1000_TSCTC    0x040F8	/* TCP Segmentation Context TX - R/clr */
-#define E1000_TSCTFC   0x040FC	/* TCP Segmentation Context TX Fail - R/clr */
-#define E1000_RXCSUM   0x05000	/* RX Checksum Control - RW */
-#define E1000_MTA      0x05200	/* Multicast Table Array - RW Array */
-#define E1000_RA       0x05400	/* Receive Address - RW Array */
-#define E1000_VFTA     0x05600	/* VLAN Filter Table Array - RW Array */
-#define E1000_WUC      0x05800	/* Wakeup Control - RW */
-#define E1000_WUFC     0x05808	/* Wakeup Filter Control - RW */
-#define E1000_WUS      0x05810	/* Wakeup Status - RO */
-#define E1000_MANC     0x05820	/* Management Control - RW */
-#define E1000_IPAV     0x05838	/* IP Address Valid - RW */
-#define E1000_IP4AT    0x05840	/* IPv4 Address Table - RW Array */
-#define E1000_IP6AT    0x05880	/* IPv6 Address Table - RW Array */
-#define E1000_WUPL     0x05900	/* Wakeup Packet Length - RW */
-#define E1000_WUPM     0x05A00	/* Wakeup Packet Memory - RO A */
-#define E1000_FFLT     0x05F00	/* Flexible Filter Length Table - RW Array */
-#define E1000_FFMT     0x09000	/* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT     0x09800	/* Flexible Filter Value Table - RW Array */
-
-/* Register Set (82542)
- *
- * Some of the 82542 registers are located at different offsets than they are
- * in more current versions of the 8254x. Despite the difference in location,
- * the registers function in the same manner.
- */
-#define E1000_82542_CTRL     E1000_CTRL
-#define E1000_82542_STATUS   E1000_STATUS
-#define E1000_82542_EECD     E1000_EECD
-#define E1000_82542_EERD     E1000_EERD
-#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
-#define E1000_82542_MDIC     E1000_MDIC
-#define E1000_82542_FCAL     E1000_FCAL
-#define E1000_82542_FCAH     E1000_FCAH
-#define E1000_82542_FCT      E1000_FCT
-#define E1000_82542_VET      E1000_VET
-#define E1000_82542_RA       0x00040
-#define E1000_82542_ICR      E1000_ICR
-#define E1000_82542_ITR      E1000_ITR
-#define E1000_82542_ICS      E1000_ICS
-#define E1000_82542_IMS      E1000_IMS
-#define E1000_82542_IMC      E1000_IMC
-#define E1000_82542_RCTL     E1000_RCTL
-#define E1000_82542_RDTR     0x00108
-#define E1000_82542_RDBAL    0x00110
-#define E1000_82542_RDBAH    0x00114
-#define E1000_82542_RDLEN    0x00118
-#define E1000_82542_RDH      0x00120
-#define E1000_82542_RDT      0x00128
-#define E1000_82542_FCRTH    0x00160
-#define E1000_82542_FCRTL    0x00168
-#define E1000_82542_FCTTV    E1000_FCTTV
-#define E1000_82542_TXCW     E1000_TXCW
-#define E1000_82542_RXCW     E1000_RXCW
-#define E1000_82542_MTA      0x00200
-#define E1000_82542_TCTL     E1000_TCTL
-#define E1000_82542_TIPG     E1000_TIPG
-#define E1000_82542_TDBAL    0x00420
-#define E1000_82542_TDBAH    0x00424
-#define E1000_82542_TDLEN    0x00428
-#define E1000_82542_TDH      0x00430
-#define E1000_82542_TDT      0x00438
-#define E1000_82542_TIDV     0x00440
-#define E1000_82542_TBT      E1000_TBT
-#define E1000_82542_AIT      E1000_AIT
-#define E1000_82542_VFTA     0x00600
-#define E1000_82542_LEDCTL   E1000_LEDCTL
-#define E1000_82542_PBA      E1000_PBA
-#define E1000_82542_RXDCTL   E1000_RXDCTL
-#define E1000_82542_RADV     E1000_RADV
-#define E1000_82542_RSRPD    E1000_RSRPD
-#define E1000_82542_TXDMAC   E1000_TXDMAC
-#define E1000_82542_TXDCTL   E1000_TXDCTL
-#define E1000_82542_TADV     E1000_TADV
-#define E1000_82542_TSPMT    E1000_TSPMT
-#define E1000_82542_CRCERRS  E1000_CRCERRS
-#define E1000_82542_ALGNERRC E1000_ALGNERRC
-#define E1000_82542_SYMERRS  E1000_SYMERRS
-#define E1000_82542_RXERRC   E1000_RXERRC
-#define E1000_82542_MPC      E1000_MPC
-#define E1000_82542_SCC      E1000_SCC
-#define E1000_82542_ECOL     E1000_ECOL
-#define E1000_82542_MCC      E1000_MCC
-#define E1000_82542_LATECOL  E1000_LATECOL
-#define E1000_82542_COLC     E1000_COLC
-#define E1000_82542_DC       E1000_DC
-#define E1000_82542_TNCRS    E1000_TNCRS
-#define E1000_82542_SEC      E1000_SEC
-#define E1000_82542_CEXTERR  E1000_CEXTERR
-#define E1000_82542_RLEC     E1000_RLEC
-#define E1000_82542_XONRXC   E1000_XONRXC
-#define E1000_82542_XONTXC   E1000_XONTXC
-#define E1000_82542_XOFFRXC  E1000_XOFFRXC
-#define E1000_82542_XOFFTXC  E1000_XOFFTXC
-#define E1000_82542_FCRUC    E1000_FCRUC
-#define E1000_82542_PRC64    E1000_PRC64
-#define E1000_82542_PRC127   E1000_PRC127
-#define E1000_82542_PRC255   E1000_PRC255
-#define E1000_82542_PRC511   E1000_PRC511
-#define E1000_82542_PRC1023  E1000_PRC1023
-#define E1000_82542_PRC1522  E1000_PRC1522
-#define E1000_82542_GPRC     E1000_GPRC
-#define E1000_82542_BPRC     E1000_BPRC
-#define E1000_82542_MPRC     E1000_MPRC
-#define E1000_82542_GPTC     E1000_GPTC
-#define E1000_82542_GORCL    E1000_GORCL
-#define E1000_82542_GORCH    E1000_GORCH
-#define E1000_82542_GOTCL    E1000_GOTCL
-#define E1000_82542_GOTCH    E1000_GOTCH
-#define E1000_82542_RNBC     E1000_RNBC
-#define E1000_82542_RUC      E1000_RUC
-#define E1000_82542_RFC      E1000_RFC
-#define E1000_82542_ROC      E1000_ROC
-#define E1000_82542_RJC      E1000_RJC
-#define E1000_82542_MGTPRC   E1000_MGTPRC
-#define E1000_82542_MGTPDC   E1000_MGTPDC
-#define E1000_82542_MGTPTC   E1000_MGTPTC
-#define E1000_82542_TORL     E1000_TORL
-#define E1000_82542_TORH     E1000_TORH
-#define E1000_82542_TOTL     E1000_TOTL
-#define E1000_82542_TOTH     E1000_TOTH
-#define E1000_82542_TPR      E1000_TPR
-#define E1000_82542_TPT      E1000_TPT
-#define E1000_82542_PTC64    E1000_PTC64
-#define E1000_82542_PTC127   E1000_PTC127
-#define E1000_82542_PTC255   E1000_PTC255
-#define E1000_82542_PTC511   E1000_PTC511
-#define E1000_82542_PTC1023  E1000_PTC1023
-#define E1000_82542_PTC1522  E1000_PTC1522
-#define E1000_82542_MPTC     E1000_MPTC
-#define E1000_82542_BPTC     E1000_BPTC
-#define E1000_82542_TSCTC    E1000_TSCTC
-#define E1000_82542_TSCTFC   E1000_TSCTFC
-#define E1000_82542_RXCSUM   E1000_RXCSUM
-#define E1000_82542_WUC      E1000_WUC
-#define E1000_82542_WUFC     E1000_WUFC
-#define E1000_82542_WUS      E1000_WUS
-#define E1000_82542_MANC     E1000_MANC
-#define E1000_82542_IPAV     E1000_IPAV
-#define E1000_82542_IP4AT    E1000_IP4AT
-#define E1000_82542_IP6AT    E1000_IP6AT
-#define E1000_82542_WUPL     E1000_WUPL
-#define E1000_82542_WUPM     E1000_WUPM
-#define E1000_82542_FFLT     E1000_FFLT
-#define E1000_82542_FFMT     E1000_FFMT
-#define E1000_82542_FFVT     E1000_FFVT
-
-/* Statistics counters collected by the MAC */
-struct e1000_hw_stats {
-	uint64_t crcerrs;
-	uint64_t algnerrc;
-	uint64_t symerrs;
-	uint64_t rxerrc;
-	uint64_t mpc;
-	uint64_t scc;
-	uint64_t ecol;
-	uint64_t mcc;
-	uint64_t latecol;
-	uint64_t colc;
-	uint64_t dc;
-	uint64_t tncrs;
-	uint64_t sec;
-	uint64_t cexterr;
-	uint64_t rlec;
-	uint64_t xonrxc;
-	uint64_t xontxc;
-	uint64_t xoffrxc;
-	uint64_t xofftxc;
-	uint64_t fcruc;
-	uint64_t prc64;
-	uint64_t prc127;
-	uint64_t prc255;
-	uint64_t prc511;
-	uint64_t prc1023;
-	uint64_t prc1522;
-	uint64_t gprc;
-	uint64_t bprc;
-	uint64_t mprc;
-	uint64_t gptc;
-	uint64_t gorcl;
-	uint64_t gorch;
-	uint64_t gotcl;
-	uint64_t gotch;
-	uint64_t rnbc;
-	uint64_t ruc;
-	uint64_t rfc;
-	uint64_t roc;
-	uint64_t rjc;
-	uint64_t mgprc;
-	uint64_t mgpdc;
-	uint64_t mgptc;
-	uint64_t torl;
-	uint64_t torh;
-	uint64_t totl;
-	uint64_t toth;
-	uint64_t tpr;
-	uint64_t tpt;
-	uint64_t ptc64;
-	uint64_t ptc127;
-	uint64_t ptc255;
-	uint64_t ptc511;
-	uint64_t ptc1023;
-	uint64_t ptc1522;
-	uint64_t mptc;
-	uint64_t bptc;
-	uint64_t tsctc;
-	uint64_t tsctfc;
-};
-
-/* Structure containing variables used by the shared code (e1000_hw.c) */
-struct e1000_hw {
-	pci_dev_t pdev;
-	uint8_t *hw_addr;
-	e1000_mac_type mac_type;
-	e1000_media_type media_type;
-	e1000_lan_loc lan_loc;
-	e1000_fc_type fc;
-	uint32_t phy_id;
-	uint32_t phy_addr;
-	uint32_t original_fc;
-	uint32_t txcw;
-	uint32_t autoneg_failed;
-	uint16_t autoneg_advertised;
-	uint16_t pci_cmd_word;
-	uint16_t fc_high_water;
-	uint16_t fc_low_water;
-	uint16_t fc_pause_time;
-	uint16_t device_id;
-	uint16_t vendor_id;
-	uint16_t subsystem_id;
-	uint16_t subsystem_vendor_id;
-	uint8_t revision_id;
-	boolean_t get_link_status;
-	boolean_t tbi_compatibility_en;
-	boolean_t tbi_compatibility_on;
-	boolean_t fc_send_xon;
-	boolean_t report_tx_early;
-};
-
-#define E1000_EEPROM_SWDPIN0   0x0001	/* SWDPIN 0 EEPROM Value */
-#define E1000_EEPROM_LED_LOGIC 0x0020	/* Led Logic Word */
-
-/* Register Bit Masks */
-/* Device Control */
-#define E1000_CTRL_FD       0x00000001	/* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM      0x00000002	/* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR    0x00000004	/* Priority on PCI. 0=rx,1=fair */
-#define E1000_CTRL_LRST     0x00000008	/* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME      0x00000010	/* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE      0x00000020	/* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE     0x00000020	/* Auto-speed detect enable */
-#define E1000_CTRL_SLU      0x00000040	/* Set link up (Force Link) */
-#define E1000_CTRL_ILOS     0x00000080	/* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL  0x00000300	/* Speed Select Mask */
-#define E1000_CTRL_SPD_10   0x00000000	/* Force 10Mb */
-#define E1000_CTRL_SPD_100  0x00000100	/* Force 100Mb */
-#define E1000_CTRL_SPD_1000 0x00000200	/* Force 1Gb */
-#define E1000_CTRL_BEM32    0x00000400	/* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD   0x00000800	/* Force Speed */
-#define E1000_CTRL_FRCDPX   0x00001000	/* Force Duplex */
-#define E1000_CTRL_SWDPIN0  0x00040000	/* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1  0x00080000	/* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2  0x00100000	/* SWDPIN 2 value */
-#define E1000_CTRL_SWDPIN3  0x00200000	/* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0  0x00400000	/* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1  0x00800000	/* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2  0x01000000	/* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3  0x02000000	/* SWDPIN 3 input or output */
-#define E1000_CTRL_RST      0x04000000	/* Global reset */
-#define E1000_CTRL_RFCE     0x08000000	/* Receive Flow Control enable */
-#define E1000_CTRL_TFCE     0x10000000	/* Transmit flow control enable */
-#define E1000_CTRL_RTE      0x20000000	/* Routing tag enable */
-#define E1000_CTRL_VME      0x40000000	/* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST  0x80000000	/* PHY Reset */
-
-/* Device Status */
-#define E1000_STATUS_FD         0x00000001	/* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU         0x00000002	/* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK  0x0000000C	/* PCI Function Mask */
-#define E1000_STATUS_FUNC_0     0x00000000	/* Function 0 */
-#define E1000_STATUS_FUNC_1     0x00000004	/* Function 1 */
-#define E1000_STATUS_TXOFF      0x00000010	/* transmission paused */
-#define E1000_STATUS_TBIMODE    0x00000020	/* TBI mode */
-#define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10   0x00000000	/* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100  0x00000040	/* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000 0x00000080	/* Speed 1000Mb/s */
-#define E1000_STATUS_ASDV       0x00000300	/* Auto speed detect value */
-#define E1000_STATUS_MTXCKOK    0x00000400	/* MTX clock running OK */
-#define E1000_STATUS_PCI66      0x00000800	/* In 66Mhz slot */
-#define E1000_STATUS_BUS64      0x00001000	/* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE  0x00002000	/* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED 0x0000C000	/* PCI-X bus speed */
-
-/* Constants used to intrepret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66  0x00000000	/* PCI-X bus speed  50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000	/* PCI-X bus speed  66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000	/* PCI-X bus speed 100-133 MHz */
-
-/* EEPROM/Flash Control */
-#define E1000_EECD_SK        0x00000001	/* EEPROM Clock */
-#define E1000_EECD_CS        0x00000002	/* EEPROM Chip Select */
-#define E1000_EECD_DI        0x00000004	/* EEPROM Data In */
-#define E1000_EECD_DO        0x00000008	/* EEPROM Data Out */
-#define E1000_EECD_FWE_MASK  0x00000030
-#define E1000_EECD_FWE_DIS   0x00000010	/* Disable FLASH writes */
-#define E1000_EECD_FWE_EN    0x00000020	/* Enable FLASH writes */
-#define E1000_EECD_FWE_SHIFT 4
-#define E1000_EECD_SIZE      0x00000200	/* EEPROM Size (0=64 word 1=256 word) */
-#define E1000_EECD_REQ       0x00000040	/* EEPROM Access Request */
-#define E1000_EECD_GNT       0x00000080	/* EEPROM Access Grant */
-#define E1000_EECD_PRES      0x00000100	/* EEPROM Present */
-
-/* EEPROM Read */
-#define E1000_EERD_START      0x00000001	/* Start Read */
-#define E1000_EERD_DONE       0x00000010	/* Read Done */
-#define E1000_EERD_ADDR_SHIFT 8
-#define E1000_EERD_ADDR_MASK  0x0000FF00	/* Read Address */
-#define E1000_EERD_DATA_SHIFT 16
-#define E1000_EERD_DATA_MASK  0xFFFF0000	/* Read Data */
-
-/* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN   0x00000001	/* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN   0x00000002	/* Maps SDP5 to GPI1 */
-#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN   0x00000004	/* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN   0x00000008	/* Maps SDP7 to GPI3 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010	/* Value of SW Defineable Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020	/* Value of SW Defineable Pin 5 */
-#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040	/* Value of SW Defineable Pin 6 */
-#define E1000_CTRL_EXT_SWDPIN6 	 0x00000040	/* SWDPIN 6 value */
-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080	/* Value of SW Defineable Pin 7 */
-#define E1000_CTRL_EXT_SWDPIN7 	 0x00000080	/* SWDPIN 7 value */
-#define E1000_CTRL_EXT_SDP4_DIR  0x00000100	/* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR  0x00000200	/* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR  0x00000400	/* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SWDPIO6   0x00000400	/* SWDPIN 6 Input or output */
-#define E1000_CTRL_EXT_SDP7_DIR  0x00000800	/* Direction of SDP7 0=in 1=out */
-#define E1000_CTRL_EXT_SWDPIO7   0x00000800	/* SWDPIN 7 Input or output */
-#define E1000_CTRL_EXT_ASDCHK    0x00001000	/* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST    0x00002000	/* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS       0x00004000	/* Invert Power State */
-#define E1000_CTRL_EXT_SPD_BYPS  0x00008000	/* Speed Select Bypass */
-#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
-#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
-#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
-#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
-#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
-#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
-
-/* MDI Control */
-#define E1000_MDIC_DATA_MASK 0x0000FFFF
-#define E1000_MDIC_REG_MASK  0x001F0000
-#define E1000_MDIC_REG_SHIFT 16
-#define E1000_MDIC_PHY_MASK  0x03E00000
-#define E1000_MDIC_PHY_SHIFT 21
-#define E1000_MDIC_OP_WRITE  0x04000000
-#define E1000_MDIC_OP_READ   0x08000000
-#define E1000_MDIC_READY     0x10000000
-#define E1000_MDIC_INT_EN    0x20000000
-#define E1000_MDIC_ERROR     0x40000000
-
-/* LED Control */
-#define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
-#define E1000_LEDCTL_LED0_MODE_SHIFT 0
-#define E1000_LEDCTL_LED0_IVRT       0x00000040
-#define E1000_LEDCTL_LED0_BLINK      0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT 8
-#define E1000_LEDCTL_LED1_IVRT       0x00004000
-#define E1000_LEDCTL_LED1_BLINK      0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT 16
-#define E1000_LEDCTL_LED2_IVRT       0x00400000
-#define E1000_LEDCTL_LED2_BLINK      0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT 24
-#define E1000_LEDCTL_LED3_IVRT       0x40000000
-#define E1000_LEDCTL_LED3_BLINK      0x80000000
-
-#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
-#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
-#define E1000_LEDCTL_MODE_LINK_UP       0x2
-#define E1000_LEDCTL_MODE_ACTIVITY      0x3
-#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
-#define E1000_LEDCTL_MODE_LINK_10       0x5
-#define E1000_LEDCTL_MODE_LINK_100      0x6
-#define E1000_LEDCTL_MODE_LINK_1000     0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
-#define E1000_LEDCTL_MODE_COLLISION     0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
-#define E1000_LEDCTL_MODE_PAUSED        0xD
-#define E1000_LEDCTL_MODE_LED_ON        0xE
-#define E1000_LEDCTL_MODE_LED_OFF       0xF
-
-/* Receive Address */
-#define E1000_RAH_AV  0x80000000	/* Receive descriptor valid */
-
-/* Interrupt Cause Read */
-#define E1000_ICR_TXDW    0x00000001	/* Transmit desc written back */
-#define E1000_ICR_TXQE    0x00000002	/* Transmit Queue empty */
-#define E1000_ICR_LSC     0x00000004	/* Link Status Change */
-#define E1000_ICR_RXSEQ   0x00000008	/* rx sequence error */
-#define E1000_ICR_RXDMT0  0x00000010	/* rx desc min. threshold (0) */
-#define E1000_ICR_RXO     0x00000040	/* rx overrun */
-#define E1000_ICR_RXT0    0x00000080	/* rx timer intr (ring 0) */
-#define E1000_ICR_MDAC    0x00000200	/* MDIO access complete */
-#define E1000_ICR_RXCFG   0x00000400	/* RX /c/ ordered set */
-#define E1000_ICR_GPI_EN0 0x00000800	/* GP Int 0 */
-#define E1000_ICR_GPI_EN1 0x00001000	/* GP Int 1 */
-#define E1000_ICR_GPI_EN2 0x00002000	/* GP Int 2 */
-#define E1000_ICR_GPI_EN3 0x00004000	/* GP Int 3 */
-#define E1000_ICR_TXD_LOW 0x00008000
-#define E1000_ICR_SRPD    0x00010000
-
-/* Interrupt Cause Set */
-#define E1000_ICS_TXDW    E1000_ICR_TXDW	/* Transmit desc written back */
-#define E1000_ICS_TXQE    E1000_ICR_TXQE	/* Transmit Queue empty */
-#define E1000_ICS_LSC     E1000_ICR_LSC	/* Link Status Change */
-#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ	/* rx sequence error */
-#define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0	/* rx desc min. threshold */
-#define E1000_ICS_RXO     E1000_ICR_RXO	/* rx overrun */
-#define E1000_ICS_RXT0    E1000_ICR_RXT0	/* rx timer intr */
-#define E1000_ICS_MDAC    E1000_ICR_MDAC	/* MDIO access complete */
-#define E1000_ICS_RXCFG   E1000_ICR_RXCFG	/* RX /c/ ordered set */
-#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0	/* GP Int 0 */
-#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1	/* GP Int 1 */
-#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2	/* GP Int 2 */
-#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3	/* GP Int 3 */
-#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD    E1000_ICR_SRPD
-
-/* Interrupt Mask Set */
-#define E1000_IMS_TXDW    E1000_ICR_TXDW	/* Transmit desc written back */
-#define E1000_IMS_TXQE    E1000_ICR_TXQE	/* Transmit Queue empty */
-#define E1000_IMS_LSC     E1000_ICR_LSC	/* Link Status Change */
-#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ	/* rx sequence error */
-#define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0	/* rx desc min. threshold */
-#define E1000_IMS_RXO     E1000_ICR_RXO	/* rx overrun */
-#define E1000_IMS_RXT0    E1000_ICR_RXT0	/* rx timer intr */
-#define E1000_IMS_MDAC    E1000_ICR_MDAC	/* MDIO access complete */
-#define E1000_IMS_RXCFG   E1000_ICR_RXCFG	/* RX /c/ ordered set */
-#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0	/* GP Int 0 */
-#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1	/* GP Int 1 */
-#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2	/* GP Int 2 */
-#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3	/* GP Int 3 */
-#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD    E1000_ICR_SRPD
-
-/* Interrupt Mask Clear */
-#define E1000_IMC_TXDW    E1000_ICR_TXDW	/* Transmit desc written back */
-#define E1000_IMC_TXQE    E1000_ICR_TXQE	/* Transmit Queue empty */
-#define E1000_IMC_LSC     E1000_ICR_LSC	/* Link Status Change */
-#define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ	/* rx sequence error */
-#define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0	/* rx desc min. threshold */
-#define E1000_IMC_RXO     E1000_ICR_RXO	/* rx overrun */
-#define E1000_IMC_RXT0    E1000_ICR_RXT0	/* rx timer intr */
-#define E1000_IMC_MDAC    E1000_ICR_MDAC	/* MDIO access complete */
-#define E1000_IMC_RXCFG   E1000_ICR_RXCFG	/* RX /c/ ordered set */
-#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0	/* GP Int 0 */
-#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1	/* GP Int 1 */
-#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2	/* GP Int 2 */
-#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3	/* GP Int 3 */
-#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMC_SRPD    E1000_ICR_SRPD
-
-/* Receive Control */
-#define E1000_RCTL_RST          0x00000001	/* Software reset */
-#define E1000_RCTL_EN           0x00000002	/* enable */
-#define E1000_RCTL_SBP          0x00000004	/* store bad packet */
-#define E1000_RCTL_UPE          0x00000008	/* unicast promiscuous enable */
-#define E1000_RCTL_MPE          0x00000010	/* multicast promiscuous enab */
-#define E1000_RCTL_LPE          0x00000020	/* long packet enable */
-#define E1000_RCTL_LBM_NO       0x00000000	/* no loopback mode */
-#define E1000_RCTL_LBM_MAC      0x00000040	/* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP      0x00000080	/* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR     0x000000C0	/* tcvr loopback mode */
-#define E1000_RCTL_RDMTS_HALF   0x00000000	/* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT   0x00000100	/* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH  0x00000200	/* rx desc min threshold size */
-#define E1000_RCTL_MO_SHIFT     12	/* multicast offset shift */
-#define E1000_RCTL_MO_0         0x00000000	/* multicast offset 11:0 */
-#define E1000_RCTL_MO_1         0x00001000	/* multicast offset 12:1 */
-#define E1000_RCTL_MO_2         0x00002000	/* multicast offset 13:2 */
-#define E1000_RCTL_MO_3         0x00003000	/* multicast offset 15:4 */
-#define E1000_RCTL_MDR          0x00004000	/* multicast desc ring 0 */
-#define E1000_RCTL_BAM          0x00008000	/* broadcast enable */
-/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048      0x00000000	/* rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024      0x00010000	/* rx buffer size 1024 */
-#define E1000_RCTL_SZ_512       0x00020000	/* rx buffer size 512 */
-#define E1000_RCTL_SZ_256       0x00030000	/* rx buffer size 256 */
-/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384     0x00010000	/* rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192      0x00020000	/* rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096      0x00030000	/* rx buffer size 4096 */
-#define E1000_RCTL_VFE          0x00040000	/* vlan filter enable */
-#define E1000_RCTL_CFIEN        0x00080000	/* canonical form enable */
-#define E1000_RCTL_CFI          0x00100000	/* canonical form indicator */
-#define E1000_RCTL_DPF          0x00400000	/* discard pause frames */
-#define E1000_RCTL_PMCF         0x00800000	/* pass MAC control frames */
-#define E1000_RCTL_BSEX         0x02000000	/* Buffer size extension */
-
-/* Receive Descriptor */
-#define E1000_RDT_DELAY 0x0000ffff	/* Delay timer (1=1024us) */
-#define E1000_RDT_FPDB  0x80000000	/* Flush descriptor block */
-#define E1000_RDLEN_LEN 0x0007ff80	/* descriptor length */
-#define E1000_RDH_RDH   0x0000ffff	/* receive descriptor head */
-#define E1000_RDT_RDT   0x0000ffff	/* receive descriptor tail */
-
-/* Flow Control */
-#define E1000_FCRTH_RTH  0x0000FFF8	/* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000	/* External Flow Control Enable */
-#define E1000_FCRTL_RTL  0x0000FFF8	/* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE 0x80000000	/* Enable XON frame transmission */
-
-/* Receive Descriptor Control */
-#define E1000_RXDCTL_PTHRESH 0x0000003F	/* RXDCTL Prefetch Threshold */
-#define E1000_RXDCTL_HTHRESH 0x00003F00	/* RXDCTL Host Threshold */
-#define E1000_RXDCTL_WTHRESH 0x003F0000	/* RXDCTL Writeback Threshold */
-#define E1000_RXDCTL_GRAN    0x01000000	/* RXDCTL Granularity */
-
-/* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH 0x000000FF	/* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH 0x0000FF00	/* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH 0x00FF0000	/* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN    0x01000000	/* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH 0xFE000000	/* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000	/* GRAN=1, WTHRESH=1 */
-
-/* Transmit Configuration Word */
-#define E1000_TXCW_FD         0x00000020	/* TXCW full duplex */
-#define E1000_TXCW_HD         0x00000040	/* TXCW half duplex */
-#define E1000_TXCW_PAUSE      0x00000080	/* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR    0x00000100	/* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK 0x00000180	/* TXCW pause request mask */
-#define E1000_TXCW_RF         0x00003000	/* TXCW remote fault */
-#define E1000_TXCW_NP         0x00008000	/* TXCW next page */
-#define E1000_TXCW_CW         0x0000ffff	/* TxConfigWord mask */
-#define E1000_TXCW_TXC        0x40000000	/* Transmit Config control */
-#define E1000_TXCW_ANE        0x80000000	/* Auto-neg enable */
-
-/* Receive Configuration Word */
-#define E1000_RXCW_CW    0x0000ffff	/* RxConfigWord mask */
-#define E1000_RXCW_NC    0x04000000	/* Receive config no carrier */
-#define E1000_RXCW_IV    0x08000000	/* Receive config invalid */
-#define E1000_RXCW_CC    0x10000000	/* Receive config change */
-#define E1000_RXCW_C     0x20000000	/* Receive config */
-#define E1000_RXCW_SYNCH 0x40000000	/* Receive config synch */
-#define E1000_RXCW_ANC   0x80000000	/* Auto-neg complete */
-
-/* Transmit Control */
-#define E1000_TCTL_RST    0x00000001	/* software reset */
-#define E1000_TCTL_EN     0x00000002	/* enable tx */
-#define E1000_TCTL_BCE    0x00000004	/* busy check enable */
-#define E1000_TCTL_PSP    0x00000008	/* pad short packets */
-#define E1000_TCTL_CT     0x00000ff0	/* collision threshold */
-#define E1000_TCTL_COLD   0x003ff000	/* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000	/* SW Xoff transmission */
-#define E1000_TCTL_PBE    0x00800000	/* Packet Burst Enable */
-#define E1000_TCTL_RTLC   0x01000000	/* Re-transmit on late collision */
-#define E1000_TCTL_NRTU   0x02000000	/* No Re-transmit on underrun */
-
-/* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF	/* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL     0x00000100	/* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL     0x00000200	/* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL   0x00000400	/* IPv6 checksum offload */
-
-/* Definitions for power management and wakeup registers */
-/* Wake Up Control */
-#define E1000_WUC_APME       0x00000001	/* APM Enable */
-#define E1000_WUC_PME_EN     0x00000002	/* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004	/* PME Status */
-#define E1000_WUC_APMPME     0x00000008	/* Assert PME on APM Wakeup */
-
-/* Wake Up Filter Control */
-#define E1000_WUFC_LNKC 0x00000001	/* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG  0x00000002	/* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX   0x00000004	/* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC   0x00000008	/* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC   0x00000010	/* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP  0x00000020	/* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4 0x00000040	/* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080	/* Directed IPv6 Packet Wakeup Enable */
-#define E1000_WUFC_FLX0 0x00010000	/* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000	/* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000	/* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000	/* Flexible Filter 3 Enable */
-#define E1000_WUFC_ALL_FILTERS 0x000F00FF	/* Mask for all wakeup filters */
-#define E1000_WUFC_FLX_OFFSET 16	/* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS 0x000F0000	/* Mask for the 4 flexible filters */
-
-/* Wake Up Status */
-#define E1000_WUS_LNKC 0x00000001	/* Link Status Changed */
-#define E1000_WUS_MAG  0x00000002	/* Magic Packet Received */
-#define E1000_WUS_EX   0x00000004	/* Directed Exact Received */
-#define E1000_WUS_MC   0x00000008	/* Directed Multicast Received */
-#define E1000_WUS_BC   0x00000010	/* Broadcast Received */
-#define E1000_WUS_ARP  0x00000020	/* ARP Request Packet Received */
-#define E1000_WUS_IPV4 0x00000040	/* Directed IPv4 Packet Wakeup Received */
-#define E1000_WUS_IPV6 0x00000080	/* Directed IPv6 Packet Wakeup Received */
-#define E1000_WUS_FLX0 0x00010000	/* Flexible Filter 0 Match */
-#define E1000_WUS_FLX1 0x00020000	/* Flexible Filter 1 Match */
-#define E1000_WUS_FLX2 0x00040000	/* Flexible Filter 2 Match */
-#define E1000_WUS_FLX3 0x00080000	/* Flexible Filter 3 Match */
-#define E1000_WUS_FLX_FILTERS 0x000F0000	/* Mask for the 4 flexible filters */
-
-/* Management Control */
-#define E1000_MANC_SMBUS_EN      0x00000001	/* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN        0x00000002	/* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE    0x00000004	/* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN       0x00000100	/* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN       0x00000200	/* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN       0x00000400	/* Enable IPv4 */
-#define E1000_MANC_IPV6_EN       0x00000800	/* Enable IPv6 */
-#define E1000_MANC_SNAP_EN       0x00001000	/* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN        0x00002000	/* Enable ARP Request Filtering */
-#define E1000_MANC_NEIGHBOR_EN   0x00004000	/* Enable Neighbor Discovery
-						 * Filtering */
-#define E1000_MANC_TCO_RESET     0x00010000	/* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN    0x00020000	/* Receive TCO Packets Enabled */
-#define E1000_MANC_REPORT_STATUS 0x00040000	/* Status Reporting Enabled */
-#define E1000_MANC_SMB_REQ       0x01000000	/* SMBus Request */
-#define E1000_MANC_SMB_GNT       0x02000000	/* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN    0x04000000	/* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN   0x08000000	/* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT  0x10000000	/* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT   0x20000000	/* SMBus Clock Out */
-
-#define E1000_MANC_SMB_DATA_OUT_SHIFT  28	/* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT   29	/* SMBus Clock Out Shift */
-
-/* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF	/* Only the lower 12 bits are valid */
-
-#define E1000_MDALIGN          4096
-
-/* EEPROM Commands */
-#define EEPROM_READ_OPCODE  0x6	/* EERPOM read opcode */
-#define EEPROM_WRITE_OPCODE 0x5	/* EERPOM write opcode */
-#define EEPROM_ERASE_OPCODE 0x7	/* EERPOM erase opcode */
-#define EEPROM_EWEN_OPCODE  0x13	/* EERPOM erase/write enable */
-#define EEPROM_EWDS_OPCODE  0x10	/* EERPOM erast/write disable */
-
-/* EEPROM Word Offsets */
-#define EEPROM_COMPAT              0x0003
-#define EEPROM_ID_LED_SETTINGS     0x0004
-#define EEPROM_INIT_CONTROL1_REG   0x000A
-#define EEPROM_INIT_CONTROL2_REG   0x000F
-#define EEPROM_FLASH_VERSION       0x0032
-#define EEPROM_CHECKSUM_REG        0x003F
-
-/* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_0000 0x0000
-#define ID_LED_RESERVED_FFFF 0xFFFF
-#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
-			      (ID_LED_OFF1_OFF2 << 8) | \
-			      (ID_LED_DEF1_DEF2 << 4) | \
-			      (ID_LED_DEF1_DEF2))
-#define ID_LED_DEF1_DEF2     0x1
-#define ID_LED_DEF1_ON2      0x2
-#define ID_LED_DEF1_OFF2     0x3
-#define ID_LED_ON1_DEF2      0x4
-#define ID_LED_ON1_ON2       0x5
-#define ID_LED_ON1_OFF2      0x6
-#define ID_LED_OFF1_DEF2     0x7
-#define ID_LED_OFF1_ON2      0x8
-#define ID_LED_OFF1_OFF2     0x9
-
-/* Mask bits for fields in Word 0x03 of the EEPROM */
-#define EEPROM_COMPAT_SERVER 0x0400
-#define EEPROM_COMPAT_CLIENT 0x0200
-
-/* Mask bits for fields in Word 0x0a of the EEPROM */
-#define EEPROM_WORD0A_ILOS   0x0010
-#define EEPROM_WORD0A_SWDPIO 0x01E0
-#define EEPROM_WORD0A_LRST   0x0200
-#define EEPROM_WORD0A_FD     0x0400
-#define EEPROM_WORD0A_66MHZ  0x0800
-
-/* Mask bits for fields in Word 0x0f of the EEPROM */
-#define EEPROM_WORD0F_PAUSE_MASK 0x3000
-#define EEPROM_WORD0F_PAUSE      0x1000
-#define EEPROM_WORD0F_ASM_DIR    0x2000
-#define EEPROM_WORD0F_ANE        0x0800
-#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
-
-/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
-#define EEPROM_SUM 0xBABA
-
-/* EEPROM Map defines (WORD OFFSETS)*/
-#define EEPROM_NODE_ADDRESS_BYTE_0 0
-#define EEPROM_PBA_BYTE_1          8
-
-/* EEPROM Map Sizes (Byte Counts) */
-#define PBA_SIZE 4
-
-/* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD       16
-#define E1000_CT_SHIFT                  4
-#define E1000_COLLISION_DISTANCE        64
-#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
-#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
-#define E1000_GB_HDX_COLLISION_DISTANCE 512
-#define E1000_COLD_SHIFT                12
-
-/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
-#define REQ_TX_DESCRIPTOR_MULTIPLE  8
-#define REQ_RX_DESCRIPTOR_MULTIPLE  8
-
-/* Default values for the transmit IPG register */
-#define DEFAULT_82542_TIPG_IPGT        10
-#define DEFAULT_82543_TIPG_IPGT_FIBER  9
-#define DEFAULT_82543_TIPG_IPGT_COPPER 8
-
-#define E1000_TIPG_IPGT_MASK  0x000003FF
-#define E1000_TIPG_IPGR1_MASK 0x000FFC00
-#define E1000_TIPG_IPGR2_MASK 0x3FF00000
-
-#define DEFAULT_82542_TIPG_IPGR1 2
-#define DEFAULT_82543_TIPG_IPGR1 8
-#define E1000_TIPG_IPGR1_SHIFT  10
-
-#define DEFAULT_82542_TIPG_IPGR2 10
-#define DEFAULT_82543_TIPG_IPGR2 6
-#define E1000_TIPG_IPGR2_SHIFT  20
-
-#define E1000_TXDMAC_DPP 0x00000001
-
-/* Adaptive IFS defines */
-#define TX_THRESHOLD_START     8
-#define TX_THRESHOLD_INCREMENT 10
-#define TX_THRESHOLD_DECREMENT 1
-#define TX_THRESHOLD_STOP      190
-#define TX_THRESHOLD_DISABLE   0
-#define TX_THRESHOLD_TIMER_MS  10000
-#define MIN_NUM_XMITS          1000
-#define IFS_MAX                80
-#define IFS_STEP               10
-#define IFS_MIN                40
-#define IFS_RATIO              4
-
-/* PBA constants */
-#define E1000_PBA_16K 0x0010	/* 16KB, default TX allocation */
-#define E1000_PBA_24K 0x0018
-#define E1000_PBA_40K 0x0028
-#define E1000_PBA_48K 0x0030	/* 48KB, default RX allocation */
-
-/* Flow Control Constants */
-#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
-#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
-#define FLOW_CONTROL_TYPE         0x8808
-
-/* The historical defaults for the flow control values are given below. */
-#define FC_DEFAULT_HI_THRESH        (0x8000)	/* 32KB */
-#define FC_DEFAULT_LO_THRESH        (0x4000)	/* 16KB */
-#define FC_DEFAULT_TX_TIMER         (0x100)	/* ~130 us */
-
-/* Flow Control High-Watermark: 43464 bytes */
-#define E1000_FC_HIGH_THRESH 0xA9C8
-/* Flow Control Low-Watermark: 43456 bytes */
-#define E1000_FC_LOW_THRESH 0xA9C0
-/* Flow Control Pause Time: 858 usec */
-#define E1000_FC_PAUSE_TIME 0x0680
-
-/* PCIX Config space */
-#define PCIX_COMMAND_REGISTER    0xE6
-#define PCIX_STATUS_REGISTER_LO  0xE8
-#define PCIX_STATUS_REGISTER_HI  0xEA
-
-#define PCIX_COMMAND_MMRBC_MASK      0x000C
-#define PCIX_COMMAND_MMRBC_SHIFT     0x2
-#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
-#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
-#define PCIX_STATUS_HI_MMRBC_4K      0x3
-#define PCIX_STATUS_HI_MMRBC_2K      0x2
-
-/* The number of bits that we need to shift right to move the "pause"
- * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
- * in the TXCW register
- */
-#define PAUSE_SHIFT 5
-
-/* The number of bits that we need to shift left to move the "SWDPIO"
- * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
- * in the CTRL register
- */
-#define SWDPIO_SHIFT 17
-
-/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
- * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
- * Extended CTRL register.
- * in the CTRL register
- */
-#define SWDPIO__EXT_SHIFT 4
-
-/* The number of bits that we need to shift left to move the "ILOS"
- * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
- * in the CTRL register
- */
-#define ILOS_SHIFT  3
-
-#define RECEIVE_BUFFER_ALIGN_SIZE  (256)
-
-/* The number of milliseconds we wait for auto-negotiation to complete */
-#define LINK_UP_TIMEOUT             500
-
-#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
-
-/* The carrier extension symbol, as received by the NIC. */
-#define CARRIER_EXTENSION   0x0F
-
-/* TBI_ACCEPT macro definition:
- *
- * This macro requires:
- *      adapter = a pointer to struct e1000_hw
- *      status = the 8 bit status field of the RX descriptor with EOP set
- *      error = the 8 bit error field of the RX descriptor with EOP set
- *      length = the sum of all the length fields of the RX descriptors that
- *               make up the current frame
- *      last_byte = the last byte of the frame DMAed by the hardware
- *      max_frame_length = the maximum frame length we want to accept.
- *      min_frame_length = the minimum frame length we want to accept.
- *
- * This macro is a conditional that should be used in the interrupt
- * handler's Rx processing routine when RxErrors have been detected.
- *
- * Typical use:
- *  ...
- *  if (TBI_ACCEPT) {
- *      accept_frame = TRUE;
- *      e1000_tbi_adjust_stats(adapter, MacAddress);
- *      frame_length--;
- *  } else {
- *      accept_frame = FALSE;
- *  }
- *  ...
- */
-
-#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
-    ((adapter)->tbi_compatibility_on && \
-     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
-     ((last_byte) == CARRIER_EXTENSION) && \
-     (((status) & E1000_RXD_STAT_VP) ? \
-	  (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
-	   ((length) <= ((adapter)->max_frame_size + 1))) : \
-	  (((length) > (adapter)->min_frame_size) && \
-	   ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
-
-/* Structures, enums, and macros for the PHY */
-
-/* Bit definitions for the Management Data IO (MDIO) and Management Data
- * Clock (MDC) pins in the Device Control Register.
- */
-#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
-#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
-#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
-#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
-#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
-
-/* PHY 1000 MII Register/Bit Definitions */
-/* PHY Registers defined by IEEE */
-#define PHY_CTRL         0x00	/* Control Register */
-#define PHY_STATUS       0x01	/* Status Regiser */
-#define PHY_ID1          0x02	/* Phy Id Reg (word 1) */
-#define PHY_ID2          0x03	/* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV  0x04	/* Autoneg Advertisement */
-#define PHY_LP_ABILITY   0x05	/* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP  0x06	/* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07	/* Next Page TX */
-#define PHY_LP_NEXT_PAGE 0x08	/* Link Partner Next Page */
-#define PHY_1000T_CTRL   0x09	/* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A	/* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS   0x0F	/* Extended Status Reg */
-
-/* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL     0x10	/* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS   0x11	/* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE        0x12	/* Interrupt Enable Register */
-#define M88E1000_INT_STATUS        0x13	/* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14	/* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR       0x15	/* Receive Error Counter */
-
-#define MAX_PHY_REG_ADDRESS 0x1F	/* 5 bit address bus (0-0x1F) */
-
-/* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040	/* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080	/* Collision test enable */
-#define MII_CR_FULL_DUPLEX      0x0100	/* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200	/* Restart auto negotiation */
-#define MII_CR_ISOLATE          0x0400	/* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN       0x0800	/* Power down */
-#define MII_CR_AUTO_NEG_EN      0x1000	/* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000	/* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK         0x4000	/* 0 = normal, 1 = loopback */
-#define MII_CR_RESET            0x8000	/* 0 = normal, 1 = PHY reset */
-
-/* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS     0x0001	/* Extended register capabilities */
-#define MII_SR_JABBER_DETECT     0x0002	/* Jabber Detected */
-#define MII_SR_LINK_STATUS       0x0004	/* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS      0x0008	/* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT      0x0010	/* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE  0x0020	/* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040	/* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS   0x0100	/* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS     0x0200	/* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS     0x0400	/* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS       0x0800	/* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS       0x1000	/* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS      0x2000	/* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS      0x4000	/* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS        0x8000	/* 100T4 Capable */
-
-/* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD 0x0001	/* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS    0x0020	/* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS    0x0040	/* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS  0x0080	/* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS  0x0100	/* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS     0x0200	/* 100T4 Capable */
-#define NWAY_AR_PAUSE          0x0400	/* Pause operation desired */
-#define NWAY_AR_ASM_DIR        0x0800	/* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT   0x2000	/* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE      0x8000	/* Next Page ability supported */
-
-/* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000	/* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS    0x0020	/* LP is 10T   Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS    0x0040	/* LP is 10T   Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS  0x0080	/* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS  0x0100	/* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS     0x0200	/* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE          0x0400	/* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR        0x0800	/* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT   0x2000	/* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE    0x4000	/* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE      0x8000	/* Next Page ability supported */
-
-/* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS      0x0001	/* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD          0x0002	/* LP is 10T   Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS    0x0004	/* LP is 10T   Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008	/* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT  0x0100	/* LP is 100TX Full Duplex Capable */
-
-/* Next Page TX Register */
-#define NPTX_MSG_CODE_FIELD 0x0001	/* NP msg code or unformatted data */
-#define NPTX_TOGGLE         0x0800	/* Toggles between exchanges
-					 * of different NP
-					 */
-#define NPTX_ACKNOWLDGE2    0x1000	/* 1 = will comply with msg
-					 * 0 = cannot comply with msg
-					 */
-#define NPTX_MSG_PAGE       0x2000	/* formatted(1)/unformatted(0) pg */
-#define NPTX_NEXT_PAGE      0x8000	/* 1 = addition NP will follow
-					 * 0 = sending last NP
-					 */
-
-/* Link Partner Next Page Register */
-#define LP_RNPR_MSG_CODE_FIELD 0x0001	/* NP msg code or unformatted data */
-#define LP_RNPR_TOGGLE         0x0800	/* Toggles between exchanges
-					 * of different NP
-					 */
-#define LP_RNPR_ACKNOWLDGE2    0x1000	/* 1 = will comply with msg
-					 * 0 = cannot comply with msg
-					 */
-#define LP_RNPR_MSG_PAGE       0x2000	/* formatted(1)/unformatted(0) pg */
-#define LP_RNPR_ACKNOWLDGE     0x4000	/* 1 = ACK / 0 = NO ACK */
-#define LP_RNPR_NEXT_PAGE      0x8000	/* 1 = addition NP will follow
-					 * 0 = sending last NP
-					 */
-
-/* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE      0x0080	/* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS         0x0100	/* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS         0x0200	/* Advertise 1000T FD capability  */
-#define CR_1000T_REPEATER_DTE    0x0400	/* 1=Repeater/switch device port */
-					/* 0=DTE device */
-#define CR_1000T_MS_VALUE        0x0800	/* 1=Configure PHY as Master */
-					/* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE       0x1000	/* 1=Master/Slave manual config value */
-					/* 0=Automatic Master/Slave config */
-#define CR_1000T_TEST_MODE_NORMAL 0x0000	/* Normal Operation */
-#define CR_1000T_TEST_MODE_1     0x2000	/* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2     0x4000	/* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3     0x6000	/* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4     0x8000	/* Transmitter Distortion test */
-
-/* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT   0x00FF	/* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR   0x0100	/* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS       0x0400	/* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS       0x0800	/* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000	/* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS  0x2000	/* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES    0x4000	/* 1=Local TX is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT  0x8000	/* Master/Slave config fault */
-#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
-#define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
-
-/* Extended Status Register */
-#define IEEE_ESR_1000T_HD_CAPS 0x1000	/* 1000T HD capable */
-#define IEEE_ESR_1000T_FD_CAPS 0x2000	/* 1000T FD capable */
-#define IEEE_ESR_1000X_HD_CAPS 0x4000	/* 1000X HD capable */
-#define IEEE_ESR_1000X_FD_CAPS 0x8000	/* 1000X FD capable */
-
-#define PHY_TX_POLARITY_MASK   0x0100	/* register 10h bit 8 (polarity bit) */
-#define PHY_TX_NORMAL_POLARITY 0	/* register 10h bit 8 (normal polarity) */
-
-#define AUTO_POLARITY_DISABLE  0x0010	/* register 11h bit 4 */
-				      /* (0=enable, 1=disable) */
-
-/* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE    0x0001	/* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002	/* 1=Polarity Reversal enabled */
-#define M88E1000_PSCR_SQE_TEST          0x0004	/* 1=SQE Test enabled */
-#define M88E1000_PSCR_CLK125_DISABLE    0x0010	/* 1=CLK125 low,
-						 * 0=CLK125 toggling
-						 */
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000	/* MDI Crossover Mode bits 6:5 */
-					       /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020	/* Manual MDIX configuration */
-#define M88E1000_PSCR_AUTO_X_1000T     0x0040	/* 1000BASE-T: Auto crossover,
-						 *  100BASE-TX/10BASE-T:
-						 *  MDI Mode
-						 */
-#define M88E1000_PSCR_AUTO_X_MODE      0x0060	/* Auto crossover enabled
-						 * all speeds.
-						 */
-#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
-					/* 1=Enable Extended 10BASE-T distance
-					 * (Lower 10BASE-T RX Threshold)
-					 * 0=Normal 10BASE-T RX Threshold */
-#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
-					/* 1=5-Bit interface in 100BASE-TX
-					 * 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200	/* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400	/* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800	/* 1=Assert CRS on Transmit */
-
-#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
-#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
-#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
-
-/* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER             0x0001	/* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY       0x0002	/* 1=Polarity reversed */
-#define M88E1000_PSSR_MDIX               0x0040	/* 1=MDIX; 0=MDI */
-#define M88E1000_PSSR_CABLE_LENGTH       0x0380	/* 0=<50M;1=50-80M;2=80-110M;
-						   * 3=110-140M;4=>140M */
-#define M88E1000_PSSR_LINK               0x0400	/* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800	/* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD          0x1000	/* 1=Page received */
-#define M88E1000_PSSR_DPLX               0x2000	/* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED              0xC000	/* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS              0x0000	/* 00=10Mbs */
-#define M88E1000_PSSR_100MBS             0x4000	/* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS            0x8000	/* 10=1000Mbs */
-
-#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
-#define M88E1000_PSSR_MDIX_SHIFT         6
-#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
-
-/* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000	/* 1=Fiber loopback */
-#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000	/* 1=Lost lock detect enabled.
-						 * Will assert lost lock and bring
-						 * link down if idle not seen
-						 * within 1ms in 1000BASE-T
-						 */
-/* Number of times we will attempt to autonegotiate before downshifting if we
- * are the master */
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
-/* Number of times we will attempt to autonegotiate before downshifting if we
- * are the slave */
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5     0x0060	/* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25      0x0070	/* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0       0x0000	/* NO  TX_CLK */
-
-/* Bit definitions for valid PHY IDs. */
-#define M88E1000_E_PHY_ID  0x01410C50
-#define M88E1000_I_PHY_ID  0x01410C30
-#define M88E1011_I_PHY_ID  0x01410C20
-#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
-#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
-
-/* Miscellaneous PHY bit definitions. */
-#define PHY_PREAMBLE        0xFFFFFFFF
-#define PHY_SOF             0x01
-#define PHY_OP_READ         0x02
-#define PHY_OP_WRITE        0x01
-#define PHY_TURNAROUND      0x02
-#define PHY_PREAMBLE_SIZE   32
-#define MII_CR_SPEED_1000   0x0040
-#define MII_CR_SPEED_100    0x2000
-#define MII_CR_SPEED_10     0x0000
-#define E1000_PHY_ADDRESS   0x01
-#define PHY_AUTO_NEG_TIME   45	/* 4.5 Seconds */
-#define PHY_FORCE_TIME      20	/* 2.0 Seconds */
-#define PHY_REVISION_MASK   0xFFFFFFF0
-#define DEVICE_SPEED_MASK   0x00000300	/* Device Ctrl Reg Speed Mask */
-#define REG4_SPEED_MASK     0x01E0
-#define REG9_SPEED_MASK     0x0300
-#define ADVERTISE_10_HALF   0x0001
-#define ADVERTISE_10_FULL   0x0002
-#define ADVERTISE_100_HALF  0x0004
-#define ADVERTISE_100_FULL  0x0008
-#define ADVERTISE_1000_HALF 0x0010
-#define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F	/* Everything but 1000-Half */
-
-#endif				/* _E1000_HW_H_ */
diff --git a/drivers/net/ether_85xx.c b/drivers/net/ether_85xx.c
deleted file mode 100644
index 128fc3173b..0000000000
--- a/drivers/net/ether_85xx.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * MPC8560 FCC Fast Ethernet
- * Copyright (c) 2003 Motorola,Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * MPC8560 FCC Fast Ethernet
- * Basic ET HW initialization and packet RX/TX routines
- *
- * This code will not perform the IO port configuration. This should be
- * done in the iop_conf_t structure specific for the board.
- *
- * TODO:
- * add a PHY driver to do the negotiation
- * reflect negotiation results in FPSMR
- * look for ways to configure the board specific stuff elsewhere, eg.
- *    config_xxx.h or the board directory
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/cpm_85xx.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-#if defined(CONFIG_CPM2)
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
-	defined(CONFIG_NET_MULTI)
-
-static struct ether_fcc_info_s
-{
-	int ether_index;
-	int proff_enet;
-	ulong cpm_cr_enet_sblock;
-	ulong cpm_cr_enet_page;
-	ulong cmxfcr_mask;
-	ulong cmxfcr_value;
-}
-	ether_fcc_info[] =
-{
-#ifdef CONFIG_ETHER_ON_FCC1
-{
-	0,
-	PROFF_FCC1,
-	CPM_CR_FCC1_SBLOCK,
-	CPM_CR_FCC1_PAGE,
-	CFG_CMXFCR_MASK1,
-	CFG_CMXFCR_VALUE1
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC2
-{
-	1,
-	PROFF_FCC2,
-	CPM_CR_FCC2_SBLOCK,
-	CPM_CR_FCC2_PAGE,
-	CFG_CMXFCR_MASK2,
-	CFG_CMXFCR_VALUE2
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC3
-{
-	2,
-	PROFF_FCC3,
-	CPM_CR_FCC3_SBLOCK,
-	CPM_CR_FCC3_PAGE,
-	CFG_CMXFCR_MASK3,
-	CFG_CMXFCR_VALUE3
-},
-#endif
-};
-
-/*---------------------------------------------------------------------*/
-
-/* Maximum input DMA size.  Must be a should(?) be a multiple of 4. */
-#define PKT_MAXDMA_SIZE         1520
-
-/* The FCC stores dest/src/type, data, and checksum for receive packets. */
-#define PKT_MAXBUF_SIZE         1518
-#define PKT_MINBUF_SIZE         64
-
-/* Maximum input buffer size.  Must be a multiple of 32. */
-#define PKT_MAXBLR_SIZE         1536
-
-#define TOUT_LOOP 1000000
-
-#define TX_BUF_CNT 2
-
-static uint rxIdx;	/* index of the current RX buffer */
-static uint txIdx;	/* index of the current TX buffer */
-
-/*
- * FCC Ethernet Tx and Rx buffer descriptors.
- * Provide for Double Buffering
- * Note: PKTBUFSRX is defined in net.h
- */
-
-typedef volatile struct rtxbd {
-    cbd_t rxbd[PKTBUFSRX];
-    cbd_t txbd[TX_BUF_CNT];
-} RTXBD;
-
-/*  Good news: the FCC supports external BDs! */
-#ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
-#else
-#error "rtx must be 64-bit aligned"
-#endif
-
-#undef ET_DEBUG
-
-static int fec_send(struct eth_device* dev, volatile void *packet, int length)
-{
-    int i = 0;
-    int result = 0;
-
-    if (length <= 0) {
-	printf("fec: bad packet size: %d\n", length);
-	goto out;
-    }
-
-    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    printf("fec: tx buffer not ready\n");
-	    goto out;
-	}
-    }
-
-    rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
-    rtx.txbd[txIdx].cbd_datlen = length;
-    rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
-			       BD_ENET_TX_TC | BD_ENET_TX_PAD);
-
-    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    printf("fec: tx error\n");
-	    goto out;
-	}
-    }
-
-#ifdef ET_DEBUG
-    printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
-    printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
-    for(i=0;i<(length/16 + 1);i++) {
-	 printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
-    *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
-    *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
-    }
-#endif
-
-    /* return only status bits */
-    result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
-    txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-out:
-    return result;
-}
-
-static int fec_recv(struct eth_device* dev)
-{
-    int length;
-
-    for (;;)
-    {
-	if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-	    length = -1;
-	    break;     /* nothing received - leave for() loop */
-	}
-	length = rtx.rxbd[rxIdx].cbd_datlen;
-
-	if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
-	    printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
-	}
-	else {
-	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
-	}
-
-
-	/* Give the buffer back to the FCC. */
-	rtx.rxbd[rxIdx].cbd_datlen = 0;
-
-	/* wrap around buffer index when necessary */
-	if ((rxIdx + 1) >= PKTBUFSRX) {
-	    rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-	    rxIdx = 0;
-	}
-	else {
-	    rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-	    rxIdx++;
-	}
-    }
-    return length;
-}
-
-
-static int fec_init(struct eth_device* dev, bd_t *bis)
-{
-    struct ether_fcc_info_s * info = dev->priv;
-    int i;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
-    fcc_enet_t *pram_ptr;
-    unsigned long mem_addr;
-
-
-    /* 28.9 - (1-2): ioports have been set up already */
-
-    /* 28.9 - (3): connect FCC's tx and rx clocks */
-    immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
-    immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
-							info->cmxfcr_value;
-
-    /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
-    if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-    } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-    } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-    }
-
-    /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
-    if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
-    } else if (info->ether_index == 1){
-	immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
-    } else if (info->ether_index == 2){
-	immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
-    }
-
-    /* 28.9 - (6): FDSR: Ethernet Syn */
-    if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
-    } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
-    } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
-    }
-
-    /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
-    rxIdx = 0;
-    txIdx = 0;
-
-    /* Setup Receiver Buffer Descriptors */
-    for (i = 0; i < PKTBUFSRX; i++)
-    {
-      rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-      rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
-    }
-    rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-    /* Setup Ethernet Transmitter Buffer Descriptors */
-    for (i = 0; i < TX_BUF_CNT; i++)
-    {
-      rtx.txbd[i].cbd_sc = 0;
-      rtx.txbd[i].cbd_datlen = 0;
-      rtx.txbd[i].cbd_bufaddr = 0;
-    }
-    rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-    /* 28.9 - (7): initialize parameter ram */
-    pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
-
-    /* clear whole structure to make sure all reserved fields are zero */
-    memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
-
-    /*
-     * common Parameter RAM area
-     *
-     * Allocate space in the reserved FCC area of DPRAM for the
-     * internal buffers.  No one uses this space (yet), so we
-     * can do this.  Later, we will add resource management for
-     * this area.
-     * CPM_FCC_SPECIAL_BASE:	0xB000 for MPC8540, MPC8560
-     *				0x9000 for MPC8541, MPC8555
-     */
-    mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
-    pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
-    pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
-    /*
-     * Set maximum bytes per receive buffer.
-     * It must be a multiple of 32.
-     */
-    pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
-    /* localbus SDRAM should be preferred */
-    pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CFG_CPMFCR_RAMTYPE) << 24;
-    pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
-    pram_ptr->fen_genfcc.fcc_rbdstat = 0;
-    pram_ptr->fen_genfcc.fcc_rbdlen = 0;
-    pram_ptr->fen_genfcc.fcc_rdptr = 0;
-    /* localbus SDRAM should be preferred */
-    pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CFG_CPMFCR_RAMTYPE) << 24;
-    pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
-    pram_ptr->fen_genfcc.fcc_tbdstat = 0;
-    pram_ptr->fen_genfcc.fcc_tbdlen = 0;
-    pram_ptr->fen_genfcc.fcc_tdptr = 0;
-
-    /* protocol-specific area */
-    pram_ptr->fen_statbuf = 0x0;
-    pram_ptr->fen_cmask = 0xdebb20e3;	/* CRC mask */
-    pram_ptr->fen_cpres = 0xffffffff;	/* CRC preset */
-    pram_ptr->fen_crcec = 0;
-    pram_ptr->fen_alec = 0;
-    pram_ptr->fen_disfc = 0;
-    pram_ptr->fen_retlim = 15;		/* Retry limit threshold */
-    pram_ptr->fen_retcnt = 0;
-    pram_ptr->fen_pper = 0;
-    pram_ptr->fen_boffcnt = 0;
-    pram_ptr->fen_gaddrh = 0;
-    pram_ptr->fen_gaddrl = 0;
-    pram_ptr->fen_mflr = PKT_MAXBUF_SIZE;   /* maximum frame length register */
-    /*
-     * Set Ethernet station address.
-     *
-     * This is supplied in the board information structure, so we
-     * copy that into the controller.
-     * So far we have only been given one Ethernet address. We make
-     * it unique by setting a few bits in the upper byte of the
-     * non-static part of the address.
-     */
-#define ea eth_get_dev()->enetaddr
-    pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
-    pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
-    pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
-    pram_ptr->fen_ibdcount = 0;
-    pram_ptr->fen_ibdstart = 0;
-    pram_ptr->fen_ibdend = 0;
-    pram_ptr->fen_txlen = 0;
-    pram_ptr->fen_iaddrh = 0;  /* disable hash */
-    pram_ptr->fen_iaddrl = 0;
-    pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
-    /* pad pointer. use tiptr since we don't need a specific padding char */
-    pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
-    pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE;	/* maximum DMA1 length:1520 */
-    pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE;	/* maximum DMA2 length:1520 */
-
-#if defined(ET_DEBUG)
-    printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
-    printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
-	pram_ptr->fen_genfcc.fcc_rbase);
-    printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
-	pram_ptr->fen_genfcc.fcc_tbase);
-#endif
-
-    /* 28.9 - (8)(9): clear out events in FCCE */
-    /* 28.9 - (9): FCCM: mask all events */
-    if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
-	immr->im_cpm.im_cpm_fcc1.fccm = 0;
-    } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
-	immr->im_cpm.im_cpm_fcc2.fccm = 0;
-    } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
-	immr->im_cpm.im_cpm_fcc3.fccm = 0;
-    }
-
-    /* 28.9 - (10-12): we don't use ethernet interrupts */
-
-    /* 28.9 - (13)
-     *
-     * Let's re-initialize the channel now.  We have to do it later
-     * than the manual describes because we have just now finished
-     * the BD initialization.
-     */
-    cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
-			    info->cpm_cr_enet_sblock,
-			    0x0c,
-			    CPM_CR_INIT_TRX) | CPM_CR_FLG;
-    do {
-	__asm__ __volatile__ ("eieio");
-    } while (cp->cpcr & CPM_CR_FLG);
-
-    /* 28.9 - (14): enable tx/rx in gfmr */
-    if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-    } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-    } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-    }
-
-    return 1;
-}
-
-static void fec_halt(struct eth_device* dev)
-{
-    struct ether_fcc_info_s * info = dev->priv;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
-    /* write GFMR: disable tx/rx */
-    if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-    } else if(info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-    } else if(info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-    }
-}
-
-int fec_initialize(bd_t *bis)
-{
-	struct eth_device* dev;
-	int i;
-
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
-	{
-		dev = (struct eth_device*) malloc(sizeof *dev);
-		memset(dev, 0, sizeof *dev);
-
-		sprintf(dev->name, "FCC%d ETHERNET",
-			ether_fcc_info[i].ether_index + 1);
-		dev->priv   = &ether_fcc_info[i];
-		dev->init   = fec_init;
-		dev->halt   = fec_halt;
-		dev->send   = fec_send;
-		dev->recv   = fec_recv;
-
-		eth_register(dev);
-
-#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
-		&& defined(CONFIG_BITBANGMII)
-		miiphy_register(dev->name,
-				bb_miiphy_read,	bb_miiphy_write);
-#endif
-	}
-
-	return 1;
-}
-
-#endif	/* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
-
-#endif /* CONFIG_CPM2 */
diff --git a/drivers/net/ether_fcc.c b/drivers/net/ether_fcc.c
deleted file mode 100644
index f4712ab62e..0000000000
--- a/drivers/net/ether_fcc.c
+++ /dev/null
@@ -1,1167 +0,0 @@
-/*
- * MPC8260 FCC Fast Ethernet
- *
- * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * MPC8260 FCC Fast Ethernet
- * Basic ET HW initialization and packet RX/TX routines
- *
- * This code will not perform the IO port configuration. This should be
- * done in the iop_conf_t structure specific for the board.
- *
- * TODO:
- * add a PHY driver to do the negotiation
- * reflect negotiation results in FPSMR
- * look for ways to configure the board specific stuff elsewhere, eg.
- *    config_xxx.h or the board directory
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/cpm_8260.h>
-#include <mpc8260.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
-	defined(CONFIG_NET_MULTI)
-
-static struct ether_fcc_info_s
-{
-	int ether_index;
-	int proff_enet;
-	ulong cpm_cr_enet_sblock;
-	ulong cpm_cr_enet_page;
-	ulong cmxfcr_mask;
-	ulong cmxfcr_value;
-}
-	ether_fcc_info[] =
-{
-#ifdef CONFIG_ETHER_ON_FCC1
-{
-	0,
-	PROFF_FCC1,
-	CPM_CR_FCC1_SBLOCK,
-	CPM_CR_FCC1_PAGE,
-	CFG_CMXFCR_MASK1,
-	CFG_CMXFCR_VALUE1
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC2
-{
-	1,
-	PROFF_FCC2,
-	CPM_CR_FCC2_SBLOCK,
-	CPM_CR_FCC2_PAGE,
-	CFG_CMXFCR_MASK2,
-	CFG_CMXFCR_VALUE2
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC3
-{
-	2,
-	PROFF_FCC3,
-	CPM_CR_FCC3_SBLOCK,
-	CPM_CR_FCC3_PAGE,
-	CFG_CMXFCR_MASK3,
-	CFG_CMXFCR_VALUE3
-},
-#endif
-};
-
-/*---------------------------------------------------------------------*/
-
-/* Maximum input DMA size.  Must be a should(?) be a multiple of 4. */
-#define PKT_MAXDMA_SIZE         1520
-
-/* The FCC stores dest/src/type, data, and checksum for receive packets. */
-#define PKT_MAXBUF_SIZE         1518
-#define PKT_MINBUF_SIZE         64
-
-/* Maximum input buffer size.  Must be a multiple of 32. */
-#define PKT_MAXBLR_SIZE         1536
-
-#define TOUT_LOOP 1000000
-
-#define TX_BUF_CNT 2
-#ifdef __GNUC__
-static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
-#else
-#error "txbuf must be 64-bit aligned"
-#endif
-
-static uint rxIdx;	/* index of the current RX buffer */
-static uint txIdx;	/* index of the current TX buffer */
-
-/*
- * FCC Ethernet Tx and Rx buffer descriptors.
- * Provide for Double Buffering
- * Note: PKTBUFSRX is defined in net.h
- */
-
-typedef volatile struct rtxbd {
-    cbd_t rxbd[PKTBUFSRX];
-    cbd_t txbd[TX_BUF_CNT];
-} RTXBD;
-
-/*  Good news: the FCC supports external BDs! */
-#ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
-#else
-#error "rtx must be 64-bit aligned"
-#endif
-
-static int fec_send(struct eth_device* dev, volatile void *packet, int length)
-{
-    int i;
-    int result = 0;
-
-    if (length <= 0) {
-	printf("fec: bad packet size: %d\n", length);
-	goto out;
-    }
-
-    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    puts ("fec: tx buffer not ready\n");
-	    goto out;
-	}
-    }
-
-    rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
-    rtx.txbd[txIdx].cbd_datlen = length;
-    rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
-			       BD_ENET_TX_WRAP);
-
-    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    puts ("fec: tx error\n");
-	    goto out;
-	}
-    }
-
-#ifdef ET_DEBUG
-    printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
-#endif
-
-    /* return only status bits */
-    result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
-
-out:
-    return result;
-}
-
-static int fec_recv(struct eth_device* dev)
-{
-    int length;
-
-    for (;;)
-    {
-	if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-	    length = -1;
-	    break;     /* nothing received - leave for() loop */
-	}
-	length = rtx.rxbd[rxIdx].cbd_datlen;
-
-	if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
-	    printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
-	}
-	else {
-	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
-	}
-
-
-	/* Give the buffer back to the FCC. */
-	rtx.rxbd[rxIdx].cbd_datlen = 0;
-
-	/* wrap around buffer index when necessary */
-	if ((rxIdx + 1) >= PKTBUFSRX) {
-	    rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-	    rxIdx = 0;
-	}
-	else {
-	    rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-	    rxIdx++;
-	}
-    }
-    return length;
-}
-
-
-static int fec_init(struct eth_device* dev, bd_t *bis)
-{
-    struct ether_fcc_info_s * info = dev->priv;
-    int i;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile cpm8260_t *cp = &(immr->im_cpm);
-    fcc_enet_t *pram_ptr;
-    unsigned long mem_addr;
-
-
-    /* 28.9 - (1-2): ioports have been set up already */
-
-    /* 28.9 - (3): connect FCC's tx and rx clocks */
-    immr->im_cpmux.cmx_uar = 0;
-    immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
-							info->cmxfcr_value;
-
-    /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
-    immr->im_fcc[info->ether_index].fcc_gfmr =
-      FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-
-    /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
-    immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
-
-    /* 28.9 - (6): FDSR: Ethernet Syn */
-    immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
-
-    /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
-    rxIdx = 0;
-    txIdx = 0;
-
-    /* Setup Receiver Buffer Descriptors */
-    for (i = 0; i < PKTBUFSRX; i++)
-    {
-      rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-      rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
-    }
-    rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-    /* Setup Ethernet Transmitter Buffer Descriptors */
-    for (i = 0; i < TX_BUF_CNT; i++)
-    {
-      rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
-      rtx.txbd[i].cbd_datlen = 0;
-      rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
-    }
-    rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-    /* 28.9 - (7): initialise parameter ram */
-    pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
-
-    /* clear whole structure to make sure all reserved fields are zero */
-    memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
-
-    /*
-     * common Parameter RAM area
-     *
-     * Allocate space in the reserved FCC area of DPRAM for the
-     * internal buffers.  No one uses this space (yet), so we
-     * can do this.  Later, we will add resource management for
-     * this area.
-     */
-    mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
-    pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
-    pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
-    /*
-     * Set maximum bytes per receive buffer.
-     * It must be a multiple of 32.
-     */
-    pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
-    pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CFG_CPMFCR_RAMTYPE) << 24;
-    pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
-    pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CFG_CPMFCR_RAMTYPE) << 24;
-    pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
-
-    /* protocol-specific area */
-    pram_ptr->fen_cmask = 0xdebb20e3;	/* CRC mask */
-    pram_ptr->fen_cpres = 0xffffffff;	/* CRC preset */
-    pram_ptr->fen_retlim = 15;		/* Retry limit threshold */
-    pram_ptr->fen_mflr = PKT_MAXBUF_SIZE;   /* maximum frame length register */
-    /*
-     * Set Ethernet station address.
-     *
-     * This is supplied in the board information structure, so we
-     * copy that into the controller.
-     * So, far we have only been given one Ethernet address. We make
-     * it unique by setting a few bits in the upper byte of the
-     * non-static part of the address.
-     */
-#define ea eth_get_dev()->enetaddr
-    pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
-    pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
-    pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
-    pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
-    /* pad pointer. use tiptr since we don't need a specific padding char */
-    pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
-    pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE;	/* maximum DMA1 length */
-    pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE;	/* maximum DMA2 length */
-    pram_ptr->fen_rfthr = 1;
-    pram_ptr->fen_rfcnt = 1;
-
-    /* 28.9 - (8): clear out events in FCCE */
-    immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
-
-    /* 28.9 - (9): FCCM: mask all events */
-    immr->im_fcc[info->ether_index].fcc_fccm = 0;
-
-    /* 28.9 - (10-12): we don't use ethernet interrupts */
-
-    /* 28.9 - (13)
-     *
-     * Let's re-initialize the channel now.  We have to do it later
-     * than the manual describes because we have just now finished
-     * the BD initialization.
-     */
-    cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
-			    info->cpm_cr_enet_sblock,
-			    0x0c,
-			    CPM_CR_INIT_TRX) | CPM_CR_FLG;
-    do {
-	__asm__ __volatile__ ("eieio");
-    } while (cp->cp_cpcr & CPM_CR_FLG);
-
-    /* 28.9 - (14): enable tx/rx in gfmr */
-    immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-
-    return 1;
-}
-
-static void fec_halt(struct eth_device* dev)
-{
-    struct ether_fcc_info_s * info = dev->priv;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
-    /* write GFMR: disable tx/rx */
-    immr->im_fcc[info->ether_index].fcc_gfmr &=
-						~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-}
-
-int fec_initialize(bd_t *bis)
-{
-	struct eth_device* dev;
-	int i;
-
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
-	{
-		dev = (struct eth_device*) malloc(sizeof *dev);
-		memset(dev, 0, sizeof *dev);
-
-		sprintf(dev->name, "FCC%d ETHERNET",
-			ether_fcc_info[i].ether_index + 1);
-		dev->priv   = &ether_fcc_info[i];
-		dev->init   = fec_init;
-		dev->halt   = fec_halt;
-		dev->send   = fec_send;
-		dev->recv   = fec_recv;
-
-		eth_register(dev);
-
-#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
-		&& defined(CONFIG_BITBANGMII)
-		miiphy_register(dev->name,
-				bb_miiphy_read,	bb_miiphy_write);
-#endif
-	}
-
-	return 1;
-}
-
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
-
-#define ELBT_BUFSZ	1024	/* must be multiple of 32 */
-
-#define ELBT_CRCSZ	4
-
-#define ELBT_NRXBD	4	/* must be at least 2 */
-#define ELBT_NTXBD	4
-
-#define ELBT_MAXRXERR	32
-#define ELBT_MAXTXERR	32
-
-#define ELBT_CLSWAIT	1000	/* msec to wait for further input frames */
-
-typedef
-	struct {
-		uint off;
-		char *lab;
-	}
-elbt_prdesc;
-
-typedef
-	struct {
-		uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
-		uint badsrc, badtyp, badlen, badbit;
-	}
-elbt_rxeacc;
-
-static elbt_prdesc rxeacc_descs[] = {
-	{ offsetof(elbt_rxeacc, _l),		"Not Last in Frame"	},
-	{ offsetof(elbt_rxeacc, _f),		"Not First in Frame"	},
-	{ offsetof(elbt_rxeacc, m),		"Address Miss"		},
-	{ offsetof(elbt_rxeacc, bc),		"Broadcast Address"	},
-	{ offsetof(elbt_rxeacc, mc),		"Multicast Address"	},
-	{ offsetof(elbt_rxeacc, lg),		"Frame Length Violation"},
-	{ offsetof(elbt_rxeacc, no),		"Non-Octet Alignment"	},
-	{ offsetof(elbt_rxeacc, sh),		"Short Frame"		},
-	{ offsetof(elbt_rxeacc, cr),		"CRC Error"		},
-	{ offsetof(elbt_rxeacc, ov),		"Overrun"		},
-	{ offsetof(elbt_rxeacc, cl),		"Collision"		},
-	{ offsetof(elbt_rxeacc, badsrc),	"Bad Src Address"	},
-	{ offsetof(elbt_rxeacc, badtyp),	"Bad Frame Type"	},
-	{ offsetof(elbt_rxeacc, badlen),	"Bad Frame Length"	},
-	{ offsetof(elbt_rxeacc, badbit),	"Data Compare Errors"	},
-};
-static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
-
-typedef
-	struct {
-		uint def, hb, lc, rl, rc, un, csl;
-	}
-elbt_txeacc;
-
-static elbt_prdesc txeacc_descs[] = {
-	{ offsetof(elbt_txeacc, def),		"Defer Indication"	},
-	{ offsetof(elbt_txeacc, hb),		"Heartbeat"		},
-	{ offsetof(elbt_txeacc, lc),		"Late Collision"	},
-	{ offsetof(elbt_txeacc, rl),		"Retransmission Limit"	},
-	{ offsetof(elbt_txeacc, rc),		"Retry Count"		},
-	{ offsetof(elbt_txeacc, un),		"Underrun"		},
-	{ offsetof(elbt_txeacc, csl),		"Carrier Sense Lost"	},
-};
-static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
-
-typedef
-	struct {
-		uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
-		uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
-		cbd_t rxbd[ELBT_NRXBD];
-		cbd_t txbd[ELBT_NTXBD];
-		enum { Idle, Running, Closing, Closed } state;
-		int proff, page, sblock;
-		uint clstime, nsent, ntxerr, nrcvd, nrxerr;
-		ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
-		elbt_rxeacc rxeacc;
-		elbt_txeacc txeacc;
-	} __attribute__ ((aligned(8)))
-elbt_chan;
-
-static uchar patbytes[ELBT_NTXBD] = {
-	0xff, 0xaa, 0x55, 0x00
-};
-static uint patwords[ELBT_NTXBD] = {
-	0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
-};
-
-#ifdef __GNUC__
-static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
-#else
-#error "elbt_chans must be 64-bit aligned"
-#endif
-
-#define CPM_CR_GRACEFUL_STOP_TX	((ushort)0x0005)
-
-static elbt_prdesc epram_descs[] = {
-	{ offsetof(fcc_enet_t, fen_crcec),	"CRC Errors"		},
-	{ offsetof(fcc_enet_t, fen_alec),	"Alignment Errors"	},
-	{ offsetof(fcc_enet_t, fen_disfc),	"Discarded Frames"	},
-	{ offsetof(fcc_enet_t, fen_octc),	"Octets"		},
-	{ offsetof(fcc_enet_t, fen_colc),	"Collisions"		},
-	{ offsetof(fcc_enet_t, fen_broc),	"Broadcast Frames"	},
-	{ offsetof(fcc_enet_t, fen_mulc),	"Multicast Frames"	},
-	{ offsetof(fcc_enet_t, fen_uspc),	"Undersize Frames"	},
-	{ offsetof(fcc_enet_t, fen_frgc),	"Fragments"		},
-	{ offsetof(fcc_enet_t, fen_ospc),	"Oversize Frames"	},
-	{ offsetof(fcc_enet_t, fen_jbrc),	"Jabbers"		},
-	{ offsetof(fcc_enet_t, fen_p64c),	"64 Octet Frames"	},
-	{ offsetof(fcc_enet_t, fen_p65c),	"65-127 Octet Frames"	},
-	{ offsetof(fcc_enet_t, fen_p128c),	"128-255 Octet Frames"	},
-	{ offsetof(fcc_enet_t, fen_p256c),	"256-511 Octet Frames"	},
-	{ offsetof(fcc_enet_t, fen_p512c),	"512-1023 Octet Frames"	},
-	{ offsetof(fcc_enet_t, fen_p1024c),	"1024-1518 Octet Frames"},
-};
-static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
-
-/*
- * given an elbt_prdesc array and an array of base addresses, print
- * each prdesc down the screen with the values fetched from each
- * base address across the screen
- */
-static void
-print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
-{
-	elbt_prdesc *dp = descs, *edp = dp + ndesc;
-	int i;
-
-	printf ("%32s", "");
-
-	for (i = 0; i < nbase; i++)
-		printf ("  Channel %d", i);
-
-	putc ('\n');
-
-	while (dp < edp) {
-
-		printf ("%-32s", dp->lab);
-
-		for (i = 0; i < nbase; i++) {
-			uint val = *(uint *)(bases[i] + dp->off);
-
-			printf (" %10u", val);
-		}
-
-		putc ('\n');
-
-		dp++;
-	}
-}
-
-/*
- * return number of bits that are set in a value; value contains
- * nbits (right-justified) bits.
- */
-static uint __inline__
-nbs (uint value, uint nbits)
-{
-	uint cnt = 0;
-	uint pos = sizeof (uint) * 8;
-
-	__asm__ __volatile__ ("\
-	mtctr	%2\n\
-1:	rlwnm.	%2,%1,%4,31,31\n\
-	beq	2f\n\
-	addi	%0,%0,1\n\
-2:	subi	%4,%4,1\n\
-	bdnz	1b"
-	: "=r"(cnt)
-	: "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
-	: "ctr", "cc" );
-
-	return (cnt);
-}
-
-static ulong
-badbits (uchar *bp, int n, ulong pat)
-{
-	ulong *lp, cnt = 0;
-	int nl;
-
-	while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
-		uchar diff;
-
-		diff = *bp++ ^ (uchar)pat;
-
-		if (diff)
-			cnt += nbs ((ulong)diff, 8);
-
-		n--;
-	}
-
-	lp = (ulong *)bp;
-	nl = n / sizeof (ulong);
-	n -= nl * sizeof (ulong);
-
-	while (nl > 0) {
-		ulong diff;
-
-		diff = *lp++ ^ pat;
-
-		if (diff)
-			cnt += nbs (diff, 32);
-
-		nl--;
-	}
-
-	bp = (uchar *)lp;
-
-	while (n > 0) {
-		uchar diff;
-
-		diff = *bp++ ^ (uchar)pat;
-
-		if (diff)
-			cnt += nbs ((ulong)diff, 8);
-
-		n--;
-	}
-
-	return (cnt);
-}
-
-static inline unsigned short
-swap16 (unsigned short x)
-{
-	return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
-}
-
-/* broadcast is not an error - we send them like that */
-#define BD_ENET_RX_ERRS	(BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
-
-void
-eth_loopback_test (void)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile cpm8260_t *cp = &(immr->im_cpm);
-	int c, nclosed;
-	ulong runtime, nmsec;
-	uchar *bases[3];
-
-	puts ("FCC Ethernet External loopback test\n");
-
-	memcpy (NetOurEther, gd->bd->bi_enetaddr, 6);
-
-	/*
-	 * global initialisations for all FCC channels
-	 */
-
-	/* 28.9 - (1-2): ioports have been set up already */
-
-#if defined(CONFIG_HYMOD)
-	/*
-	 * Attention: this is board-specific
-	 * 0, FCC1
-	 * 1, FCC2
-	 * 2, FCC3
-	 */
-#       define FCC_START_LOOP 0
-#       define FCC_END_LOOP   2
-
-	/*
-	 * Attention: this is board-specific
-	 * - FCC1 Rx-CLK is CLK10
-	 * - FCC1 Tx-CLK is CLK11
-	 * - FCC2 Rx-CLK is CLK13
-	 * - FCC2 Tx-CLK is CLK14
-	 * - FCC3 Rx-CLK is CLK15
-	 * - FCC3 Tx-CLK is CLK16
-	 */
-
-	/* 28.9 - (3): connect FCC's tx and rx clocks */
-	immr->im_cpmux.cmx_uar = 0;
-	immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
-	    CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
-	    CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
-#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
-	/*
-	 * Attention: this is board-specific
-	 * 1, FCC2
-	 */
-#       define FCC_START_LOOP 1
-#       define FCC_END_LOOP   1
-
-	/*
-	 * Attention: this is board-specific
-	 * - FCC2 Rx-CLK is CLK13
-	 * - FCC2 Tx-CLK is CLK14
-	 */
-
-	/* 28.9 - (3): connect FCC's tx and rx clocks */
-	immr->im_cpmux.cmx_uar = 0;
-	immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
-#else
-#error "eth_loopback_test not supported on your board"
-#endif
-
-	puts ("Initialise FCC channels:");
-
-	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
-		elbt_chan *ecp = &elbt_chans[c];
-		volatile fcc_t *fcp = &immr->im_fcc[c];
-		volatile fcc_enet_t *fpp;
-		int i;
-		ulong addr;
-
-		/*
-		 * initialise channel data
-		 */
-
-		printf (" %d", c);
-
-		memset ((void *)ecp, 0, sizeof (*ecp));
-
-		ecp->state = Idle;
-
-		switch (c) {
-
-		case 0: /* FCC1 */
-			ecp->proff = PROFF_FCC1;
-			ecp->page = CPM_CR_FCC1_PAGE;
-			ecp->sblock = CPM_CR_FCC1_SBLOCK;
-			break;
-
-		case 1: /* FCC2 */
-			ecp->proff = PROFF_FCC2;
-			ecp->page = CPM_CR_FCC2_PAGE;
-			ecp->sblock = CPM_CR_FCC2_SBLOCK;
-			break;
-
-		case 2: /* FCC3 */
-			ecp->proff = PROFF_FCC3;
-			ecp->page = CPM_CR_FCC3_PAGE;
-			ecp->sblock = CPM_CR_FCC3_SBLOCK;
-			break;
-		}
-
-		/*
-		 * set up tx buffers and bds
-		 */
-
-		for (i = 0; i < ELBT_NTXBD; i++) {
-			cbd_t *bdp = &ecp->txbd[i];
-			uchar *bp = &ecp->txbufs[i][0];
-
-			bdp->cbd_bufaddr = (uint)bp;
-			/* room for crc */
-			bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
-			bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
-				BD_ENET_TX_LAST | BD_ENET_TX_TC;
-
-			memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
-			NetSetEther (bp, NetBcastAddr, 0x8000);
-		}
-		ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-		/*
-		 * set up rx buffers and bds
-		 */
-
-		for (i = 0; i < ELBT_NRXBD; i++) {
-		    cbd_t *bdp = &ecp->rxbd[i];
-		    uchar *bp = &ecp->rxbufs[i][0];
-
-		    bdp->cbd_bufaddr = (uint)bp;
-		    bdp->cbd_datlen = 0;
-		    bdp->cbd_sc = BD_ENET_RX_EMPTY;
-
-		    memset ((void *)bp, 0, ELBT_BUFSZ);
-		}
-		ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-		/*
-		 * set up the FCC channel hardware
-		 */
-
-		/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
-		fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
-
-		/* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
-		fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
-			FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
-			FCC_PSMR_MON | FCC_PSMR_RSH;
-
-		/* 28.9 - (6): FDSR: Ethernet Syn */
-		fcp->fcc_fdsr = 0xD555;
-
-		/* 29.9 - (7): initialise parameter ram */
-		fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
-
-		/* clear whole struct to make sure all resv fields are zero */
-		memset ((void *)fpp, 0, sizeof (fcc_enet_t));
-
-		/*
-		 * common Parameter RAM area
-		 *
-		 * Allocate space in the reserved FCC area of DPRAM for the
-		 * internal buffers.  No one uses this space (yet), so we
-		 * can do this.  Later, we will add resource management for
-		 * this area.
-		 */
-		addr = CPM_FCC_SPECIAL_BASE + (c * 64);
-		fpp->fen_genfcc.fcc_riptr = addr;
-		fpp->fen_genfcc.fcc_tiptr = addr + 32;
-
-		/*
-		 * Set maximum bytes per receive buffer.
-		 * It must be a multiple of 32.
-		 * buffers are in 60x bus memory.
-		 */
-		fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
-		fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
-		fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
-		fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
-		fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
-
-		/* protocol-specific area */
-		fpp->fen_cmask = 0xdebb20e3;	/* CRC mask */
-		fpp->fen_cpres = 0xffffffff;	/* CRC preset */
-		fpp->fen_retlim = 15;		/* Retry limit threshold */
-		fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
-
-		/*
-		 * Set Ethernet station address.
-		 *
-		 * This is supplied in the board information structure, so we
-		 * copy that into the controller.
-		 * So, far we have only been given one Ethernet address. We use
-		 * the same address for all channels
-		 */
-#define ea gd->bd->bi_enetaddr
-		fpp->fen_paddrh = (ea[5] << 8) + ea[4];
-		fpp->fen_paddrm = (ea[3] << 8) + ea[2];
-		fpp->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
-
-		fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
-		/*
-		 * pad pointer. use tiptr since we don't need
-		 * a specific padding char
-		 */
-		fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
-		fpp->fen_maxd1 = PKT_MAXDMA_SIZE;	/* max DMA1 length */
-		fpp->fen_maxd2 = PKT_MAXDMA_SIZE;	/* max DMA2 length */
-		fpp->fen_rfthr = 1;
-		fpp->fen_rfcnt = 1;
-
-		/* 28.9 - (8): clear out events in FCCE */
-		fcp->fcc_fcce = ~0x0;
-
-		/* 28.9 - (9): FCCM: mask all events */
-		fcp->fcc_fccm = 0;
-
-		/* 28.9 - (10-12): we don't use ethernet interrupts */
-
-		/* 28.9 - (13)
-		 *
-		 * Let's re-initialize the channel now.  We have to do it later
-		 * than the manual describes because we have just now finished
-		 * the BD initialization.
-		 */
-		cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
-			0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-		do {
-			__asm__ __volatile__ ("eieio");
-		} while (cp->cp_cpcr & CPM_CR_FLG);
-	}
-
-	puts (" done\nStarting test... (Ctrl-C to Finish)\n");
-
-	/*
-	 * Note: don't want serial output from here until the end of the
-	 * test - the delays would probably stuff things up.
-	 */
-
-	runtime = get_timer (0);
-
-	do {
-		nclosed = 0;
-
-		for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
-			volatile fcc_t *fcp = &immr->im_fcc[c];
-			elbt_chan *ecp = &elbt_chans[c];
-			int i;
-
-			switch (ecp->state) {
-
-			case Idle:
-				/*
-				 * set the channel Running ...
-				 */
-
-				/* 28.9 - (14): enable tx/rx in gfmr */
-				fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
-
-				ecp->state = Running;
-				break;
-
-			case Running:
-				/*
-				 * (while Running only) check for
-				 * termination of the test
-				 */
-				if (ctrlc ()) {
-					/*
-					 * initiate a "graceful stop transmit"
-					 * on the channel
-					 */
-					cp->cp_cpcr = mk_cr_cmd (ecp->page, \
-						ecp->sblock, 0x0c, \
-						CPM_CR_GRACEFUL_STOP_TX) | \
-						CPM_CR_FLG;
-					do {
-						__asm__ __volatile__ ("eieio");
-					} while (cp->cp_cpcr & CPM_CR_FLG);
-
-					ecp->clstime = get_timer (0);
-					ecp->state = Closing;
-				}
-				/* fall through ... */
-
-			case Closing:
-				/*
-				 * (while Running or Closing) poll the channel:
-				 * - check for any non-READY tx buffers and
-				 *   make them ready
-				 * - check for any non-EMPTY rx buffers and
-				 *   check that they were received correctly,
-				 *   adjust counters etc, then make empty
-				 */
-
-				for (i = 0; i < ELBT_NTXBD; i++) {
-					cbd_t *bdp = &ecp->txbd[i];
-					ushort sc = bdp->cbd_sc;
-
-					if ((sc & BD_ENET_TX_READY) != 0)
-						continue;
-
-					/*
-					 * this frame has finished
-					 * transmitting
-					 */
-					ecp->nsent++;
-
-					if (sc & BD_ENET_TX_STATS) {
-						ulong n;
-
-						/*
-						 * we had an error on
-						 * the transmission
-						 */
-						n = ecp->ntxerr++;
-						if (n < ELBT_MAXTXERR)
-							ecp->txerrs[n] = sc;
-
-						if (sc & BD_ENET_TX_DEF)
-							ecp->txeacc.def++;
-						if (sc & BD_ENET_TX_HB)
-							ecp->txeacc.hb++;
-						if (sc & BD_ENET_TX_LC)
-							ecp->txeacc.lc++;
-						if (sc & BD_ENET_TX_RL)
-							ecp->txeacc.rl++;
-						if (sc & BD_ENET_TX_RCMASK)
-							ecp->txeacc.rc++;
-						if (sc & BD_ENET_TX_UN)
-							ecp->txeacc.un++;
-						if (sc & BD_ENET_TX_CSL)
-							ecp->txeacc.csl++;
-
-						bdp->cbd_sc &= \
-							~BD_ENET_TX_STATS;
-					}
-
-					if (ecp->state == Closing)
-						ecp->clstime = get_timer (0);
-
-					/* make it ready again */
-					bdp->cbd_sc |= BD_ENET_TX_READY;
-				}
-
-				for (i = 0; i < ELBT_NRXBD; i++) {
-					cbd_t *bdp = &ecp->rxbd[i];
-					ushort sc = bdp->cbd_sc, mask;
-
-					if ((sc & BD_ENET_RX_EMPTY) != 0)
-						continue;
-
-					/* we have a new frame in this buffer */
-					ecp->nrcvd++;
-
-					mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
-					if ((sc & mask) != mask) {
-						/* somethings wrong here ... */
-						if (!(sc & BD_ENET_RX_LAST))
-							ecp->rxeacc._l++;
-						if (!(sc & BD_ENET_RX_FIRST))
-							ecp->rxeacc._f++;
-					}
-
-					if (sc & BD_ENET_RX_ERRS) {
-						ulong n;
-
-						/*
-						 * we had some sort of error
-						 * on the frame
-						 */
-						n = ecp->nrxerr++;
-						if (n < ELBT_MAXRXERR)
-							ecp->rxerrs[n] = sc;
-
-						if (sc & BD_ENET_RX_MISS)
-							ecp->rxeacc.m++;
-						if (sc & BD_ENET_RX_BC)
-							ecp->rxeacc.bc++;
-						if (sc & BD_ENET_RX_MC)
-							ecp->rxeacc.mc++;
-						if (sc & BD_ENET_RX_LG)
-							ecp->rxeacc.lg++;
-						if (sc & BD_ENET_RX_NO)
-							ecp->rxeacc.no++;
-						if (sc & BD_ENET_RX_SH)
-							ecp->rxeacc.sh++;
-						if (sc & BD_ENET_RX_CR)
-							ecp->rxeacc.cr++;
-						if (sc & BD_ENET_RX_OV)
-							ecp->rxeacc.ov++;
-						if (sc & BD_ENET_RX_CL)
-							ecp->rxeacc.cl++;
-
-						bdp->cbd_sc &= \
-							~BD_ENET_RX_ERRS;
-					}
-					else {
-						ushort datlen = bdp->cbd_datlen;
-						Ethernet_t *ehp;
-						ushort prot;
-						int ours, tb, n, nbytes;
-
-						ehp = (Ethernet_t *) \
-							&ecp->rxbufs[i][0];
-
-						ours = memcmp (ehp->et_src, \
-							NetOurEther, 6);
-
-						prot = swap16 (ehp->et_protlen);
-						tb = prot & 0x8000;
-						n = prot & 0x7fff;
-
-						nbytes = ELBT_BUFSZ - \
-							offsetof (Ethernet_t, \
-								et_dsap) - \
-							ELBT_CRCSZ;
-
-						/* check the frame is correct */
-						if (datlen != ELBT_BUFSZ)
-							ecp->rxeacc.badlen++;
-						else if (!ours)
-							ecp->rxeacc.badsrc++;
-						else if (!tb || n >= ELBT_NTXBD)
-							ecp->rxeacc.badtyp++;
-						else {
-							ulong patword = \
-								patwords[n];
-							uint nbb;
-
-							nbb = badbits ( \
-								&ehp->et_dsap, \
-								nbytes, \
-								patword);
-
-							ecp->rxeacc.badbit += \
-								nbb;
-						}
-					}
-
-					if (ecp->state == Closing)
-					    ecp->clstime = get_timer (0);
-
-					/* make it empty again */
-					bdp->cbd_sc |= BD_ENET_RX_EMPTY;
-				}
-
-				if (ecp->state != Closing)
-					break;
-
-				/*
-				 * (while Closing) check to see if
-				 * waited long enough
-				 */
-
-				if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
-					/* write GFMR: disable tx/rx */
-					fcp->fcc_gfmr &= \
-						~(FCC_GFMR_ENT | FCC_GFMR_ENR);
-					ecp->state = Closed;
-				}
-
-				break;
-
-			case Closed:
-				nclosed++;
-				break;
-			}
-		}
-
-	} while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
-
-	runtime = get_timer (runtime);
-	if (runtime <= ELBT_CLSWAIT) {
-		printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
-			runtime, ELBT_CLSWAIT);
-		return;
-	}
-	nmsec = runtime - ELBT_CLSWAIT;
-
-	printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
-		nmsec, ELBT_CLSWAIT);
-
-	/*
-	 * now print stats
-	 */
-
-	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
-		elbt_chan *ecp = &elbt_chans[c];
-		uint rxpps, txpps, nerr;
-
-		rxpps = (ecp->nrcvd * 1000) / nmsec;
-		txpps = (ecp->nsent * 1000) / nmsec;
-
-		printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
-			"%d sent (%d pps, %d txerrs)\n\n", c,
-			ecp->nrcvd, rxpps, ecp->nrxerr,
-			ecp->nsent, txpps, ecp->ntxerr);
-
-		if ((nerr = ecp->nrxerr) > 0) {
-			ulong i;
-
-			printf ("\tFirst %d rx errs:", nerr);
-			for (i = 0; i < nerr; i++)
-				printf (" %04x", ecp->rxerrs[i]);
-			putc ('\n');
-		}
-
-		if ((nerr = ecp->ntxerr) > 0) {
-			ulong i;
-
-			printf ("\tFirst %d tx errs:", nerr);
-			for (i = 0; i < nerr; i++)
-				printf (" %04x", ecp->txerrs[i]);
-			putc ('\n');
-		}
-	}
-
-	puts ("Receive Error Counts:\n");
-	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
-		bases[c] = (uchar *)&elbt_chans[c].rxeacc;
-	print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
-
-	puts ("\nTransmit Error Counts:\n");
-	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
-		bases[c] = (uchar *)&elbt_chans[c].txeacc;
-	print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
-
-	puts ("\nRMON(-like) Counters:\n");
-	for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
-		bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
-	print_desc (epram_descs, epram_ndesc, bases, 3);
-}
-
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-#endif	/* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
diff --git a/drivers/net/ether_scc.c b/drivers/net/ether_scc.c
deleted file mode 100644
index d22e8b216c..0000000000
--- a/drivers/net/ether_scc.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * MPC8260 SCC Ethernet
- *
- * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright (c) 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/cpm_8260.h>
-#include <mpc8260.h>
-#include <net.h>
-#include <command.h>
-#include <config.h>
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET)
-
-#if (CONFIG_ETHER_INDEX == 1)
-#  define PROFF_ENET            PROFF_SCC1
-#  define CPM_CR_ENET_PAGE      CPM_CR_SCC1_PAGE
-#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC1_SBLOCK
-#  define CMXSCR_MASK          (CMXSCR_SC1          |\
-				CMXSCR_RS1CS_MSK    |\
-				CMXSCR_TS1CS_MSK)
-
-#elif (CONFIG_ETHER_INDEX == 2)
-#  define PROFF_ENET            PROFF_SCC2
-#  define CPM_CR_ENET_PAGE      CPM_CR_SCC2_PAGE
-#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC2_SBLOCK
-#  define CMXSCR_MASK          (CMXSCR_SC2          |\
-				CMXSCR_RS2CS_MSK    |\
-				CMXSCR_TS2CS_MSK)
-
-#elif (CONFIG_ETHER_INDEX == 3)
-#  define PROFF_ENET            PROFF_SCC3
-#  define CPM_CR_ENET_PAGE      CPM_CR_SCC3_PAGE
-#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC3_SBLOCK
-#  define CMXSCR_MASK          (CMXSCR_SC3          |\
-				CMXSCR_RS3CS_MSK    |\
-				CMXSCR_TS3CS_MSK)
-#elif (CONFIG_ETHER_INDEX == 4)
-#  define PROFF_ENET            PROFF_SCC4
-#  define CPM_CR_ENET_PAGE      CPM_CR_SCC4_PAGE
-#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC4_SBLOCK
-#  define CMXSCR_MASK          (CMXSCR_SC4          |\
-				CMXSCR_RS4CS_MSK    |\
-				CMXSCR_TS4CS_MSK)
-
-#endif
-
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH  1520
-
-#define TX_BUF_CNT 2
-
-#define TOUT_LOOP 1000000
-
-static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
-
-static uint rxIdx;      /* index of the current RX buffer */
-static uint txIdx;      /* index of the current TX buffer */
-
-/*
- * SCC Ethernet Tx and Rx buffer descriptors allocated at the
- *  immr->udata_bd address on Dual-Port RAM
- * Provide for Double Buffering
- */
-
-typedef volatile struct CommonBufferDescriptor {
-    cbd_t rxbd[PKTBUFSRX];         /* Rx BD */
-    cbd_t txbd[TX_BUF_CNT];        /* Tx BD */
-} RTXBD;
-
-static RTXBD *rtx;
-
-
-int eth_send(volatile void *packet, int length)
-{
-    int i;
-    int result = 0;
-
-    if (length <= 0) {
-	printf("scc: bad packet size: %d\n", length);
-	goto out;
-    }
-
-    for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    puts ("scc: tx buffer not ready\n");
-	    goto out;
-	}
-    }
-
-    rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
-    rtx->txbd[txIdx].cbd_datlen = length;
-    rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
-				BD_ENET_TX_WRAP);
-
-    for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-	if (i >= TOUT_LOOP) {
-	    puts ("scc: tx error\n");
-	    goto out;
-	}
-    }
-
-    /* return only status bits */
-    result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
-
- out:
-    return result;
-}
-
-
-int eth_rx(void)
-{
-    int length;
-
-    for (;;)
-    {
-	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-	    length = -1;
-	    break;     /* nothing received - leave for() loop */
-	}
-
-	length = rtx->rxbd[rxIdx].cbd_datlen;
-
-	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
-	{
-	    printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
-	}
-	else
-	{
-	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
-	}
-
-
-	/* Give the buffer back to the SCC. */
-	rtx->rxbd[rxIdx].cbd_datlen = 0;
-
-	/* wrap around buffer index when necessary */
-	if ((rxIdx + 1) >= PKTBUFSRX) {
-	    rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
-					       BD_ENET_RX_EMPTY);
-	    rxIdx = 0;
-	}
-	else {
-	    rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-	    rxIdx++;
-	}
-    }
-    return length;
-}
-
-/**************************************************************
- *
- * SCC Ethernet Initialization Routine
- *
- *************************************************************/
-
-int eth_init(bd_t *bis)
-{
-    int i;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    scc_enet_t *pram_ptr;
-    uint dpaddr;
-
-    rxIdx = 0;
-    txIdx = 0;
-
-    /* assign static pointer to BD area */
-    dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
-    rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
-
-    /* 24.21 - (1-3): ioports have been set up already */
-
-    /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
-    immr->im_cpmux.cmx_uar = 0;
-    immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
-			       CFG_CMXSCR_VALUE);
-
-
-    /* 24.21 (6) write RBASE and TBASE to parameter RAM */
-    pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
-    pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
-    pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);
-
-    pram_ptr->sen_genscc.scc_rfcr = 0x18;  /* Nrml Ops and Mot byte ordering */
-    pram_ptr->sen_genscc.scc_tfcr = 0x18;  /* Mot byte ordering, Nrml access */
-
-    pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */
-
-    pram_ptr->sen_cpres  = ~(0x0);        /* Preset CRC */
-    pram_ptr->sen_cmask  = 0xdebb20e3;    /* Constant Mask for CRC */
-
-
-    /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
-    while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
-    immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
-				     CPM_CR_ENET_SBLOCK,
-				     0x0c,
-				     CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-    /* 24.21 - (8-18): Set up parameter RAM */
-    pram_ptr->sen_crcec  = 0x0;           /* Error Counter CRC (unused) */
-    pram_ptr->sen_alec   = 0x0;           /* Align Error Counter (unused) */
-    pram_ptr->sen_disfc  = 0x0;           /* Discard Frame Counter (unused) */
-
-    pram_ptr->sen_pads   = 0x8888;        /* Short Frame PAD Characters */
-
-    pram_ptr->sen_retlim = 15;            /* Retry Limit Threshold */
-
-    pram_ptr->sen_maxflr = 1518;  /* MAX Frame Length Register */
-    pram_ptr->sen_minflr = 64;            /* MIN Frame Length Register */
-
-    pram_ptr->sen_maxd1  = DBUF_LENGTH;   /* MAX DMA1 Length Register */
-    pram_ptr->sen_maxd2  = DBUF_LENGTH;   /* MAX DMA2 Length Register */
-
-    pram_ptr->sen_gaddr1 = 0x0;   /* Group Address Filter 1 (unused) */
-    pram_ptr->sen_gaddr2 = 0x0;   /* Group Address Filter 2 (unused) */
-    pram_ptr->sen_gaddr3 = 0x0;   /* Group Address Filter 3 (unused) */
-    pram_ptr->sen_gaddr4 = 0x0;   /* Group Address Filter 4 (unused) */
-
-#  define ea bis->bi_enetaddr
-    pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
-    pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
-    pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
-#  undef ea
-
-    pram_ptr->sen_pper   = 0x0;   /* Persistence (unused) */
-
-    pram_ptr->sen_iaddr1 = 0x0;   /* Individual Address Filter 1 (unused) */
-    pram_ptr->sen_iaddr2 = 0x0;   /* Individual Address Filter 2 (unused) */
-    pram_ptr->sen_iaddr3 = 0x0;   /* Individual Address Filter 3 (unused) */
-    pram_ptr->sen_iaddr4 = 0x0;   /* Individual Address Filter 4 (unused) */
-
-    pram_ptr->sen_taddrh = 0x0;   /* Tmp Address (MSB) (unused) */
-    pram_ptr->sen_taddrm = 0x0;   /* Tmp Address (unused) */
-    pram_ptr->sen_taddrl = 0x0;   /* Tmp Address (LSB) (unused) */
-
-
-    /* 24.21 - (19): Initialize RxBD */
-    for (i = 0; i < PKTBUFSRX; i++)
-    {
-	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-	rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
-	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
-    }
-
-    rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-    /* 24.21 - (20): Initialize TxBD */
-    for (i = 0; i < TX_BUF_CNT; i++)
-    {
-	rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD  |
-			       BD_ENET_TX_LAST |
-			       BD_ENET_TX_TC);
-	rtx->txbd[i].cbd_datlen = 0;                  /* Reset */
-	rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
-    }
-
-    rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-    /* 24.21 - (21): Write 0xffff to SCCE */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);
-
-    /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
-						   SCCE_ENET_RXF |
-						   SCCE_ENET_TXB);
-
-    /* 24.21 - (23): we don't use ethernet interrupts */
-
-    /* 24.21 - (24): Clear GSMR_H to enable normal operations */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;
-
-    /* 24.21 - (25): Clear GSMR_L to enable normal operations */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI        |
-						    SCC_GSMRL_TPL_48     |
-						    SCC_GSMRL_TPP_10     |
-						    SCC_GSMRL_MODE_ENET);
-
-    /* 24.21 - (26): Initialize DSR */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
-
-    /* 24.21 - (27): Initialize PSMR2
-     *
-     * Settings:
-     *	CRC = 32-Bit CCITT
-     *	NIB = Begin searching for SFD 22 bits after RENA
-     *	FDE = Full Duplex Enable
-     *	BRO = Reject broadcast packets
-     *	PROMISCOUS = Catch all packets regardless of dest. MAC adress
-     */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr   =	SCC_PSMR_ENCRC	|
-							SCC_PSMR_NIB22	|
-#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
-							SCC_PSMR_FDE	|
-#endif
-#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
-							SCC_PSMR_BRO	|
-#endif
-#if defined(CONFIG_SCC_ENET_PROMISCOUS)
-							SCC_PSMR_PRO	|
-#endif
-							0;
-
-    /* 24.21 - (28): Write to GSMR_L to enable SCC */
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
-						     SCC_GSMRL_ENT);
-
-    return 0;
-}
-
-
-void eth_halt(void)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
-						      SCC_GSMRL_ENT);
-}
-
-
-#endif  /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
deleted file mode 100644
index fed57139f8..0000000000
--- a/drivers/net/fec.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/fec.h>
-
-#ifdef  CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-#endif
-
-#ifdef	CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
-#endif
-
-#ifdef	CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
-#endif
-
-#include <net.h>
-#include <command.h>
-
-#ifdef	CONFIG_M5272
-#define FEC_ADDR		(CFG_MBAR + 0x840)
-#endif
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
-#define FEC_ADDR 		(CFG_MBAR + 0x1000)
-#endif
-
-#undef	ET_DEBUG
-#undef	MII_DEBUG
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
-
-#ifdef CFG_DISCOVER_PHY
-#include <miiphy.h>
-static void mii_discover_phy (void);
-#endif
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH  1520
-
-#define TX_BUF_CNT 2
-
-#define TOUT_LOOP 100
-
-#define PKT_MAXBUF_SIZE		1518
-#define PKT_MINBUF_SIZE		64
-#define PKT_MAXBLR_SIZE		1520
-
-
-static char txbuf[DBUF_LENGTH];
-
-static uint rxIdx;		/* index of the current RX buffer */
-static uint txIdx;		/* index of the current TX buffer */
-
-/*
-  * FEC Ethernet Tx and Rx buffer descriptors allocated at the
-  *  immr->udata_bd address on Dual-Port RAM
-  * Provide for Double Buffering
-  */
-
-typedef volatile struct CommonBufferDescriptor {
-	cbd_t rxbd[PKTBUFSRX];	/* Rx BD */
-	cbd_t txbd[TX_BUF_CNT];	/* Tx BD */
-} RTXBD;
-
-static RTXBD *rtx = NULL;
-
-int eth_send (volatile void *packet, int length)
-{
-	int j, rc;
-	volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
-
-	/* section 16.9.23.3
-	 * Wait for ready
-	 */
-	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
-	       && (j < TOUT_LOOP)) {
-		udelay (1);
-		j++;
-	}
-	if (j >= TOUT_LOOP) {
-		printf ("TX not ready\n");
-	}
-
-	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
-	rtx->txbd[txIdx].cbd_datlen = length;
-	rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
-
-	/* Activate transmit Buffer Descriptor polling */
-	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active    */
-
-	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
-	       && (j < TOUT_LOOP)) {
-		udelay (1);
-		j++;
-	}
-	if (j >= TOUT_LOOP) {
-		printf ("TX timeout\n");
-	}
-#ifdef ET_DEBUG
-	printf ("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
-		__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
-		(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
-#endif
-
-	/* return only status bits */ ;
-	rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
-
-	txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-	return rc;
-}
-
-int eth_rx (void)
-{
-	int length;
-	volatile fec_t *fecp = (fec_t *) FEC_ADDR;
-
-	for (;;) {
-		/* section 16.9.23.2 */
-		if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-			length = -1;
-			break;	/* nothing received - leave for() loop */
-		}
-
-		length = rtx->rxbd[rxIdx].cbd_datlen;
-
-		if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
-#ifdef ET_DEBUG
-			printf ("%s[%d] err: %x\n",
-				__FUNCTION__, __LINE__,
-				rtx->rxbd[rxIdx].cbd_sc);
-#endif
-		} else {
-			/* Pass the packet up to the protocol layers. */
-			NetReceive (NetRxPackets[rxIdx], length - 4);
-		}
-
-		/* Give the buffer back to the FEC. */
-		rtx->rxbd[rxIdx].cbd_datlen = 0;
-
-		/* wrap around buffer index when necessary */
-		if ((rxIdx + 1) >= PKTBUFSRX) {
-			rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
-				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-			rxIdx = 0;
-		} else {
-			rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-			rxIdx++;
-		}
-
-		/* Try to fill Buffer Descriptors */
-		fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
-	}
-
-	return length;
-}
-
-/**************************************************************
- *
- * FEC Ethernet Initialization Routine
- *
- *************************************************************/
-#define FEC_ECNTRL_ETHER_EN	0x00000002
-#define FEC_ECNTRL_RESET	0x00000001
-
-#define FEC_RCNTRL_BC_REJ	0x00000010
-#define FEC_RCNTRL_PROM		0x00000008
-#define FEC_RCNTRL_MII_MODE	0x00000004
-#define FEC_RCNTRL_DRT		0x00000002
-#define FEC_RCNTRL_LOOP		0x00000001
-
-#define FEC_TCNTRL_FDEN		0x00000004
-#define FEC_TCNTRL_HBC		0x00000002
-#define FEC_TCNTRL_GTS		0x00000001
-
-#define	FEC_RESET_DELAY		50000
-
-int eth_init (bd_t * bd)
-{
-#ifndef CFG_ENET_BD_BASE
-	DECLARE_GLOBAL_DATA_PTR;
-#endif
-	int i;
-	volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
-		return 0;
-	}
-
-	/* We use strictly polling mode only
-	 */
-	fecp->fec_imask = 0;
-
-	/* Clear any pending interrupt */
-	fecp->fec_ievent = 0xffffffff;
-
-	/* Set station address   */
-#define ea bd->bi_enetaddr
-	fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
-		(ea[2] << 8) | (ea[3]);
-	fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
-#ifdef ET_DEBUG
-	printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
-		ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
-#endif
-#undef ea
-
-#ifdef CONFIG_M5271
-	/* Clear multicast address hash table
-	 */
-	fecp->fec_ghash_table_high = 0;
-	fecp->fec_ghash_table_low = 0;
-
-	/* Clear individual address hash table
-	 */
-	fecp->fec_ihash_table_high = 0;
-	fecp->fec_ihash_table_low = 0;
-#else
-	/* Clear multicast address hash table
-	 */
-#ifdef	CONFIG_M5282
-	fecp->fec_ihash_table_high = 0;
-	fecp->fec_ihash_table_low = 0;
-#else
-	fecp->fec_hash_table_high = 0;
-	fecp->fec_hash_table_low = 0;
-#endif
-#endif
-
-	/* Set maximum receive buffer size.
-	 */
-	fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
-
-	/*
-	 * Setup Buffers and Buffer Desriptors
-	 */
-	rxIdx = 0;
-	txIdx = 0;
-
-	if (!rtx) {
-#ifdef CFG_ENET_BD_BASE
-		rtx = (RTXBD *) CFG_ENET_BD_BASE;
-#else
-		rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
-				 (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
-				  +0xFF)
-				  & ~0xFF)
-				);
-		debug("set ENET_DB_BASE to %lX\n",(long) rtx);
-#endif
-	}
-
-	/*
-	 * Setup Receiver Buffer Descriptors (13.14.24.18)
-	 * Settings:
-	 *     Empty, Wrap
-	 */
-	for (i = 0; i < PKTBUFSRX; i++) {
-		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
-	}
-	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-	/*
-	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
-	 * Settings:
-	 *    Last, Tx CRC
-	 */
-	for (i = 0; i < TX_BUF_CNT; i++) {
-		rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
-		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
-	}
-	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-	/* Set receive and transmit descriptor base
-	 */
-	fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
-	fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
-
-	/* Enable MII mode
-	 */
-
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
-	fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
-	fecp->fec_x_cntrl = 0;
-	/* Set MII speed */
-	fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
-	fecp->fec_mii_speed *= 2;
-
-	/* Configure port B for MII.
-	 */
-	/* port initialization was already made in cpu_init_f() */
-
-	/* Now enable the transmit and receive processing
-	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
-
-#ifdef CFG_DISCOVER_PHY
-	/* wait for the PHY to wake up after reset */
-	mii_discover_phy ();
-#endif
-
-	/* And last, try to fill Rx Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
-
-	return 1;
-}
-
-void eth_halt (void)
-{
-	volatile fec_t *fecp = (fec_t *) FEC_ADDR;
-
-	fecp->fec_ecntrl = 0;
-}
-
-
-#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
-
-static int phyaddr = -1;	/* didn't find a PHY yet */
-static uint phytype;
-
-/* Make MII read/write commands for the FEC.
-*/
-
-#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | \
-						(REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
-						(REG & 0x1f) << 18) | \
-						(VAL & 0xffff))
-
-/* Interrupt events/masks.
-*/
-#define FEC_ENET_HBERR	((uint)0x80000000)	/* Heartbeat error */
-#define FEC_ENET_BABR	((uint)0x40000000)	/* Babbling receiver */
-#define FEC_ENET_BABT	((uint)0x20000000)	/* Babbling transmitter */
-#define FEC_ENET_GRA	((uint)0x10000000)	/* Graceful stop complete */
-#define FEC_ENET_TXF	((uint)0x08000000)	/* Full frame transmitted */
-#define FEC_ENET_TXB	((uint)0x04000000)	/* A buffer was transmitted */
-#define FEC_ENET_RXF	((uint)0x02000000)	/* Full frame received */
-#define FEC_ENET_RXB	((uint)0x01000000)	/* A buffer was received */
-#define FEC_ENET_MII	((uint)0x00800000)	/* MII interrupt */
-#define FEC_ENET_EBERR	((uint)0x00400000)	/* SDMA bus error */
-
-/* PHY identification
- */
-#define PHY_ID_LXT970		0x78100000	/* LXT970 */
-#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
-#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
-#define PHY_ID_QS6612		0x01814400	/* QS6612 */
-#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
-#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
-#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
-
-/* send command to phy using mii, wait for result */
-static uint mii_send (uint mii_cmd)
-{
-	uint mii_reply;
-	volatile fec_t *ep = (fec_t *) (FEC_ADDR);
-
-	ep->fec_mii_data = mii_cmd;	/* command to phy */
-
-	/* wait for mii complete */
-	while (!(ep->fec_ievent & FEC_ENET_MII));	/* spin until done */
-	mii_reply = ep->fec_mii_data;	/* result from phy */
-	ep->fec_ievent = FEC_ENET_MII;	/* clear MII complete */
-#ifdef ET_DEBUG
-	printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
-		__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-	return (mii_reply & 0xffff);	/* data read from phy */
-}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
-
-#if defined(CFG_DISCOVER_PHY)
-static void mii_discover_phy (void)
-{
-#define MAX_PHY_PASSES 11
-	uint phyno;
-	int pass;
-
-	phyaddr = -1;		/* didn't find a PHY yet */
-	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
-		if (pass > 1) {
-			/* PHY may need more time to recover from reset.
-			 * The LXT970 needs 50ms typical, no maximum is
-			 * specified, so wait 10ms before try again.
-			 * With 11 passes this gives it 100ms to wake up.
-			 */
-			udelay (10000);	/* wait 10ms */
-		}
-		for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
-			phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
-			printf ("PHY type 0x%x pass %d type ", phytype, pass);
-#endif
-			if (phytype != 0xffff) {
-				phyaddr = phyno;
-				phytype <<= 16;
-				phytype |= mii_send (mk_mii_read (phyno,
-								  PHY_PHYIDR2));
-
-#ifdef ET_DEBUG
-				printf ("PHY @ 0x%x pass %d type ", phyno,
-					pass);
-				switch (phytype & 0xfffffff0) {
-				case PHY_ID_LXT970:
-					printf ("LXT970\n");
-					break;
-				case PHY_ID_LXT971:
-					printf ("LXT971\n");
-					break;
-				case PHY_ID_82555:
-					printf ("82555\n");
-					break;
-				case PHY_ID_QS6612:
-					printf ("QS6612\n");
-					break;
-				case PHY_ID_AMD79C784:
-					printf ("AMD79C784\n");
-					break;
-				case PHY_ID_LSI80225B:
-					printf ("LSI L80225/B\n");
-					break;
-				default:
-					printf ("0x%08x\n", phytype);
-					break;
-				}
-#endif
-			}
-		}
-	}
-	if (phyaddr < 0) {
-		printf ("No PHY device found.\n");
-	}
-}
-#endif /* CFG_DISCOVER_PHY */
-
-#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
-
-static int mii_init_done = 0;
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_init (void)
-{
-	volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
-
-	int i;
-
-	if (mii_init_done != 0) {
-		return;
-	}
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-
-	fecp->fec_ecntrl = FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
-		return;
-	}
-
-	/* We use strictly polling mode only
-	 */
-	fecp->fec_imask = 0;
-
-	/* Clear any pending interrupt
-	 */
-	fecp->fec_ievent = 0xffffffff;
-
-	/* Set MII speed */
-	fecp->fec_mii_speed = 0x0e;
-
-	/* Configure port B for MII.
-	 */
-	/* port initialization was already made in cpu_init_f() */
-
-	/* Now enable the transmit and receive processing */
-	fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
-
-	mii_init_done = 1;
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- *	  no PHY connected...
- *	  For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- *	  Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcf52x2_miiphy_read (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short *value)
-{
-	short rdreg;		/* register working value */
-
-#ifdef MII_DEBUG
-	printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
-	rdreg = mii_send (mk_mii_read (addr, reg));
-
-	*value = rdreg;
-
-#ifdef MII_DEBUG
-	printf ("0x%04x\n", *value);
-#endif
-
-	return 0;
-}
-
-int mcf52x2_miiphy_write (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value)
-{
-	short rdreg;		/* register working value */
-
-#ifdef MII_DEBUG
-	printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
-	rdreg = mii_send (mk_mii_write (addr, reg, value));
-
-#ifdef MII_DEBUG
-	printf ("0x%04x\n", value);
-#endif
-
-	return 0;
-}
-#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
-#endif /* CFG_CMD_NET, FEC_ENET */
-
-int mcf52x2_miiphy_initialize(bd_t *bis)
-{
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
-#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
-	miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
-#endif
-#endif
-	return 0;
-}
diff --git a/drivers/net/fec_mpc8xx.c b/drivers/net/fec_mpc8xx.c
deleted file mode 100644
index 18464ba80f..0000000000
--- a/drivers/net/fec_mpc8xx.c
+++ /dev/null
@@ -1,1016 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <commproc.h>
-#include <net.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef	ET_DEBUG
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && \
-	(defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
-
-/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
-#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
-#define CONFIG_ETHER_ON_FEC1 1
-#endif
-
-/* define WANT_MII when MII support is required */
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
-#define WANT_MII
-#else
-#undef WANT_MII
-#endif
-
-#if defined(WANT_MII)
-#include <miiphy.h>
-
-#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#endif
-
-#if defined(CONFIG_RMII) && !defined(WANT_MII)
-#error RMII support is unusable without a working PHY.
-#endif
-
-#ifdef CFG_DISCOVER_PHY
-static int mii_discover_phy(struct eth_device *dev);
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
-		unsigned char  reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char  addr,
-		unsigned char  reg, unsigned short value);
-
-static struct ether_fcc_info_s
-{
-	int ether_index;
-	int fecp_offset;
-	int phy_addr;
-	int actual_phy_addr;
-	int initialized;
-}
-	ether_fcc_info[] = {
-#if defined(CONFIG_ETHER_ON_FEC1)
-	{
-		0,
-		offsetof(immap_t, im_cpm.cp_fec1),
-#if defined(CONFIG_FEC1_PHY)
-		CONFIG_FEC1_PHY,
-#else
-		-1,	/* discover */
-#endif
-		-1,
-		0,
-
-	},
-#endif
-#if defined(CONFIG_ETHER_ON_FEC2)
-	{
-		1,
-		offsetof(immap_t, im_cpm.cp_fec2),
-#if defined(CONFIG_FEC2_PHY)
-		CONFIG_FEC2_PHY,
-#else
-		-1,
-#endif
-		-1,
-		0,
-	},
-#endif
-};
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH  1520
-
-#define TX_BUF_CNT 2
-
-#define TOUT_LOOP 100
-
-#define PKT_MAXBUF_SIZE		1518
-#define PKT_MINBUF_SIZE		64
-#define PKT_MAXBLR_SIZE		1520
-
-#ifdef __GNUC__
-static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
-#else
-#error txbuf must be aligned.
-#endif
-
-static uint rxIdx;	/* index of the current RX buffer */
-static uint txIdx;	/* index of the current TX buffer */
-
-/*
-  * FEC Ethernet Tx and Rx buffer descriptors allocated at the
-  *  immr->udata_bd address on Dual-Port RAM
-  * Provide for Double Buffering
-  */
-
-typedef volatile struct CommonBufferDescriptor {
-    cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
-    cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
-} RTXBD;
-
-static RTXBD *rtx = NULL;
-
-static int fec_send(struct eth_device* dev, volatile void *packet, int length);
-static int fec_recv(struct eth_device* dev);
-static int fec_init(struct eth_device* dev, bd_t * bd);
-static void fec_halt(struct eth_device* dev);
-
-int fec_initialize(bd_t *bis)
-{
-	struct eth_device* dev;
-	struct ether_fcc_info_s *efis;
-	int             i;
-
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
-
-		dev = malloc(sizeof(*dev));
-		if (dev == NULL)
-			hang();
-
-		memset(dev, 0, sizeof(*dev));
-
-		/* for FEC1 make sure that the name of the interface is the same
-		   as the old one for compatibility reasons */
-		if (i == 0) {
-			sprintf (dev->name, "FEC ETHERNET");
-		} else {
-			sprintf (dev->name, "FEC%d ETHERNET",
-				ether_fcc_info[i].ether_index + 1);
-		}
-
-		efis = &ether_fcc_info[i];
-
-		/*
-		 * reset actual phy addr
-		 */
-		efis->actual_phy_addr = -1;
-
-		dev->priv = efis;
-		dev->init = fec_init;
-		dev->halt = fec_halt;
-		dev->send = fec_send;
-		dev->recv = fec_recv;
-
-		eth_register(dev);
-
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
-		miiphy_register(dev->name,
-			fec8xx_miiphy_read, fec8xx_miiphy_write);
-#endif
-	}
-	return 1;
-}
-
-static int fec_send(struct eth_device* dev, volatile void *packet, int length)
-{
-	int j, rc;
-	struct ether_fcc_info_s *efis = dev->priv;
-	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
-
-	/* section 16.9.23.3
-	 * Wait for ready
-	 */
-	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-		udelay(1);
-		j++;
-	}
-	if (j>=TOUT_LOOP) {
-		printf("TX not ready\n");
-	}
-
-	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
-	rtx->txbd[txIdx].cbd_datlen  = length;
-	rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
-	__asm__ ("eieio");
-
-	/* Activate transmit Buffer Descriptor polling */
-	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active	*/
-
-	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-#if defined(CONFIG_ICU862)
-		udelay(10);
-#else
-		udelay(1);
-#endif
-		j++;
-	}
-	if (j>=TOUT_LOOP) {
-		printf("TX timeout\n");
-	}
-#ifdef ET_DEBUG
-	printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
-	__FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
-	(rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
-#endif
-	/* return only status bits */;
-	rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
-
-	txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-	return rc;
-}
-
-static int fec_recv (struct eth_device *dev)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	volatile fec_t *fecp =
-		(volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
-	int length;
-
-	for (;;) {
-		/* section 16.9.23.2 */
-		if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-			length = -1;
-			break;	/* nothing received - leave for() loop */
-		}
-
-		length = rtx->rxbd[rxIdx].cbd_datlen;
-
-		if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
-#ifdef ET_DEBUG
-			printf ("%s[%d] err: %x\n",
-				__FUNCTION__, __LINE__,
-				rtx->rxbd[rxIdx].cbd_sc);
-#endif
-		} else {
-			volatile uchar *rx = NetRxPackets[rxIdx];
-
-			length -= 4;
-
-#if (CONFIG_COMMANDS & CFG_CMD_CDP)
-			if ((rx[0] & 1) != 0
-			    && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
-			    && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
-				rx = NULL;
-#endif
-			/*
-			 * Pass the packet up to the protocol layers.
-			 */
-			if (rx != NULL)
-				NetReceive (rx, length);
-		}
-
-		/* Give the buffer back to the FEC. */
-		rtx->rxbd[rxIdx].cbd_datlen = 0;
-
-		/* wrap around buffer index when necessary */
-		if ((rxIdx + 1) >= PKTBUFSRX) {
-			rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
-				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-			rxIdx = 0;
-		} else {
-			rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-			rxIdx++;
-		}
-
-		__asm__ ("eieio");
-
-		/* Try to fill Buffer Descriptors */
-		fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
-	}
-
-	return length;
-}
-
-/**************************************************************
- *
- * FEC Ethernet Initialization Routine
- *
- *************************************************************/
-
-#define	FEC_ECNTRL_PINMUX	0x00000004
-#define FEC_ECNTRL_ETHER_EN	0x00000002
-#define FEC_ECNTRL_RESET	0x00000001
-
-#define FEC_RCNTRL_BC_REJ	0x00000010
-#define FEC_RCNTRL_PROM		0x00000008
-#define FEC_RCNTRL_MII_MODE	0x00000004
-#define FEC_RCNTRL_DRT		0x00000002
-#define FEC_RCNTRL_LOOP		0x00000001
-
-#define FEC_TCNTRL_FDEN		0x00000004
-#define FEC_TCNTRL_HBC		0x00000002
-#define FEC_TCNTRL_GTS		0x00000001
-
-#define	FEC_RESET_DELAY		50
-
-#if defined(CONFIG_RMII)
-
-static inline void fec_10Mbps(struct eth_device *dev)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	int fecidx = efis->ether_index;
-	uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
-
-	if ((unsigned int)fecidx >= 2)
-		hang();
-
-	((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |=  mask;
-}
-
-static inline void fec_100Mbps(struct eth_device *dev)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	int fecidx = efis->ether_index;
-	uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
-
-	if ((unsigned int)fecidx >= 2)
-		hang();
-
-	((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
-}
-
-#endif
-
-static inline void fec_full_duplex(struct eth_device *dev)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
-
-	fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
-	fecp->fec_x_cntrl |=  FEC_TCNTRL_FDEN;	/* FD enable */
-}
-
-static inline void fec_half_duplex(struct eth_device *dev)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
-
-	fecp->fec_r_cntrl |=  FEC_RCNTRL_DRT;
-	fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN;	/* FD disable */
-}
-
-static void fec_pin_init(int fecidx)
-{
-	bd_t           *bd = gd->bd;
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	volatile fec_t *fecp;
-
-	/*
-	 * only two FECs please
-	 */
-	if ((unsigned int)fecidx >= 2)
-		hang();
-
-	if (fecidx == 0)
-		fecp = &immr->im_cpm.cp_fec1;
-	else
-		fecp = &immr->im_cpm.cp_fec2;
-
-	/*
-	 * Set MII speed to 2.5 MHz or slightly below.
-	 * * According to the MPC860T (Rev. D) Fast ethernet controller user
-	 * * manual (6.2.14),
-	 * * the MII management interface clock must be less than or equal
-	 * * to 2.5 MHz.
-	 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
-	 * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
-	 *
-	 * All MII configuration is done via FEC1 registers:
-	 */
-	immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-
-#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
-	/* our PHYs are the limit at 2.5 MHz */
-	fecp->fec_mii_speed <<= 1;
-#endif
-
-#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
-	/* use MDC for MII */
-	immr->im_ioport.iop_pdpar |=  0x0080;
-	immr->im_ioport.iop_pddir &= ~0x0080;
-#endif
-
-	if (fecidx == 0) {
-#if defined(CONFIG_ETHER_ON_FEC1)
-
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
-
-#if !defined(CONFIG_RMII)
-
-		immr->im_ioport.iop_papar |=  0xf830;
-		immr->im_ioport.iop_padir |=  0x0830;
-		immr->im_ioport.iop_padir &= ~0xf000;
-
-		immr->im_cpm.cp_pbpar     |=  0x00001001;
-		immr->im_cpm.cp_pbdir     &= ~0x00001001;
-
-		immr->im_ioport.iop_pcpar |=  0x000c;
-		immr->im_ioport.iop_pcdir &= ~0x000c;
-
-		immr->im_cpm.cp_pepar     |=  0x00000003;
-		immr->im_cpm.cp_pedir     |=  0x00000003;
-		immr->im_cpm.cp_peso      &= ~0x00000003;
-
-		immr->im_cpm.cp_cptr      &= ~0x00000100;
-
-#else
-
-#if !defined(CONFIG_FEC1_PHY_NORXERR)
-		immr->im_ioport.iop_papar |=  0x1000;
-		immr->im_ioport.iop_padir &= ~0x1000;
-#endif
-		immr->im_ioport.iop_papar |=  0xe810;
-		immr->im_ioport.iop_padir |=  0x0810;
-		immr->im_ioport.iop_padir &= ~0xe000;
-
-		immr->im_cpm.cp_pbpar     |=  0x00000001;
-		immr->im_cpm.cp_pbdir     &= ~0x00000001;
-
-		immr->im_cpm.cp_cptr      |=  0x00000100;
-		immr->im_cpm.cp_cptr      &= ~0x00000050;
-
-#endif /* !CONFIG_RMII */
-
-#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
-		/*
-		 * Configure all of port D for MII.
-		 */
-		immr->im_ioport.iop_pdpar = 0x1fff;
-
-		/*
-		 * Bits moved from Rev. D onward
-		 */
-		if ((get_immr(0) & 0xffff) < 0x0501)
-			immr->im_ioport.iop_pddir = 0x1c58;	/* Pre rev. D */
-		else
-			immr->im_ioport.iop_pddir = 0x1fff;	/* Rev. D and later */
-#else
-		/*
-		 * Configure port A for MII.
-		 */
-
-#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
-
-		/*
-		 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
-		 * * of CPU, so for this board we need to configure Utopia and
-		 * * enable PD8 to MII-MDC function
-		 */
-		immr->im_ioport.iop_pdpar |= 0x4080;
-#endif
-
-		/*
-		 * Has Utopia been configured?
-		 */
-		if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
-			/*
-			 * YES - Use MUXED mode for UTOPIA bus.
-			 * This frees Port A for use by MII (see 862UM table 41-6).
-			 */
-			immr->im_ioport.utmode &= ~0x80;
-		} else {
-			/*
-			 * NO - set SPLIT mode for UTOPIA bus.
-			 *
-			 * This doesn't really effect UTOPIA (which isn't
-			 * enabled anyway) but just tells the 862
-			 * to use port A for MII (see 862UM table 41-6).
-			 */
-			immr->im_ioport.utmode |= 0x80;
-		}
-#endif				/* !defined(CONFIG_ICU862) */
-
-#endif	/* CONFIG_ETHER_ON_FEC1 */
-	} else if (fecidx == 1) {
-
-#if defined(CONFIG_ETHER_ON_FEC2)
-
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
-
-#if !defined(CONFIG_RMII)
-		immr->im_cpm.cp_pepar     |=  0x0003fffc;
-		immr->im_cpm.cp_pedir     |=  0x0003fffc;
-		immr->im_cpm.cp_peso      &= ~0x000087fc;
-		immr->im_cpm.cp_peso      |=  0x00037800;
-
-		immr->im_cpm.cp_cptr      &= ~0x00000080;
-#else
-
-#if !defined(CONFIG_FEC2_PHY_NORXERR)
-		immr->im_cpm.cp_pepar     |=  0x00000010;
-		immr->im_cpm.cp_pedir     |=  0x00000010;
-		immr->im_cpm.cp_peso      &= ~0x00000010;
-#endif
-		immr->im_cpm.cp_pepar     |=  0x00039620;
-		immr->im_cpm.cp_pedir     |=  0x00039620;
-		immr->im_cpm.cp_peso      |=  0x00031000;
-		immr->im_cpm.cp_peso      &= ~0x00008620;
-
-		immr->im_cpm.cp_cptr      |=  0x00000080;
-		immr->im_cpm.cp_cptr      &= ~0x00000028;
-#endif /* CONFIG_RMII */
-
-#endif /* CONFIG_MPC885_FAMILY */
-
-#endif /* CONFIG_ETHER_ON_FEC2 */
-
-	}
-}
-
-static int fec_init (struct eth_device *dev, bd_t * bd)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	volatile fec_t *fecp =
-		(volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
-	int i;
-
-	if (efis->ether_index == 0) {
-#if defined(CONFIG_FADS)	/* FADS family uses FPGA (BCSR) to control PHYs */
-#if defined(CONFIG_MPC885ADS)
-		*(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
-#else
-		/* configure FADS for fast (FEC) ethernet, half-duplex */
-		/* The LXT970 needs about 50ms to recover from reset, so
-		 * wait for it by discovering the PHY before leaving eth_init().
-		 */
-		{
-			volatile uint *bcsr4 = (volatile uint *) BCSR4;
-
-			*bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
-				| (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
-				   BCSR4_FETHRST);
-
-			/* reset the LXT970 PHY */
-			*bcsr4 &= ~BCSR4_FETHRST;
-			udelay (10);
-			*bcsr4 |= BCSR4_FETHRST;
-			udelay (10);
-		}
-#endif /* CONFIG_MPC885ADS */
-#endif /* CONFIG_FADS */
-	}
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
-		return 0;
-	}
-
-	/* We use strictly polling mode only
-	 */
-	fecp->fec_imask = 0;
-
-	/* Clear any pending interrupt
-	 */
-	fecp->fec_ievent = 0xffc0;
-
-	/* No need to set the IVEC register */
-
-	/* Set station address
-	 */
-#define ea eth_get_dev()->enetaddr
-	fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
-	fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
-#undef ea
-
-#if (CONFIG_COMMANDS & CFG_CMD_CDP)
-	/*
-	 * Turn on multicast address hash table
-	 */
-	fecp->fec_hash_table_high = 0xffffffff;
-	fecp->fec_hash_table_low = 0xffffffff;
-#else
-	/* Clear multicast address hash table
-	 */
-	fecp->fec_hash_table_high = 0;
-	fecp->fec_hash_table_low = 0;
-#endif
-
-	/* Set maximum receive buffer size.
-	 */
-	fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
-
-	/* Set maximum frame length
-	 */
-	fecp->fec_r_hash = PKT_MAXBUF_SIZE;
-
-	/*
-	 * Setup Buffers and Buffer Desriptors
-	 */
-	rxIdx = 0;
-	txIdx = 0;
-
-	if (!rtx) {
-#ifdef CFG_ALLOC_DPRAM
-		rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
-				 dpram_alloc_align (sizeof (RTXBD), 8));
-#else
-		rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
-#endif
-	}
-	/*
-	 * Setup Receiver Buffer Descriptors (13.14.24.18)
-	 * Settings:
-	 *     Empty, Wrap
-	 */
-	for (i = 0; i < PKTBUFSRX; i++) {
-		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
-	}
-	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-	/*
-	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
-	 * Settings:
-	 *    Last, Tx CRC
-	 */
-	for (i = 0; i < TX_BUF_CNT; i++) {
-		rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
-		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
-	}
-	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-	/* Set receive and transmit descriptor base
-	 */
-	fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
-	fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
-
-	/* Enable MII mode
-	 */
-	fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
-	fecp->fec_x_cntrl = 0;
-
-	/* Enable big endian and don't care about SDMA FC.
-	 */
-	fecp->fec_fun_code = 0x78000000;
-
-	/*
-	 * Setup the pin configuration of the FEC
-	 */
-	fec_pin_init (efis->ether_index);
-
-	rxIdx = 0;
-	txIdx = 0;
-
-	/*
-	 * Now enable the transmit and receive processing
-	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
-
-	if (efis->phy_addr == -1) {
-#ifdef CFG_DISCOVER_PHY
-		/*
-		 * wait for the PHY to wake up after reset
-		 */
-		efis->actual_phy_addr = mii_discover_phy (dev);
-
-		if (efis->actual_phy_addr == -1) {
-			printf ("Unable to discover phy!\n");
-			return 0;
-		}
-#else
-		efis->actual_phy_addr = -1;
-#endif
-	} else {
-		efis->actual_phy_addr = efis->phy_addr;
-	}
-#if defined(CONFIG_MII) && defined(CONFIG_RMII)
-
-	/* the MII interface is connected to FEC1
-	 * so for the miiphy_xxx function to work we must
-	 * call mii_init since fec_halt messes the thing up
-	 */
-	if (efis->ether_index != 0)
-		mii_init();
-
-	/*
-	 * adapt the RMII speed to the speed of the phy
-	 */
-	if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
-		fec_100Mbps (dev);
-	} else {
-		fec_10Mbps (dev);
-	}
-#endif
-
-#if defined(CONFIG_MII)
-	/*
-	 * adapt to the half/full speed settings
-	 */
-	if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
-		fec_full_duplex (dev);
-	} else {
-		fec_half_duplex (dev);
-	}
-#endif
-
-	/* And last, try to fill Rx Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
-
-	efis->initialized = 1;
-
-	return 1;
-}
-
-
-static void fec_halt(struct eth_device* dev)
-{
-	struct ether_fcc_info_s *efis = dev->priv;
-	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
-	int i;
-
-	/* avoid halt if initialized; mii gets stuck otherwise */
-	if (!efis->initialized)
-		return;
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
-		return;
-	}
-
-	efis->initialized = 0;
-}
-
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
-
-/* Make MII read/write commands for the FEC.
-*/
-
-#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | \
-						(REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
-						(REG & 0x1f) << 18) | \
-						(VAL & 0xffff))
-
-/* Interrupt events/masks.
-*/
-#define FEC_ENET_HBERR	((uint)0x80000000)	/* Heartbeat error */
-#define FEC_ENET_BABR	((uint)0x40000000)	/* Babbling receiver */
-#define FEC_ENET_BABT	((uint)0x20000000)	/* Babbling transmitter */
-#define FEC_ENET_GRA	((uint)0x10000000)	/* Graceful stop complete */
-#define FEC_ENET_TXF	((uint)0x08000000)	/* Full frame transmitted */
-#define FEC_ENET_TXB	((uint)0x04000000)	/* A buffer was transmitted */
-#define FEC_ENET_RXF	((uint)0x02000000)	/* Full frame received */
-#define FEC_ENET_RXB	((uint)0x01000000)	/* A buffer was received */
-#define FEC_ENET_MII	((uint)0x00800000)	/* MII interrupt */
-#define FEC_ENET_EBERR	((uint)0x00400000)	/* SDMA bus error */
-
-/* PHY identification
- */
-#define PHY_ID_LXT970		0x78100000	/* LXT970 */
-#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
-#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
-#define PHY_ID_QS6612		0x01814400	/* QS6612 */
-#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
-#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
-#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
-#define PHY_ID_DM9161		0x0181B880	/* Davicom DM9161 */
-#define PHY_ID_KSM8995M		0x00221450	/* MICREL KS8995MA */
-
-/* send command to phy using mii, wait for result */
-static uint
-mii_send(uint mii_cmd)
-{
-	uint mii_reply;
-	volatile fec_t	*ep;
-	int cnt;
-
-	ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
-
-	ep->fec_mii_data = mii_cmd;	/* command to phy */
-
-	/* wait for mii complete */
-	cnt = 0;
-	while (!(ep->fec_ievent & FEC_ENET_MII)) {
-		if (++cnt > 1000) {
-			printf("mii_send STUCK!\n");
-			break;
-		}
-	}
-	mii_reply = ep->fec_mii_data;		/* result from phy */
-	ep->fec_ievent = FEC_ENET_MII;		/* clear MII complete */
-	return (mii_reply & 0xffff);		/* data read from phy */
-}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
-
-#if defined(CFG_DISCOVER_PHY)
-static int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
-	uint phyno;
-	int  pass;
-	uint phytype;
-	int phyaddr;
-
-	phyaddr = -1;	/* didn't find a PHY yet */
-	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
-		if (pass > 1) {
-			/* PHY may need more time to recover from reset.
-			 * The LXT970 needs 50ms typical, no maximum is
-			 * specified, so wait 10ms before try again.
-			 * With 11 passes this gives it 100ms to wake up.
-			 */
-			udelay(10000);	/* wait 10ms */
-		}
-		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
-			printf("PHY type 0x%x pass %d type ", phytype, pass);
-#endif
-			if (phytype != 0xffff) {
-				phyaddr = phyno;
-				phytype <<= 16;
-				phytype |= mii_send(mk_mii_read(phyno,
-								PHY_PHYIDR2));
-
-#ifdef ET_DEBUG
-				printf("PHY @ 0x%x pass %d type ",phyno,pass);
-				switch (phytype & 0xfffffff0) {
-				case PHY_ID_LXT970:
-					printf("LXT970\n");
-					break;
-				case PHY_ID_LXT971:
-					printf("LXT971\n");
-					break;
-				case PHY_ID_82555:
-					printf("82555\n");
-					break;
-				case PHY_ID_QS6612:
-					printf("QS6612\n");
-					break;
-				case PHY_ID_AMD79C784:
-					printf("AMD79C784\n");
-					break;
-				case PHY_ID_LSI80225B:
-					printf("LSI L80225/B\n");
-					break;
-				case PHY_ID_DM9161:
-					printf("Davicom DM9161\n");
-					break;
-				case PHY_ID_KSM8995M:
-					printf("MICREL KS8995M\n");
-					break;
-				default:
-					printf("0x%08x\n", phytype);
-					break;
-				}
-#endif
-			}
-		}
-	}
-	if (phyaddr < 0) {
-		printf("No PHY device found.\n");
-	}
-	return phyaddr;
-}
-#endif	/* CFG_DISCOVER_PHY */
-
-#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_init (void)
-{
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
-	int i, j;
-
-	for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
-		return;
-	}
-
-	/* We use strictly polling mode only
-	 */
-	fecp->fec_imask = 0;
-
-	/* Clear any pending interrupt
-	 */
-	fecp->fec_ievent = 0xffc0;
-
-	/* Setup the pin configuration of the FEC(s)
-	*/
-		fec_pin_init(ether_fcc_info[i].ether_index);
-
-	/* Now enable the transmit and receive processing
-	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
-	}
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- *	  no PHY connected...
- *	  For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- *	  Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
-		unsigned char  reg, unsigned short *value)
-{
-	short rdreg;    /* register working value */
-
-#ifdef MII_DEBUG
-	printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
-	rdreg = mii_send(mk_mii_read(addr, reg));
-
-	*value = rdreg;
-#ifdef MII_DEBUG
-	printf ("0x%04x\n", *value);
-#endif
-	return 0;
-}
-
-int fec8xx_miiphy_write(char *devname, unsigned char  addr,
-		unsigned char  reg, unsigned short value)
-{
-	short rdreg;    /* register working value */
-#ifdef MII_DEBUG
-	printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-	rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
-	printf ("0x%04x\n", value);
-#endif
-	return 0;
-}
-#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
-
-#endif	/* CFG_CMD_NET, FEC_ENET */
diff --git a/drivers/net/fec_mpc8xx.h b/drivers/net/fec_mpc8xx.h
deleted file mode 100644
index a49417c666..0000000000
--- a/drivers/net/fec_mpc8xx.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef	_FEC_H_
-#define	_FEC_H_
-
-
-#endif	/* _FEC_H_ */
diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c
deleted file mode 100644
index b598dd7f23..0000000000
--- a/drivers/net/ks8695eth.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * ks8695eth.c -- KS8695 ethernet driver
- *
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/****************************************************************************/
-
-#include <common.h>
-
-#ifdef	CONFIG_DRIVER_KS8695ETH
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-/****************************************************************************/
-
-/*
- * Hardware register access to the KS8695 LAN ethernet port
- * (well, it is the 4 port switch really).
- */
-#define	ks8695_read(a)    *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
-#define	ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
-
-/****************************************************************************/
-
-/*
- * Define the descriptor in-memory data structures.
- */
-struct ks8695_txdesc {
-	uint32_t	owner;
-	uint32_t	ctrl;
-	uint32_t	addr;
-	uint32_t	next;
-};
-
-struct ks8695_rxdesc {
-	uint32_t	status;
-	uint32_t	ctrl;
-	uint32_t	addr;
-	uint32_t	next;
-};
-
-/****************************************************************************/
-
-/*
- * Allocate local data structures to use for receiving and sending
- * packets. Just to keep it all nice and simple.
- */
-
-#define	TXDESCS		4
-#define	RXDESCS		4
-#define	BUFSIZE		2048
-
-volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
-volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
-volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
-
-/****************************************************************************/
-
-/*
- *	Ideally we want to use the MAC address stored in flash.
- *	But we do some sanity checks in case they are not present
- *	first.
- */
-unsigned char eth_mac[] = {
-	0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
-};
-
-void ks8695_getmac(void)
-{
-	unsigned char *fp;
-	int i;
-
-	/* Check if flash MAC is valid */
-	fp = (unsigned char *) 0x0201c000;
-	for (i = 0; (i < 6); i++) {
-		if ((fp[i] != 0) && (fp[i] != 0xff))
-			break;
-	}
-
-	/* If we found a valid looking MAC address then use it */
-	if (i < 6)
-		memcpy(&eth_mac[0], fp, 6);
-}
-
-/****************************************************************************/
-
-void eth_reset(bd_t *bd)
-{
-	int i;
-
-	debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
-
-	/* Reset the ethernet engines first */
-	ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
-	ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-
-	ks8695_getmac();
-
-	/* Set MAC address */
-	ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
-		(eth_mac[3] << 16) | (eth_mac[2] << 24)));
-	ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
-
-	/* Turn the 4 port switch on */
-	i = ks8695_read(KS8695_SWITCH_CTRL0);
-	ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
-	/* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
-
-	/* Initialize descriptor rings */
-	for (i = 0; (i < TXDESCS); i++) {
-		ks8695_tx[i].owner = 0;
-		ks8695_tx[i].ctrl = 0;
-		ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
-		ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
-	}
-	ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
-	ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
-
-	for (i = 0; (i < RXDESCS); i++) {
-		ks8695_rx[i].status = 0x80000000;
-		ks8695_rx[i].ctrl = BUFSIZE - 4;
-		ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
-		ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
-	}
-	ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
-	ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
-
-	/* The KS8695 is pretty slow reseting the ethernets... */
-	udelay(2000000);
-
-	/* Enable the ethernet engine */
-	ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
-	ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
-	ks8695_write(KS8695_LAN_DMA_TX, 0x3);
-	ks8695_write(KS8695_LAN_DMA_RX, 0x71);
-	ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
-
-	printf("KS8695 ETHERNET: ");
-	for (i = 0; (i < 5); i++) {
-		bd->bi_enetaddr[i] = eth_mac[i];
-		printf("%02x:", eth_mac[i]);
-	}
-	bd->bi_enetaddr[i] = eth_mac[i];
-	printf("%02x\n", eth_mac[i]);
-}
-
-/****************************************************************************/
-
-int eth_init(bd_t *bd)
-{
-	debug ("%s(%d): eth_init()\n", __FILE__, __LINE__);
-
-	eth_reset(bd);
-	return 0;
-}
-
-/****************************************************************************/
-
-void eth_halt(void)
-{
-	debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
-
-	/* Reset the ethernet engines */
-	ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
-	ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-}
-
-/****************************************************************************/
-
-int eth_rx(void)
-{
-	volatile struct ks8695_rxdesc *dp;
-	int i, len = 0;
-
-	debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
-
-	for (i = 0; (i < RXDESCS); i++) {
-		dp= &ks8695_rx[i];
-		if ((dp->status & 0x80000000) == 0) {
-			len = (dp->status & 0x7ff) - 4;
-			NetReceive((void *) dp->addr, len);
-			dp->status = 0x80000000;
-			ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
-			break;
-		}
-	}
-
-	return len;
-}
-
-/****************************************************************************/
-
-int eth_send(volatile void *packet, int len)
-{
-	volatile struct ks8695_txdesc *dp;
-	static int next = 0;
-
-	debug ("%s(%d): eth_send(packet=%x,len=%d)\n", __FILE__, __LINE__,
-		packet, len);
-
-	dp = &ks8695_tx[next];
-	memcpy((void *) dp->addr, (void *) packet, len);
-
-	if (len < 64) {
-		memset((void *) (dp->addr + len), 0, 64-len);
-		len = 64;
-	}
-
-	dp->ctrl = len | 0xe0000000;
-	dp->owner = 0x80000000;
-
-	ks8695_write(KS8695_LAN_DMA_TX, 0x3);
-	ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
-
-	if (++next >= TXDESCS)
-		next = 0;
-
-	return len;
-}
-
-#endif	/* CONFIG_DRIVER_KS8695ETH */
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
deleted file mode 100644
index a89c959cee..0000000000
--- a/drivers/net/lan91c96.c
+++ /dev/null
@@ -1,870 +0,0 @@
-/*------------------------------------------------------------------------
- * lan91c96.c
- * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based
- * on the SMC91111 driver from U-boot.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- *
- * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- *       Developed by Simple Network Magic Corporation (SNMC)
- * Copyright (C) 1996 by Erik Stahlman (ES)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * Information contained in this file was obtained from the LAN91C96
- * manual from SMC.  To get a copy, if you really want one, you can find
- * information under www.smsc.com.
- *
- *
- * "Features" of the SMC chip:
- *   6144 byte packet memory. ( for the 91C96 )
- *   EEPROM for configuration
- *   AUI/TP selection  ( mine has 10Base2/10BaseT select )
- *
- * Arguments:
- * 	io	= for the base address
- *	irq	= for the IRQ
- *
- * author:
- * 	Erik Stahlman				( erik@vt.edu )
- * 	Daris A Nevil				( dnevil@snmc.com )
- *
- *
- * Hardware multicast code from Peter Cammaert ( pc@denkart.be )
- *
- * Sources:
- *    o   SMSC LAN91C96 databook (www.smsc.com)
- *    o   smc91111.c (u-boot driver)
- *    o   smc9194.c (linux kernel driver)
- *    o   lan91c96.c (Intel Diagnostic Manager driver)
- *
- * History:
- * 	04/30/03  Mathijs Haarman	Modified smc91111.c (u-boot version)
- *					for lan91c96
- *---------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <command.h>
-#include "lan91c96.h"
-#include <net.h>
-
-#ifdef CONFIG_DRIVER_LAN91C96
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
-
-/*------------------------------------------------------------------------
- *
- * Configuration options, for the experienced user to change.
- *
- -------------------------------------------------------------------------*/
-
-/* Use power-down feature of the chip */
-#define POWER_DOWN	0
-
-/*
- * Wait time for memory to be free.  This probably shouldn't be
- * tuned that much, as waiting for this means nothing else happens
- * in the system
-*/
-#define MEMORY_WAIT_TIME 16
-
-#define SMC_DEBUG 0
-
-#if (SMC_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if SMC_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef SMC_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-
-/*------------------------------------------------------------------------
- *
- * The internal workings of the driver.  If you are changing anything
- * here with the SMC stuff, you should have the datasheet and know
- * what you are doing.
- *
- *------------------------------------------------------------------------
- */
-#define CARDNAME "LAN91C96"
-
-#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE
-
-#define SMC_DEV_NAME "LAN91C96"
-#define SMC_ALLOC_MAX_TRY 5
-#define SMC_TX_TIMEOUT 30
-
-#define ETH_ZLEN 60
-
-#ifdef  CONFIG_LAN91C96_USE_32_BIT
-#define USE_32_BIT  1
-#else
-#undef USE_32_BIT
-#endif
-
-/*-----------------------------------------------------------------
- *
- *  The driver can be entered at any of the following entry points.
- *
- *-----------------------------------------------------------------
- */
-
-extern int eth_init (bd_t * bd);
-extern void eth_halt (void);
-extern int eth_rx (void);
-extern int eth_send (volatile void *packet, int length);
-
-/*
- * This is called by  register_netdev().  It is responsible for
- * checking the portlist for the SMC9000 series chipset.  If it finds
- * one, then it will initialize the device, find the hardware information,
- * and sets up the appropriate device parameters.
- * NOTE: Interrupts are *OFF* when this procedure is called.
- *
- * NB:This shouldn't be static since it is referred to externally.
- */
-int smc_init (void);
-
-/*
- * This is called by  unregister_netdev().  It is responsible for
- * cleaning up before the driver is finally unregistered and discarded.
- */
-void smc_destructor (void);
-
-/*
- * The kernel calls this function when someone wants to use the device,
- * typically 'ifconfig ethX up'.
- */
-static int smc_open (bd_t *bd);
-
-
-/*
- * This is called by the kernel in response to 'ifconfig ethX down'.  It
- * is responsible for cleaning up everything that the open routine
- * does, and maybe putting the card into a powerdown state.
- */
-static int smc_close (void);
-
-/*
- * This is a separate procedure to handle the receipt of a packet, to
- * leave the interrupt code looking slightly cleaner
- */
-static int smc_rcv (void);
-
-/* See if a MAC address is defined in the current environment. If so use it. If not
- . print a warning and set the environment and other globals with the default.
- . If an EEPROM is present it really should be consulted.
-*/
-int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(unsigned char *v_rom_mac);
-
-/* ------------------------------------------------------------
- * Internal routines
- * ------------------------------------------------------------
- */
-
-static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
-
-/*
- * This function must be called before smc_open() if you want to override
- * the default mac address.
- */
-
-void smc_set_mac_addr (const unsigned char *addr)
-{
-	int i;
-
-	for (i = 0; i < sizeof (smc_mac_addr); i++) {
-		smc_mac_addr[i] = addr[i];
-	}
-}
-
-/*
- * smc_get_macaddr is no longer used. If you want to override the default
- * mac address, call smc_get_mac_addr as a part of the board initialisation.
- */
-
-
-/***********************************************
- * Show available memory                       *
- ***********************************************/
-void dump_memory_info (void)
-{
-	word mem_info;
-	word old_bank;
-
-	old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF;
-
-	SMC_SELECT_BANK (0);
-	mem_info = SMC_inw (LAN91C96_MIR);
-	PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
-
-	SMC_SELECT_BANK (old_bank);
-}
-
-/*
- * A rather simple routine to print out a packet for debugging purposes.
- */
-#if SMC_DEBUG > 2
-static void print_packet (byte *, int);
-#endif
-
-/* #define tx_done(dev) 1 */
-
-
-/* this does a soft reset on the device */
-static void smc_reset (void);
-
-/* Enable Interrupts, Receive, and Transmit */
-static void smc_enable (void);
-
-/* this puts the device in an inactive state */
-static void smc_shutdown (void);
-
-
-static int poll4int (byte mask, int timeout)
-{
-	int tmo = get_timer (0) + timeout * CFG_HZ;
-	int is_timeout = 0;
-	word old_bank = SMC_inw (LAN91C96_BANK_SELECT);
-
-	PRINTK2 ("Polling...\n");
-	SMC_SELECT_BANK (2);
-	while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) {
-		if (get_timer (0) >= tmo) {
-			is_timeout = 1;
-			break;
-		}
-	}
-
-	/* restore old bank selection */
-	SMC_SELECT_BANK (old_bank);
-
-	if (is_timeout)
-		return 1;
-	else
-		return 0;
-}
-
-/*
- * Function: smc_reset( void )
- * Purpose:
- *  	This sets the SMC91111 chip to its normal state, hopefully from whatever
- * 	mess that any other DOS driver has put it in.
- *
- * Maybe I should reset more registers to defaults in here?  SOFTRST  should
- * do that for me.
- *
- * Method:
- *	1.  send a SOFT RESET
- *	2.  wait for it to finish
- *	3.  enable autorelease mode
- *	4.  reset the memory management unit
- *	5.  clear all interrupts
- *
-*/
-static void smc_reset (void)
-{
-	PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME);
-
-	/* This resets the registers mostly to defaults, but doesn't
-	   affect EEPROM.  That seems unnecessary */
-	SMC_SELECT_BANK (0);
-	SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
-
-	udelay (10);
-
-	/* Disable transmit and receive functionality */
-	SMC_outw (0, LAN91C96_RCR);
-	SMC_outw (0, LAN91C96_TCR);
-
-	/* set the control register */
-	SMC_SELECT_BANK (1);
-	SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
-			  LAN91C96_CONTROL);
-
-	/* Disable all interrupts */
-	SMC_outb (0, LAN91C96_INT_MASK);
-}
-
-/*
- * Function: smc_enable
- * Purpose: let the chip talk to the outside work
- * Method:
- *	1.  Initialize the Memory Configuration Register
- *	2.  Enable the transmitter
- *	3.  Enable the receiver
-*/
-static void smc_enable ()
-{
-	PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME);
-	SMC_SELECT_BANK (0);
-
-	/* Initialize the Memory Configuration Register. See page
-	   49 of the LAN91C96 data sheet for details. */
-	SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
-
-	/* Initialize the Transmit Control Register */
-	SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR);
-	/* Initialize the Receive Control Register
-	 * FIXME:
-	 * The promiscuous bit set because I could not receive ARP reply
-	 * packets from the server when I send a ARP request. It only works
-	 * when I set the promiscuous bit
-	 */
-	SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
-}
-
-/*
- * Function: smc_shutdown
- * Purpose:  closes down the SMC91xxx chip.
- * Method:
- *	1. zero the interrupt mask
- *	2. clear the enable receive flag
- *	3. clear the enable xmit flags
- *
- * TODO:
- *   (1) maybe utilize power down mode.
- *	Why not yet?  Because while the chip will go into power down mode,
- *	the manual says that it will wake up in response to any I/O requests
- *	in the register space.   Empirical results do not show this working.
- */
-static void smc_shutdown ()
-{
-	PRINTK2 (CARDNAME ":smc_shutdown\n");
-
-	/* no more interrupts for me */
-	SMC_SELECT_BANK (2);
-	SMC_outb (0, LAN91C96_INT_MASK);
-
-	/* and tell the card to stay away from that nasty outside world */
-	SMC_SELECT_BANK (0);
-	SMC_outb (0, LAN91C96_RCR);
-	SMC_outb (0, LAN91C96_TCR);
-}
-
-
-/*
- * Function:  smc_hardware_send_packet(struct net_device * )
- * Purpose:
- *	This sends the actual packet to the SMC9xxx chip.
- *
- * Algorithm:
- * 	First, see if a saved_skb is available.
- *		( this should NOT be called if there is no 'saved_skb'
- *	Now, find the packet number that the chip allocated
- *	Point the data pointers at it in memory
- *	Set the length word in the chip's memory
- *	Dump the packet to chip memory
- *	Check if a last byte is needed ( odd length packet )
- *		if so, set the control flag right
- * 	Tell the card to send it
- *	Enable the transmit interrupt, so I know if it failed
- * 	Free the kernel data if I actually sent it.
- */
-static int smc_send_packet (volatile void *packet, int packet_length)
-{
-	byte packet_no;
-	unsigned long ioaddr;
-	byte *buf;
-	int length;
-	int numPages;
-	int try = 0;
-	int time_out;
-	byte status;
-
-
-	PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
-
-	length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
-
-	/* allocate memory
-	 ** The MMU wants the number of pages to be the number of 256 bytes
-	 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
-	 **
-	 ** The 91C111 ignores the size bits, but the code is left intact
-	 ** for backwards and future compatibility.
-	 **
-	 ** Pkt size for allocating is data length +6 (for additional status
-	 ** words, length and ctl!)
-	 **
-	 ** If odd size then last byte is included in this header.
-	 */
-	numPages = ((length & 0xfffe) + 6);
-	numPages >>= 8;				/* Divide by 256 */
-
-	if (numPages > 7) {
-		printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
-		return 0;
-	}
-
-	/* now, try to allocate the memory */
-
-	SMC_SELECT_BANK (2);
-	SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
-
-  again:
-	try++;
-	time_out = MEMORY_WAIT_TIME;
-	do {
-		status = SMC_inb (LAN91C96_INT_STATS);
-		if (status & LAN91C96_IST_ALLOC_INT) {
-
-			SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS);
-			break;
-		}
-	} while (--time_out);
-
-	if (!time_out) {
-		PRINTK2 ("%s: memory allocation, try %d failed ...\n",
-				 SMC_DEV_NAME, try);
-		if (try < SMC_ALLOC_MAX_TRY)
-			goto again;
-		else
-			return 0;
-	}
-
-	PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
-			 SMC_DEV_NAME, try);
-
-	/* I can send the packet now.. */
-
-	ioaddr = SMC_BASE_ADDRESS;
-
-	buf = (byte *) packet;
-
-	/* If I get here, I _know_ there is a packet slot waiting for me */
-	packet_no = SMC_inb (LAN91C96_ARR);
-	if (packet_no & LAN91C96_ARR_FAILED) {
-		/* or isn't there?  BAD CHIP! */
-		printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
-		return 0;
-	}
-
-	/* we have a packet address, so tell the card to use it */
-	SMC_outb (packet_no, LAN91C96_PNR);
-
-	/* point to the beginning of the packet */
-	SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
-
-	PRINTK3 ("%s: Trying to xmit packet of length %x\n",
-			 SMC_DEV_NAME, length);
-
-#if SMC_DEBUG > 2
-	printf ("Transmitting Packet\n");
-	print_packet (buf, length);
-#endif
-
-	/* send the packet length ( +6 for status, length and ctl byte )
-	   and the status word ( set to zeros ) */
-#ifdef USE_32_BIT
-	SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH);
-#else
-	SMC_outw (0, LAN91C96_DATA_HIGH);
-	/* send the packet length ( +6 for status words, length, and ctl */
-	SMC_outw ((length + 6), LAN91C96_DATA_HIGH);
-#endif /* USE_32_BIT */
-
-	/* send the actual data
-	 * I _think_ it's faster to send the longs first, and then
-	 * mop up by sending the last word.  It depends heavily
-	 * on alignment, at least on the 486.  Maybe it would be
-	 * a good idea to check which is optimal?  But that could take
-	 * almost as much time as is saved?
-	 */
-#ifdef USE_32_BIT
-	SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2);
-	if (length & 0x2)
-		SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
-				  LAN91C96_DATA_HIGH);
-#else
-	SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1);
-#endif /* USE_32_BIT */
-
-	/* Send the last byte, if there is one.   */
-	if ((length & 1) == 0) {
-		SMC_outw (0, LAN91C96_DATA_HIGH);
-	} else {
-		SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
-	}
-
-	/* and let the chipset deal with it */
-	SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
-
-	/* poll for TX INT */
-	if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
-		/* sending failed */
-		PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
-
-		/* release packet */
-		SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
-
-		/* wait for MMU getting ready (low) */
-		while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) {
-			udelay (10);
-		}
-
-		PRINTK2 ("MMU ready\n");
-
-
-		return 0;
-	} else {
-		/* ack. int */
-		SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
-
-		PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
-
-		/* release packet */
-		SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
-
-		/* wait for MMU getting ready (low) */
-		while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) {
-			udelay (10);
-		}
-
-		PRINTK2 ("MMU ready\n");
-	}
-
-	return length;
-}
-
-/*-------------------------------------------------------------------------
- * smc_destructor( struct net_device * dev )
- *   Input parameters:
- *	dev, pointer to the device structure
- *
- *   Output:
- *	None.
- *--------------------------------------------------------------------------
- */
-void smc_destructor ()
-{
-	PRINTK2 (CARDNAME ":smc_destructor\n");
-}
-
-
-/*
- * Open and Initialize the board
- *
- * Set up everything, reset the card, etc ..
- *
- */
-static int smc_open (bd_t *bd)
-{
-	int i, err;			/* used to set hw ethernet address */
-
-	PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME);
-
-	/* reset the hardware */
-
-	smc_reset ();
-	smc_enable ();
-
-	SMC_SELECT_BANK (1);
-
-	err = smc_get_ethaddr (bd);	/* set smc_mac_addr, and sync it with u-boot globals */
-	if (err < 0) {
-		memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
-		return (-1);	/* upper code ignores this, but NOT bi_enetaddr */
-	}
-#ifdef USE_32_BIT
-	for (i = 0; i < 6; i += 2) {
-		word address;
-
-		address = smc_mac_addr[i + 1] << 8;
-		address |= smc_mac_addr[i];
-		SMC_outw (address, LAN91C96_IA0 + i);
-	}
-#else
-	for (i = 0; i < 6; i++)
-		SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i);
-#endif
-	return 0;
-}
-
-/*-------------------------------------------------------------
- *
- * smc_rcv -  receive a packet from the card
- *
- * There is ( at least ) a packet waiting to be read from
- * chip-memory.
- *
- * o Read the status
- * o If an error, record it
- * o otherwise, read in the packet
- *-------------------------------------------------------------
- */
-static int smc_rcv ()
-{
-	int packet_number;
-	word status;
-	word packet_length;
-	int is_error = 0;
-
-#ifdef USE_32_BIT
-	dword stat_len;
-#endif
-
-
-	SMC_SELECT_BANK (2);
-	packet_number = SMC_inw (LAN91C96_FIFO);
-
-	if (packet_number & LAN91C96_FIFO_RXEMPTY) {
-		return 0;
-	}
-
-	PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME);
-	/*  start reading from the start of the packet */
-	SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
-			  LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
-
-	/* First two words are status and packet_length */
-#ifdef USE_32_BIT
-	stat_len = SMC_inl (LAN91C96_DATA_HIGH);
-	status = stat_len & 0xffff;
-	packet_length = stat_len >> 16;
-#else
-	status = SMC_inw (LAN91C96_DATA_HIGH);
-	packet_length = SMC_inw (LAN91C96_DATA_HIGH);
-#endif
-
-	packet_length &= 0x07ff;	/* mask off top bits */
-
-	PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length);
-
-	if (!(status & FRAME_FILTER)) {
-		/* Adjust for having already read the first two words */
-		packet_length -= 4;		/*4; */
-
-
-		/* set odd length for bug in LAN91C111, */
-		/* which never sets RS_ODDFRAME */
-		/* TODO ? */
-
-
-#ifdef USE_32_BIT
-		PRINTK3 (" Reading %d dwords (and %d bytes) \n",
-			 packet_length >> 2, packet_length & 3);
-		/* QUESTION:  Like in the TX routine, do I want
-		   to send the DWORDs or the bytes first, or some
-		   mixture.  A mixture might improve already slow PIO
-		   performance  */
-		SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2);
-		/* read the left over bytes */
-		if (packet_length & 3) {
-			int i;
-
-			byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3));
-			dword leftover = SMC_inl (LAN91C96_DATA_HIGH);
-
-			for (i = 0; i < (packet_length & 3); i++)
-				*tail++ = (byte) (leftover >> (8 * i)) & 0xff;
-		}
-#else
-		PRINTK3 (" Reading %d words and %d byte(s) \n",
-				 (packet_length >> 1), packet_length & 1);
-		SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1);
-
-#endif /* USE_32_BIT */
-
-#if	SMC_DEBUG > 2
-		printf ("Receiving Packet\n");
-		print_packet (NetRxPackets[0], packet_length);
-#endif
-	} else {
-		/* error ... */
-		/* TODO ? */
-		is_error = 1;
-	}
-
-	while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
-		udelay (1);		/* Wait until not busy */
-
-	/*  error or good, tell the card to get rid of this packet */
-	SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
-
-	while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
-		udelay (1);		/* Wait until not busy */
-
-	if (!is_error) {
-		/* Pass the packet up to the protocol layers. */
-		NetReceive (NetRxPackets[0], packet_length);
-		return packet_length;
-	} else {
-		return 0;
-	}
-
-}
-
-/*----------------------------------------------------
- * smc_close
- *
- * this makes the board clean up everything that it can
- * and not talk to the outside world.   Caused by
- * an 'ifconfig ethX down'
- *
- -----------------------------------------------------*/
-static int smc_close ()
-{
-	PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME);
-
-	/* clear everything */
-	smc_shutdown ();
-
-	return 0;
-}
-
-#if SMC_DEBUG > 2
-static void print_packet (byte * buf, int length)
-{
-}
-#endif /* SMC_DEBUG > 2 */
-
-int eth_init (bd_t * bd)
-{
-	return (smc_open(bd));
-}
-
-void eth_halt ()
-{
-	smc_close ();
-}
-
-int eth_rx ()
-{
-	return smc_rcv ();
-}
-
-int eth_send (volatile void *packet, int length)
-{
-	return smc_send_packet (packet, length);
-}
-
-
-
-#endif /* COMMANDS & CFG_NET */
-
-
-/* smc_get_ethaddr (bd_t * bd)
- *
- * This checks both the environment and the ROM for an ethernet address. If
- * found, the environment takes precedence.
- */
-
-int smc_get_ethaddr (bd_t * bd)
-{
-	int env_size = 0;
-	int rom_valid = 0;
-	int env_present = 0;
-	int reg = 0;
-	char *s = NULL;
-	char *e = NULL;
-	char *v_mac, es[] = "11:22:33:44:55:66";
-	char s_env_mac[64];
-	uchar v_env_mac[6];
-	uchar v_rom_mac[6];
-
-	env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
-	if (env_size != sizeof(es)) {	/* Ignore if env is bad or not set */
-		printf ("\n*** Warning: ethaddr is not set properly, ignoring!!\n");
-	} else {
-		env_present = 1;
-		s = s_env_mac;
-
-		for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
-			v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-	}
-
-	rom_valid = get_rom_mac (v_rom_mac);	/* get ROM mac value if any */
-
-	if (!env_present) {	/* if NO env */
-		if (rom_valid) {	/* but ROM is valid */
-			v_mac = (char *)v_rom_mac;
-			sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
-				 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
-				 v_mac[4], v_mac[5]);
-			setenv ("ethaddr", s_env_mac);
-		} else {	/* no env, bad ROM */
-			printf ("\n*** ERROR: ethaddr is NOT set !!\n");
-			return (-1);
-		}
-	} else {		/* good env, don't care ROM */
-		v_mac = (char *)v_env_mac;	/* always use a good env over a ROM */
-	}
-
-	if (env_present && rom_valid) { /* if both env and ROM are good */
-		if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
-			printf ("\nWarning: MAC addresses don't match:\n");
-			printf ("\tHW MAC address:  "
-				"%02X:%02X:%02X:%02X:%02X:%02X\n",
-				v_rom_mac[0], v_rom_mac[1],
-				v_rom_mac[2], v_rom_mac[3],
-				v_rom_mac[4], v_rom_mac[5] );
-			printf ("\t\"ethaddr\" value: "
-				"%02X:%02X:%02X:%02X:%02X:%02X\n",
-				v_env_mac[0], v_env_mac[1],
-				v_env_mac[2], v_env_mac[3],
-				v_env_mac[4], v_env_mac[5]) ;
-			debug ("### Set MAC addr from environment\n");
-		}
-	}
-	memcpy (bd->bi_enetaddr, v_mac, 6);	/* update global address to match env (allows env changing) */
-	smc_set_mac_addr ((unsigned char *)v_mac); /* use old function to update smc default */
-	PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
-		v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
-	return (0);
-}
-
-/*
- * get_rom_mac()
- * Note, this has omly been tested for the OMAP730 P2.
- */
-
-int get_rom_mac (unsigned char *v_rom_mac)
-{
-#ifdef HARDCODE_MAC	/* used for testing or to supress run time warnings */
-	char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
-
-	memcpy (v_rom_mac, hw_mac_addr, 6);
-	return (1);
-#else
-	int i;
-	SMC_SELECT_BANK (1);
-	for (i=0; i<6; i++)
-	{
-		v_rom_mac[i] = SMC_inb (LAN91C96_IA0 + i);
-	}
-	return (1);
-#endif
-}
-
-#endif /* CONFIG_DRIVER_LAN91C96 */
diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h
deleted file mode 100644
index 519c0c8389..0000000000
--- a/drivers/net/lan91c96.h
+++ /dev/null
@@ -1,635 +0,0 @@
-/*------------------------------------------------------------------------
- * lan91c96.h
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- *       Developed by Simple Network Magic Corporation (SNMC)
- * Copyright (C) 1996 by Erik Stahlman (ES)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * This file contains register information and access macros for
- * the LAN91C96 single chip ethernet controller.  It is a modified
- * version of the smc9111.h file.
- *
- * Information contained in this file was obtained from the LAN91C96
- * manual from SMC. To get a copy, if you really want one, you can find
- * information under www.smsc.com.
- *
- * Authors
- * 	Erik Stahlman				( erik@vt.edu )
- *	Daris A Nevil				( dnevil@snmc.com )
- *
- * History
- * 04/30/03	Mathijs Haarman		Modified smc91111.h (u-boot version)
- *		                        for lan91c96
- *-------------------------------------------------------------------------
- */
-#ifndef _LAN91C96_H_
-#define _LAN91C96_H_
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <config.h>
-
-/*
- * This function may be called by the board specific initialisation code
- * in order to override the default mac address.
- */
-
-void smc_set_mac_addr(const unsigned char *addr);
-
-
-/* I want some simple types */
-
-typedef unsigned char			byte;
-typedef unsigned short			word;
-typedef unsigned long int 		dword;
-
-/*
- * DEBUGGING LEVELS
- *
- * 0 for normal operation
- * 1 for slightly more details
- * >2 for various levels of increasingly useless information
- *    2 for interrupt tracking, status flags
- *    3 for packet info
- *    4 for complete packet dumps
- */
-/*#define SMC_DEBUG 0 */
-
-/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
-
-#define	SMC_IO_EXTENT	16
-
-#ifdef CONFIG_PXA250
-
-#ifdef	CONFIG_LUBBOCK
-#define	SMC_IO_SHIFT	2
-#undef	USE_32_BIT
-
-#else
-#define	SMC_IO_SHIFT	0
-#endif
-
-#define	SMCREG(r)	(SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT))
-
-#define	SMC_inl(r) 	(*((volatile dword *)SMCREG(r)))
-#define	SMC_inw(r) 	(*((volatile word *)SMCREG(r)))
-#define SMC_inb(p) ({ \
-	unsigned int __p = p; \
-	unsigned int __v = SMC_inw(__p & ~1); \
-	if (__p & 1) __v >>= 8; \
-	else __v &= 0xff; \
-	__v; })
-
-#define	SMC_outl(d,r)	(*((volatile dword *)SMCREG(r)) = d)
-#define	SMC_outw(d,r)	(*((volatile word *)SMCREG(r)) = d)
-#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
-				word __w = SMC_inw((r)&~1);  \
-				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
-				__w |= ((r)&1) ? __d<<8 : __d;  \
-				SMC_outw(__w,(r)&~1);  \
-			})
-
-#define SMC_outsl(r,b,l)	({	int __i; \
-					dword *__b2; \
-					__b2 = (dword *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outl( *(__b2 + __i), r ); \
-					} \
-				})
-
-#define SMC_outsw(r,b,l)	({	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outw( *(__b2 + __i), r ); \
-					} \
-				})
-
-#define SMC_insl(r,b,l) 	({	int __i ;  \
-					dword *__b2;  \
-					__b2 = (dword *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inl(r);  \
-					  SMC_inl(0);  \
-					};  \
-				})
-
-#define SMC_insw(r,b,l) 	({	int __i ;  \
-					word *__b2;  \
-					__b2 = (word *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inw(r);  \
-					  SMC_inw(0);  \
-					};  \
-				})
-
-#define SMC_insb(r,b,l) 	({	int __i ;  \
-					byte *__b2;  \
-					__b2 = (byte *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inb(r);  \
-					  SMC_inb(0);  \
-					};  \
-				})
-
-#else /* if not CONFIG_PXA250 */
-
-/*
- * We have only 16 Bit PCMCIA access on Socket 0
- */
-
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
-#define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
-
-#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
-#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
-				word __w = SMC_inw((r)&~1);  \
-				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
-				__w |= ((r)&1) ? __d<<8 : __d;  \
-				SMC_outw(__w,(r)&~1);  \
-			})
-#define SMC_outsw(r,b,l)	({	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outw( *(__b2 + __i), r); \
-					} \
-				})
-
-#define SMC_insw(r,b,l) 	({	int __i ;  \
-					word *__b2;  \
-					__b2 = (word *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inw(r);  \
-					  SMC_inw(0);  \
-					};  \
-				})
-
-#endif
-
-/*
- ****************************************************************************
- *	Bank Select Field
- ****************************************************************************
- */
-#define LAN91C96_BANK_SELECT  14       /* Bank Select Register */
-#define LAN91C96_BANKSELECT (0x3UC << 0)
-#define BANK0               0x00
-#define BANK1               0x01
-#define BANK2               0x02
-#define BANK3               0x03
-#define BANK4               0x04
-
-/*
- ****************************************************************************
- *	EEPROM Addresses.
- ****************************************************************************
- */
-#define EEPROM_MAC_OFFSET_1    0x6020
-#define EEPROM_MAC_OFFSET_2    0x6021
-#define EEPROM_MAC_OFFSET_3    0x6022
-
-/*
- ****************************************************************************
- *	Bank 0 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_TCR          0        /* Transmit Control Register */
-#define LAN91C96_EPH_STATUS   2        /* EPH Status Register */
-#define LAN91C96_RCR          4        /* Receive Control Register */
-#define LAN91C96_COUNTER      6        /* Counter Register */
-#define LAN91C96_MIR          8        /* Memory Information Register */
-#define LAN91C96_MCR          10       /* Memory Configuration Register */
-
-/*
- ****************************************************************************
- *	Transmit Control Register - Bank 0 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_TCR_TXENA        (0x1U << 0)
-#define LAN91C96_TCR_LOOP         (0x1U << 1)
-#define LAN91C96_TCR_FORCOL       (0x1U << 2)
-#define LAN91C96_TCR_TXP_EN       (0x1U << 3)
-#define LAN91C96_TCR_PAD_EN       (0x1U << 7)
-#define LAN91C96_TCR_NOCRC        (0x1U << 8)
-#define LAN91C96_TCR_MON_CSN      (0x1U << 10)
-#define LAN91C96_TCR_FDUPLX       (0x1U << 11)
-#define LAN91C96_TCR_STP_SQET     (0x1U << 12)
-#define LAN91C96_TCR_EPH_LOOP     (0x1U << 13)
-#define LAN91C96_TCR_ETEN_TYPE    (0x1U << 14)
-#define LAN91C96_TCR_FDSE         (0x1U << 15)
-
-/*
- ****************************************************************************
- *	EPH Status Register - Bank 0 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_EPHSR_TX_SUC     (0x1U << 0)
-#define LAN91C96_EPHSR_SNGL_COL   (0x1U << 1)
-#define LAN91C96_EPHSR_MUL_COL    (0x1U << 2)
-#define LAN91C96_EPHSR_LTX_MULT   (0x1U << 3)
-#define LAN91C96_EPHSR_16COL      (0x1U << 4)
-#define LAN91C96_EPHSR_SQET       (0x1U << 5)
-#define LAN91C96_EPHSR_LTX_BRD    (0x1U << 6)
-#define LAN91C96_EPHSR_TX_DEFR    (0x1U << 7)
-#define LAN91C96_EPHSR_WAKEUP     (0x1U << 8)
-#define LAN91C96_EPHSR_LATCOL     (0x1U << 9)
-#define LAN91C96_EPHSR_LOST_CARR  (0x1U << 10)
-#define LAN91C96_EPHSR_EXC_DEF    (0x1U << 11)
-#define LAN91C96_EPHSR_CTR_ROL    (0x1U << 12)
-
-#define LAN91C96_EPHSR_LINK_OK    (0x1U << 14)
-#define LAN91C96_EPHSR_TX_UNRN    (0x1U << 15)
-
-#define LAN91C96_EPHSR_ERRORS     (LAN91C96_EPHSR_SNGL_COL  |    \
-				   LAN91C96_EPHSR_MUL_COL   |    \
-				   LAN91C96_EPHSR_16COL     |    \
-				   LAN91C96_EPHSR_SQET      |    \
-				   LAN91C96_EPHSR_TX_DEFR   |    \
-				   LAN91C96_EPHSR_LATCOL    |    \
-				   LAN91C96_EPHSR_LOST_CARR |    \
-				   LAN91C96_EPHSR_EXC_DEF   |    \
-				   LAN91C96_EPHSR_LINK_OK   |    \
-				   LAN91C96_EPHSR_TX_UNRN)
-
-/*
- ****************************************************************************
- *	Receive Control Register - Bank 0 - Offset 4
- ****************************************************************************
- */
-#define LAN91C96_RCR_RX_ABORT     (0x1U << 0)
-#define LAN91C96_RCR_PRMS         (0x1U << 1)
-#define LAN91C96_RCR_ALMUL        (0x1U << 2)
-#define LAN91C96_RCR_RXEN         (0x1U << 8)
-#define LAN91C96_RCR_STRIP_CRC    (0x1U << 9)
-#define LAN91C96_RCR_FILT_CAR     (0x1U << 14)
-#define LAN91C96_RCR_SOFT_RST     (0x1U << 15)
-
-/*
- ****************************************************************************
- *	Counter Register - Bank 0 - Offset 6
- ****************************************************************************
- */
-#define LAN91C96_ECR_SNGL_COL     (0xFU << 0)
-#define LAN91C96_ECR_MULT_COL     (0xFU << 5)
-#define LAN91C96_ECR_DEF_TX       (0xFU << 8)
-#define LAN91C96_ECR_EXC_DEF_TX   (0xFU << 12)
-
-/*
- ****************************************************************************
- *	Memory Information Register - Bank 0 - OFfset 8
- ****************************************************************************
- */
-#define LAN91C96_MIR_SIZE        (0x18 << 0)    /* 6144 bytes */
-
-/*
- ****************************************************************************
- *	Memory Configuration Register - Bank 0 - Offset 10
- ****************************************************************************
- */
-#define LAN91C96_MCR_MEM_RES      (0xFFU << 0)
-#define LAN91C96_MCR_MEM_MULT     (0x3U << 9)
-#define LAN91C96_MCR_HIGH_ID      (0x3U << 12)
-
-#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
-
-/*
- ****************************************************************************
- *	Bank 1 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_CONFIG       0        /* Configuration Register */
-#define LAN91C96_BASE         2        /* Base Address Register */
-#define LAN91C96_IA0          4        /* Individual Address Register - 0 */
-#define LAN91C96_IA1          5        /* Individual Address Register - 1 */
-#define LAN91C96_IA2          6        /* Individual Address Register - 2 */
-#define LAN91C96_IA3          7        /* Individual Address Register - 3 */
-#define LAN91C96_IA4          8        /* Individual Address Register - 4 */
-#define LAN91C96_IA5          9        /* Individual Address Register - 5 */
-#define LAN91C96_GEN_PURPOSE  10       /* General Address Registers */
-#define LAN91C96_CONTROL      12       /* Control Register */
-
-/*
- ****************************************************************************
- *	Configuration Register - Bank 1 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_CR_INT_SEL0      (0x1U << 1)
-#define LAN91C96_CR_INT_SEL1      (0x1U << 2)
-#define LAN91C96_CR_RES           (0x3U << 3)
-#define LAN91C96_CR_DIS_LINK      (0x1U << 6)
-#define LAN91C96_CR_16BIT         (0x1U << 7)
-#define LAN91C96_CR_AUI_SELECT    (0x1U << 8)
-#define LAN91C96_CR_SET_SQLCH     (0x1U << 9)
-#define LAN91C96_CR_FULL_STEP     (0x1U << 10)
-#define LAN91C96_CR_NO_WAIT       (0x1U << 12)
-
-/*
- ****************************************************************************
- *	Base Address Register - Bank 1 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_BAR_RA_BITS      (0x27U << 0)
-#define LAN91C96_BAR_ROM_SIZE     (0x1U << 6)
-#define LAN91C96_BAR_A_BITS       (0xFFU << 8)
-
-/*
- ****************************************************************************
- *	Control Register - Bank 1 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_CTR_STORE        (0x1U << 0)
-#define LAN91C96_CTR_RELOAD       (0x1U << 1)
-#define LAN91C96_CTR_EEPROM       (0x1U << 2)
-#define LAN91C96_CTR_TE_ENABLE    (0x1U << 5)
-#define LAN91C96_CTR_CR_ENABLE    (0x1U << 6)
-#define LAN91C96_CTR_LE_ENABLE    (0x1U << 7)
-#define LAN91C96_CTR_BIT_8        (0x1U << 8)
-#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
-#define LAN91C96_CTR_WAKEUP_EN    (0x1U << 12)
-#define LAN91C96_CTR_PWRDN        (0x1U << 13)
-#define LAN91C96_CTR_RCV_BAD      (0x1U << 14)
-
-/*
- ****************************************************************************
- *	Bank 2 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_MMU            0      /* MMU Command Register */
-#define LAN91C96_AUTO_TX_START  1      /* Auto Tx Start Register */
-#define LAN91C96_PNR            2      /* Packet Number Register */
-#define LAN91C96_ARR            3      /* Allocation Result Register */
-#define LAN91C96_FIFO           4      /* FIFO Ports Register */
-#define LAN91C96_POINTER        6      /* Pointer Register */
-#define LAN91C96_DATA_HIGH      8      /* Data High Register */
-#define LAN91C96_DATA_LOW       10     /* Data Low Register */
-#define LAN91C96_INT_STATS      12     /* Interrupt Status Register - RO */
-#define LAN91C96_INT_ACK        12     /* Interrupt Acknowledge Register -WO */
-#define LAN91C96_INT_MASK       13     /* Interrupt Mask Register */
-
-/*
- ****************************************************************************
- *	MMU Command Register - Bank 2 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_MMUCR_NO_BUSY    (0x1U << 0)
-#define LAN91C96_MMUCR_N1         (0x1U << 1)
-#define LAN91C96_MMUCR_N2         (0x1U << 2)
-#define LAN91C96_MMUCR_COMMAND    (0xFU << 4)
-#define LAN91C96_MMUCR_ALLOC_TX   (0x2U << 4)    /* WXYZ = 0010 */
-#define LAN91C96_MMUCR_RESET_MMU  (0x4U << 4)    /* WXYZ = 0100 */
-#define LAN91C96_MMUCR_REMOVE_RX  (0x6U << 4)    /* WXYZ = 0110 */
-#define LAN91C96_MMUCR_REMOVE_TX  (0x7U << 4)    /* WXYZ = 0111 */
-#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4)    /* WXYZ = 1000 */
-#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4)    /* WXYZ = 1010 */
-#define LAN91C96_MMUCR_ENQUEUE    (0xCU << 4)    /* WXYZ = 1100 */
-#define LAN91C96_MMUCR_RESET_TX   (0xEU << 4)    /* WXYZ = 1110 */
-
-/*
- ****************************************************************************
- *	Auto Tx Start Register - Bank 2 - Offset 1
- ****************************************************************************
- */
-#define LAN91C96_AUTOTX           (0xFFU << 0)
-
-/*
- ****************************************************************************
- *	Packet Number Register - Bank 2 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_PNR_TX           (0x1FU << 0)
-
-/*
- ****************************************************************************
- *	Allocation Result Register - Bank 2 - Offset 3
- ****************************************************************************
- */
-#define LAN91C96_ARR_ALLOC_PN     (0x7FU << 0)
-#define LAN91C96_ARR_FAILED       (0x1U << 7)
-
-/*
- ****************************************************************************
- *	FIFO Ports Register - Bank 2 - Offset 4
- ****************************************************************************
- */
-#define LAN91C96_FIFO_TX_DONE_PN  (0x1FU << 0)
-#define LAN91C96_FIFO_TEMPTY      (0x1U << 7)
-#define LAN91C96_FIFO_RX_DONE_PN  (0x1FU << 8)
-#define LAN91C96_FIFO_RXEMPTY     (0x1U << 15)
-
-/*
- ****************************************************************************
- *	Pointer Register - Bank 2 - Offset 6
- ****************************************************************************
- */
-#define LAN91C96_PTR_LOW          (0xFFU << 0)
-#define LAN91C96_PTR_HIGH         (0x7U << 8)
-#define LAN91C96_PTR_AUTO_TX      (0x1U << 11)
-#define LAN91C96_PTR_ETEN         (0x1U << 12)
-#define LAN91C96_PTR_READ         (0x1U << 13)
-#define LAN91C96_PTR_AUTO_INCR    (0x1U << 14)
-#define LAN91C96_PTR_RCV          (0x1U << 15)
-
-#define LAN91C96_PTR_RX_FRAME     (LAN91C96_PTR_RCV       |    \
-				   LAN91C96_PTR_AUTO_INCR |    \
-				   LAN91C96_PTR_READ)
-
-/*
- ****************************************************************************
- *	Data Register - Bank 2 - Offset 8
- ****************************************************************************
- */
-#define LAN91C96_CONTROL_CRC      (0x1U << 4)    /* CRC bit */
-#define LAN91C96_CONTROL_ODD      (0x1U << 5)    /* ODD bit */
-
-/*
- ****************************************************************************
- *	Interrupt Status Register - Bank 2 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_IST_RCV_INT      (0x1U << 0)
-#define LAN91C96_IST_TX_INT       (0x1U << 1)
-#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_IST_ALLOC_INT    (0x1U << 3)
-#define LAN91C96_IST_RX_OVRN_INT  (0x1U << 4)
-#define LAN91C96_IST_EPH_INT      (0x1U << 5)
-#define LAN91C96_IST_ERCV_INT     (0x1U << 6)
-#define LAN91C96_IST_RX_IDLE_INT  (0x1U << 7)
-
-/*
- ****************************************************************************
- *	Interrupt Acknowledge Register - Bank 2 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_ACK_TX_INT       (0x1U << 1)
-#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_ACK_RX_OVRN_INT  (0x1U << 4)
-#define LAN91C96_ACK_ERCV_INT     (0x1U << 6)
-
-/*
- ****************************************************************************
- *	Interrupt Mask Register - Bank 2 - Offset 13
- ****************************************************************************
- */
-#define LAN91C96_MSK_RCV_INT      (0x1U << 0)
-#define LAN91C96_MSK_TX_INT       (0x1U << 1)
-#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_MSK_ALLOC_INT    (0x1U << 3)
-#define LAN91C96_MSK_RX_OVRN_INT  (0x1U << 4)
-#define LAN91C96_MSK_EPH_INT      (0x1U << 5)
-#define LAN91C96_MSK_ERCV_INT     (0x1U << 6)
-#define LAN91C96_MSK_TX_IDLE_INT  (0x1U << 7)
-
-/*
- ****************************************************************************
- *	Bank 3 Register Map in I/O Space
- **************************************************************************
- */
-#define LAN91C96_MGMT_MDO         (0x1U << 0)
-#define LAN91C96_MGMT_MDI         (0x1U << 1)
-#define LAN91C96_MGMT_MCLK        (0x1U << 2)
-#define LAN91C96_MGMT_MDOE        (0x1U << 3)
-#define LAN91C96_MGMT_LOW_ID      (0x3U << 4)
-#define LAN91C96_MGMT_IOS0        (0x1U << 8)
-#define LAN91C96_MGMT_IOS1        (0x1U << 9)
-#define LAN91C96_MGMT_IOS2        (0x1U << 10)
-#define LAN91C96_MGMT_nXNDEC      (0x1U << 11)
-#define LAN91C96_MGMT_HIGH_ID     (0x3U << 12)
-
-/*
- ****************************************************************************
- *	Revision Register - Bank 3 - Offset 10
- ****************************************************************************
- */
-#define LAN91C96_REV_REVID        (0xFU << 0)
-#define LAN91C96_REV_CHIPID       (0xFU << 4)
-
-/*
- ****************************************************************************
- *	Early RCV Register - Bank 3 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_ERCV_THRESHOLD   (0x1FU << 0)
-#define LAN91C96_ERCV_RCV_DISCRD  (0x1U << 7)
-
-/*
- ****************************************************************************
- *	PCMCIA Configuration Registers
- ****************************************************************************
- */
-#define LAN91C96_ECOR    0x8000        /* Ethernet Configuration Register */
-#define LAN91C96_ECSR    0x8002        /* Ethernet Configuration and Status */
-
-/*
- ****************************************************************************
- *	PCMCIA Ethernet Configuration Option Register (ECOR)
- ****************************************************************************
- */
-#define LAN91C96_ECOR_ENABLE       (0x1U << 0)
-#define LAN91C96_ECOR_WR_ATTRIB    (0x1U << 2)
-#define LAN91C96_ECOR_LEVEL_REQ    (0x1U << 6)
-#define LAN91C96_ECOR_SRESET       (0x1U << 7)
-
-/*
- ****************************************************************************
- *	PCMCIA Ethernet Configuration and Status Register (ECSR)
- ****************************************************************************
- */
-#define LAN91C96_ECSR_INTR        (0x1U << 1)
-#define LAN91C96_ECSR_PWRDWN      (0x1U << 2)
-#define LAN91C96_ECSR_IOIS8       (0x1U << 5)
-
-/*
- ****************************************************************************
- *	Receive Frame Status Word - See page 38 of the LAN91C96 specification.
- ****************************************************************************
- */
-#define LAN91C96_TOO_SHORT        (0x1U << 10)
-#define LAN91C96_TOO_LONG         (0x1U << 11)
-#define LAN91C96_ODD_FRM          (0x1U << 12)
-#define LAN91C96_BAD_CRC          (0x1U << 13)
-#define LAN91C96_BROD_CAST        (0x1U << 14)
-#define LAN91C96_ALGN_ERR         (0x1U << 15)
-
-#define FRAME_FILTER              (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG  | LAN91C96_BAD_CRC   | LAN91C96_ALGN_ERR)
-
-/*
- ****************************************************************************
- *	Default MAC Address
- ****************************************************************************
- */
-#define MAC_DEF_HI  0x0800
-#define MAC_DEF_MED 0x3333
-#define MAC_DEF_LO  0x0100
-
-/*
- ****************************************************************************
- *	Default I/O Signature - 0x33
- ****************************************************************************
- */
-#define LAN91C96_LOW_SIGNATURE        (0x33U << 0)
-#define LAN91C96_HIGH_SIGNATURE       (0x33U << 8)
-#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
-
-#define LAN91C96_MAX_PAGES     6        /* Maximum number of 256 pages. */
-#define ETHERNET_MAX_LENGTH 1514
-
-
-/*-------------------------------------------------------------------------
- *  I define some macros to make it easier to do somewhat common
- * or slightly complicated, repeated tasks.
- *-------------------------------------------------------------------------
- */
-
-/* select a register bank, 0 to 3  */
-
-#define SMC_SELECT_BANK(x)  { SMC_outw( x, LAN91C96_BANK_SELECT ); }
-
-/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) {\
-		unsigned char mask;\
-		SMC_SELECT_BANK(2);\
-		mask = SMC_inb( LAN91C96_INT_MASK );\
-		mask |= (x);\
-		SMC_outb( mask, LAN91C96_INT_MASK ); \
-}
-
-/* this disables an interrupt from the interrupt mask register */
-
-#define SMC_DISABLE_INT(x) {\
-		unsigned char mask;\
-		SMC_SELECT_BANK(2);\
-		mask = SMC_inb( LAN91C96_INT_MASK );\
-		mask &= ~(x);\
-		SMC_outb( mask, LAN91C96_INT_MASK ); \
-}
-
-/*----------------------------------------------------------------------
- * Define the interrupts that I want to receive from the card
- *
- * I want:
- *  LAN91C96_IST_EPH_INT, for nasty errors
- *  LAN91C96_IST_RCV_INT, for happy received packets
- *  LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
- *-------------------------------------------------------------------------
- */
-#define SMC_INTERRUPT_MASK   (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
-
-#endif  /* _LAN91C96_H_ */
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
deleted file mode 100644
index b92c7864b5..0000000000
--- a/drivers/net/ne2000.c
+++ /dev/null
@@ -1,961 +0,0 @@
-/*
-Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-
-==========================================================================
-
-dev/if_dp83902a.c
-
-Ethernet device driver for NS DP83902a ethernet controller
-
-==========================================================================
-####ECOSGPLCOPYRIGHTBEGIN####
--------------------------------------------
-This file is part of eCos, the Embedded Configurable Operating System.
-Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
-eCos is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2 or (at your option) any later version.
-
-eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-for more details.
-
-You should have received a copy of the GNU General Public License along
-with eCos; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
-As a special exception, if other files instantiate templates or use macros
-or inline functions from this file, or you compile this file and link it
-with other works to produce a work based on this file, this file does not
-by itself cause the resulting work to be covered by the GNU General Public
-License. However the source code for this file must still be made available
-in accordance with section (3) of the GNU General Public License.
-
-This exception does not invalidate any other reasons why a work based on
-this file might be covered by the GNU General Public License.
-
-Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-at http://sources.redhat.com/ecos/ecos-license/
--------------------------------------------
-####ECOSGPLCOPYRIGHTEND####
-####BSDCOPYRIGHTBEGIN####
-
--------------------------------------------
-
-Portions of this software may have been derived from OpenBSD or other sources,
-and are covered by the appropriate copyright disclaimers included herein.
-
--------------------------------------------
-
-####BSDCOPYRIGHTEND####
-==========================================================================
-#####DESCRIPTIONBEGIN####
-
-Author(s):    gthomas
-Contributors: gthomas, jskov, rsandifo
-Date:	      2001-06-13
-Purpose:
-Description:
-
-FIXME:	      Will fail if pinged with large packets (1520 bytes)
-Add promisc config
-Add SNMP
-
-####DESCRIPTIONEND####
-
-
-==========================================================================
-
-*/
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <malloc.h>
-
-#ifdef CONFIG_DRIVER_NE2000
-
-/* wor around udelay resetting OCR */
-static void my_udelay(long us) {
-	long tmo;
-
-	tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */
-	while (get_timer (0) < tmo);
-}
-
-#define mdelay(n)       my_udelay((n)*1000)
-
-/* forward definition of function used for the uboot interface */
-void uboot_push_packet_len(int len);
-void uboot_push_tx_done(int key, int val);
-
-/* timeout for tx/rx in s */
-#define TOUT 5
-
-#define ETHER_ADDR_LEN 6
-
-/*
-  ------------------------------------------------------------------------
-  Debugging details
-
-  Set to perms of:
-  0 disables all debug output
-  1 for process debug output
-  2 for added data IO output: get_reg, put_reg
-  4 for packet allocation/free output
-  8 for only startup status, so we can tell we're installed OK
-*/
-/*#define DEBUG 0xf*/
-#define DEBUG 0
-
-#if DEBUG & 1
-#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
-#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
-#else
-#define DEBUG_FUNCTION() do {} while(0)
-#define DEBUG_LINE() do {} while(0)
-#endif
-
-#include "ne2000.h"
-
-#if DEBUG & 1
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-static dp83902a_priv_data_t nic; /* just one instance of the card supported */
-
-static bool
-dp83902a_init(void)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	cyg_uint8* base;
-	int i;
-
-	DEBUG_FUNCTION();
-
-	base = dp->base;
-	if (!base) return false;  /* No device found */
-
-	DEBUG_LINE();
-
-	/* Prepare ESA */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);  /* Select page 1 */
-	/* Use the address from the serial EEPROM */
-	for (i = 0; i < 6; i++)
-		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);  /* Select page 0 */
-
-	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
-	       "eeprom",
-	       dp->esa[0],
-	       dp->esa[1],
-	       dp->esa[2],
-	       dp->esa[3],
-	       dp->esa[4],
-	       dp->esa[5] );
-
-	return true;
-}
-
-static void
-dp83902a_stop(void)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	cyg_uint8 *base = dp->base;
-
-	DEBUG_FUNCTION();
-
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);  /* Brutal */
-	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
-	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
-
-	dp->running = false;
-}
-
-/*
-  This function is called to "start up" the interface.  It may be called
-  multiple times, even when the hardware is already running.  It will be
-  called whenever something "hardware oriented" changes and should leave
-  the hardware ready to send/receive packets.
-*/
-static void
-dp83902a_start(unsigned char * enaddr)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	cyg_uint8 *base = dp->base;
-	int i;
-
-	DEBUG_FUNCTION();
-
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
-	DP_OUT(base, DP_DCR, DP_DCR_INIT);
-	DP_OUT(base, DP_RBCH, 0);		/* Remote byte count */
-	DP_OUT(base, DP_RBCL, 0);
-	DP_OUT(base, DP_RCR, DP_RCR_MON);	/* Accept no packets */
-	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);	/* Transmitter [virtually] off */
-	DP_OUT(base, DP_TPSR, dp->tx_buf1);	/* Transmitter start page */
-	dp->tx1 = dp->tx2 = 0;
-	dp->tx_next = dp->tx_buf1;
-	dp->tx_started = false;
-	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
-	DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */
-	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
-	dp->rx_next = dp->rx_buf_start-1;
-	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
-	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);  /* Select page 1 */
-	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);   /* Current page - next free page for Rx */
-	for (i = 0;  i < ETHER_ADDR_LEN;  i++) {
-		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
-	}
-	/* Enable and start device */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
-	DP_OUT(base, DP_RCR, DP_RCR_AB);  /* Accept broadcast, no errors, no multicast */
-	dp->running = true;
-}
-
-/*
-  This routine is called to start the transmitter.  It is split out from the
-  data handling routine so it may be called either when data becomes first
-  available or when an Tx interrupt occurs
-*/
-
-static void
-dp83902a_start_xmit(int start_page, int len)
-{
-	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
-	cyg_uint8 *base = dp->base;
-
-	DEBUG_FUNCTION();
-
-#if DEBUG & 1
-	printf("Tx pkt %d len %d\n", start_page, len);
-	if (dp->tx_started)
-		printf("TX already started?!?\n");
-#endif
-
-	DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_TBCL, len & 0xFF);
-	DP_OUT(base, DP_TBCH, len >> 8);
-	DP_OUT(base, DP_TPSR, start_page);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-
-	dp->tx_started = true;
-}
-
-/*
-  This routine is called to send data to the hardware.  It is known a-priori
-  that there is free buffer space (dp->tx_next).
-*/
-static void
-dp83902a_send(unsigned char *data, int total_len, unsigned long key)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	int len, start_page, pkt_len, i, isr;
-#if DEBUG & 4
-	int dx;
-#endif
-
-	DEBUG_FUNCTION();
-
-	len = pkt_len = total_len;
-	if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME;
-
-	start_page = dp->tx_next;
-	if (dp->tx_next == dp->tx_buf1) {
-		dp->tx1 = start_page;
-		dp->tx1_len = pkt_len;
-		dp->tx1_key = key;
-		dp->tx_next = dp->tx_buf2;
-	} else {
-		dp->tx2 = start_page;
-		dp->tx2_len = pkt_len;
-		dp->tx2_key = key;
-		dp->tx_next = dp->tx_buf1;
-	}
-
-#if DEBUG & 5
-	printf("TX prep page %d len %d\n", start_page, pkt_len);
-#endif
-
-	DP_OUT(base, DP_ISR, DP_ISR_RDC);  /* Clear end of DMA */
-	{
-		/* Dummy read. The manual sez something slightly different, */
-		/* but the code is extended a bit to do what Hitachi's monitor */
-		/* does (i.e., also read data). */
-
-		cyg_uint16 tmp;
-		int len = 1;
-
-		DP_OUT(base, DP_RSAL, 0x100-len);
-		DP_OUT(base, DP_RSAH, (start_page-1) & 0xff);
-		DP_OUT(base, DP_RBCL, len);
-		DP_OUT(base, DP_RBCH, 0);
-		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
-		DP_IN_DATA(dp->data, tmp);
-	}
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/* Stall for a bit before continuing to work around random data */
-	/* corruption problems on some platforms. */
-	CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
-	/* Send data to device buffer(s) */
-	DP_OUT(base, DP_RSAL, 0);
-	DP_OUT(base, DP_RSAH, start_page);
-	DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
-	DP_OUT(base, DP_RBCH, pkt_len >> 8);
-	DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
-
-	/* Put data into buffer */
-#if DEBUG & 4
-	printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len);
-	dx = 0;
-#endif
-	while (len > 0) {
-#if DEBUG & 4
-		printf(" %02x", *data);
-		if (0 == (++dx % 16)) printf("\n ");
-#endif
-		DP_OUT_DATA(dp->data, *data++);
-		len--;
-	}
-#if DEBUG & 4
-	printf("\n");
-#endif
-	if (total_len < pkt_len) {
-#if DEBUG & 4
-		printf("  + %d bytes of padding\n", pkt_len - total_len);
-#endif
-		/* Padding to 802.3 length was required */
-		for (i = total_len;  i < pkt_len;) {
-			i++;
-			DP_OUT_DATA(dp->data, 0);
-		}
-	}
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/* After last data write, delay for a bit before accessing the */
-	/* device again, or we may get random data corruption in the last */
-	/* datum (on some platforms). */
-	CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
-	/* Wait for DMA to complete */
-	do {
-		DP_IN(base, DP_ISR, isr);
-	} while ((isr & DP_ISR_RDC) == 0);
-	/* Then disable DMA */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-
-	/* Start transmit if not already going */
-	if (!dp->tx_started) {
-		if (start_page == dp->tx1) {
-			dp->tx_int = 1;  /* Expecting interrupt from BUF1 */
-		} else {
-			dp->tx_int = 2;  /* Expecting interrupt from BUF2 */
-		}
-		dp83902a_start_xmit(start_page, pkt_len);
-	}
-}
-
-/*
-  This function is called when a packet has been received.  It's job is
-  to prepare to unload the packet from the hardware.  Once the length of
-  the packet is known, the upper layer of the driver can be told.  When
-  the upper layer is ready to unload the packet, the internal function
-  'dp83902a_recv' will be called to actually fetch it from the hardware.
-*/
-static void
-dp83902a_RxEvent(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	unsigned char rsr;
-	unsigned char rcv_hdr[4];
-	int i, len, pkt, cur;
-
-	DEBUG_FUNCTION();
-
-	DP_IN(base, DP_RSR, rsr);
-	while (true) {
-		/* Read incoming packet header */
-		DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
-		DP_IN(base, DP_P1_CURP, cur);
-		DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-		DP_IN(base, DP_BNDRY, pkt);
-
-		pkt += 1;
-		if (pkt == dp->rx_buf_end)
-			pkt = dp->rx_buf_start;
-
-		if (pkt == cur) {
-			break;
-		}
-		DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
-		DP_OUT(base, DP_RBCH, 0);
-		DP_OUT(base, DP_RSAL, 0);
-		DP_OUT(base, DP_RSAH, pkt);
-		if (dp->rx_next == pkt) {
-			if (cur == dp->rx_buf_start)
-				DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
-			else
-				DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */
-			return;
-		}
-		dp->rx_next = pkt;
-		DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
-		DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
-		CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
-		for (i = 0;  i < sizeof(rcv_hdr);) {
-			DP_IN_DATA(dp->data, rcv_hdr[i++]);
-		}
-
-#if DEBUG & 5
-		printf("rx hdr %02x %02x %02x %02x\n",
-		       rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
-#endif
-		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
-		uboot_push_packet_len(len);
-		if (rcv_hdr[1] == dp->rx_buf_start)
-			DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
-		else
-			DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */
-	}
-}
-
-/*
-  This function is called as a result of the "eth_drv_recv()" call above.
-  It's job is to actually fetch data for a packet from the hardware once
-  memory buffers have been allocated for the packet.  Note that the buffers
-  may come in pieces, using a scatter-gather list.  This allows for more
-  efficient processing in the upper layers of the stack.
-*/
-static void
-dp83902a_recv(unsigned char *data, int len)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	int i, mlen;
-	cyg_uint8 saved_char = 0;
-	bool saved;
-#if DEBUG & 4
-	int dx;
-#endif
-
-	DEBUG_FUNCTION();
-
-#if DEBUG & 5
-	printf("Rx packet %d length %d\n", dp->rx_next, len);
-#endif
-
-	/* Read incoming packet data */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_RBCL, len & 0xFF);
-	DP_OUT(base, DP_RBCH, len >> 8);
-	DP_OUT(base, DP_RSAL, 4);		/* Past header */
-	DP_OUT(base, DP_RSAH, dp->rx_next);
-	DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
-	DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
-	CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
-	saved = false;
-	for (i = 0;  i < 1;  i++) {
-		if (data) {
-			mlen = len;
-#if DEBUG & 4
-			printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen);
-			dx = 0;
-#endif
-			while (0 < mlen) {
-				/* Saved byte from previous loop? */
-				if (saved) {
-					*data++ = saved_char;
-					mlen--;
-					saved = false;
-					continue;
-				}
-
-				{
-					cyg_uint8 tmp;
-					DP_IN_DATA(dp->data, tmp);
-#if DEBUG & 4
-					printf(" %02x", tmp);
-					if (0 == (++dx % 16)) printf("\n ");
-#endif
-					*data++ = tmp;;
-					mlen--;
-				}
-			}
-#if DEBUG & 4
-			printf("\n");
-#endif
-		}
-	}
-}
-
-static void
-dp83902a_TxEvent(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	unsigned char tsr;
-	unsigned long key;
-
-	DEBUG_FUNCTION();
-
-	DP_IN(base, DP_TSR, tsr);
-	if (dp->tx_int == 1) {
-		key = dp->tx1_key;
-		dp->tx1 = 0;
-	} else {
-		key = dp->tx2_key;
-		dp->tx2 = 0;
-	}
-	/* Start next packet if one is ready */
-	dp->tx_started = false;
-	if (dp->tx1) {
-		dp83902a_start_xmit(dp->tx1, dp->tx1_len);
-		dp->tx_int = 1;
-	} else if (dp->tx2) {
-		dp83902a_start_xmit(dp->tx2, dp->tx2_len);
-		dp->tx_int = 2;
-	} else {
-		dp->tx_int = 0;
-	}
-	/* Tell higher level we sent this packet */
-	uboot_push_tx_done(key, 0);
-}
-
-/* Read the tally counters to clear them.  Called in response to a CNT */
-/* interrupt. */
-static void
-dp83902a_ClearCounters(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	cyg_uint8 cnt1, cnt2, cnt3;
-
-	DP_IN(base, DP_FER, cnt1);
-	DP_IN(base, DP_CER, cnt2);
-	DP_IN(base, DP_MISSED, cnt3);
-	DP_OUT(base, DP_ISR, DP_ISR_CNT);
-}
-
-/* Deal with an overflow condition.  This code follows the procedure set */
-/* out in section 7.0 of the datasheet. */
-static void
-dp83902a_Overflow(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
-	cyg_uint8 *base = dp->base;
-	cyg_uint8 isr;
-
-	/* Issue a stop command and wait 1.6ms for it to complete. */
-	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
-	CYGACC_CALL_IF_DELAY_US(1600);
-
-	/* Clear the remote byte counter registers. */
-	DP_OUT(base, DP_RBCL, 0);
-	DP_OUT(base, DP_RBCH, 0);
-
-	/* Enter loopback mode while we clear the buffer. */
-	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
-	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
-
-	/* Read in as many packets as we can and acknowledge any and receive */
-	/* interrupts.  Since the buffer has overflowed, a receive event of */
-	/* some kind will have occured. */
-	dp83902a_RxEvent();
-	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
-
-	/* Clear the overflow condition and leave loopback mode. */
-	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
-	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
-
-	/* If a transmit command was issued, but no transmit event has occured, */
-	/* restart it here. */
-	DP_IN(base, DP_ISR, isr);
-	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
-		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-	}
-}
-
-static void
-dp83902a_poll(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	cyg_uint8 *base = dp->base;
-	unsigned char isr;
-
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
-	DP_IN(base, DP_ISR, isr);
-	while (0 != isr) {
-		/* The CNT interrupt triggers when the MSB of one of the error */
-		/* counters is set.  We don't much care about these counters, but */
-		/* we should read their values to reset them. */
-		if (isr & DP_ISR_CNT) {
-			dp83902a_ClearCounters();
-		}
-		/* Check for overflow.  It's a special case, since there's a */
-		/* particular procedure that must be followed to get back into */
-		/* a running state.a */
-		if (isr & DP_ISR_OFLW) {
-			dp83902a_Overflow();
-		} else {
-			/* Other kinds of interrupts can be acknowledged simply by */
-			/* clearing the relevant bits of the ISR.  Do that now, then */
-			/* handle the interrupts we care about. */
-			DP_OUT(base, DP_ISR, isr);      /* Clear set bits */
-			if (!dp->running) break;	/* Is this necessary? */
-			/* Check for tx_started on TX event since these may happen */
-			/* spuriously it seems. */
-			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
-				dp83902a_TxEvent();
-			}
-			if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
-				dp83902a_RxEvent();
-			}
-		}
-		DP_IN(base, DP_ISR, isr);
-	}
-}
-
-/* find prom (taken from pc_net_cs.c from Linux) */
-
-#include "8390.h"
-
-typedef struct hw_info_t {
-	u_int	offset;
-	u_char	a0, a1, a2;
-	u_int	flags;
-} hw_info_t;
-
-#define DELAY_OUTPUT	0x01
-#define HAS_MISC_REG	0x02
-#define USE_BIG_BUF	0x04
-#define HAS_IBM_MISC	0x08
-#define IS_DL10019	0x10
-#define IS_DL10022	0x20
-#define HAS_MII		0x40
-#define USE_SHMEM	0x80	/* autodetected */
-
-#define AM79C9XX_HOME_PHY	0x00006B90  /* HomePNA PHY */
-#define AM79C9XX_ETH_PHY	0x00006B70  /* 10baseT PHY */
-#define MII_PHYID_REV_MASK	0xfffffff0
-#define MII_PHYID_REG1		0x02
-#define MII_PHYID_REG2		0x03
-
-static hw_info_t hw_info[] = {
-	{ /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT },
-	{ /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 },
-	{ /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 },
-	{ /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94,
-	  DELAY_OUTPUT | HAS_IBM_MISC },
-	{ /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 },
-	{ /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 },
-	{ /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 },
-	{ /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 },
-	{ /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 },
-	{ /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 },
-	{ /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 },
-	{ /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 },
-	{ /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* IBM FME */ 0x0374, 0x00, 0x04, 0xac,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 },
-	{ /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 },
-	{ /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 },
-	{ /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 },
-	{ /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 },
-	{ /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 },
-	{ /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45,
-	  HAS_MISC_REG | HAS_IBM_MISC },
-	{ /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 },
-	{ /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 },
-	{ /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 },
-	{ /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b,
-	  DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF },
-	{ /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 },
-	{ /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
-	{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
-	{ /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
-	{ /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 }
-};
-
-#define NR_INFO		(sizeof(hw_info)/sizeof(hw_info_t))
-
-static hw_info_t default_info = { 0, 0, 0, 0, 0 };
-
-unsigned char dev_addr[6];
-
-#define PCNET_CMD	0x00
-#define PCNET_DATAPORT	0x10	/* NatSemi-defined port window offset. */
-#define PCNET_RESET	0x1f	/* Issue a read to reset, a write to clear. */
-#define PCNET_MISC	0x18	/* For IBM CCAE and Socket EA cards */
-
-unsigned long nic_base;
-
-static void pcnet_reset_8390(void)
-{
-	int i, r;
-
-	PRINTK("nic base is %lx\n", nic_base);
-
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-
-	n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET);
-
-	for (i = 0; i < 100; i++) {
-		if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
-			break;
-		PRINTK("got %x in reset\n", r);
-		my_udelay(100);
-	}
-	n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
-
-	if (i == 100)
-		printf("pcnet_reset_8390() did not complete.\n");
-} /* pcnet_reset_8390 */
-
-static hw_info_t * get_prom(void ) {
-	unsigned char prom[32];
-	int i, j;
-	struct {
-		u_char value, offset;
-	} program_seq[] = {
-		{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
-		{0x48,	EN0_DCFG},	/* Set byte-wide (0x48) access. */
-		{0x00,	EN0_RCNTLO},	/* Clear the count regs. */
-		{0x00,	EN0_RCNTHI},
-		{0x00,	EN0_IMR},	/* Mask completion irq. */
-		{0xFF,	EN0_ISR},
-		{E8390_RXOFF, EN0_RXCR},	/* 0x20  Set to monitor */
-		{E8390_TXOFF, EN0_TXCR},	/* 0x02  and loopback mode. */
-		{32,	EN0_RCNTLO},
-		{0x00,	EN0_RCNTHI},
-		{0x00,	EN0_RSARLO},	/* DMA starting at 0x0000. */
-		{0x00,	EN0_RSARHI},
-		{E8390_RREAD+E8390_START, E8390_CMD},
-	};
-
-	PRINTK("trying to get MAC via prom reading\n");
-
-	pcnet_reset_8390();
-
-	mdelay(10);
-
-	for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
-		n2k_outb(program_seq[i].value, program_seq[i].offset);
-
-	PRINTK("PROM:");
-	for (i = 0; i < 32; i++) {
-		prom[i] = n2k_inb(PCNET_DATAPORT);
-		PRINTK(" %02x", prom[i]);
-	}
-	PRINTK("\n");
-	for (i = 0; i < NR_INFO; i++) {
-		if ((prom[0] == hw_info[i].a0) &&
-		    (prom[2] == hw_info[i].a1) &&
-		    (prom[4] == hw_info[i].a2)) {
-			PRINTK("matched board %d\n", i);
-			break;
-		}
-	}
-	if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
-		for (j = 0; j < 6; j++)
-			dev_addr[j] = prom[j<<1];
-		PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
-		PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n",
-		       dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]);
-		return (i < NR_INFO) ? hw_info+i : &default_info;
-	}
-	return NULL;
-}
-
-/* U-boot specific routines */
-
-#define NB 5
-
-static unsigned char *pbuf = NULL;
-static int plen[NB];
-static int nrx = 0;
-
-static int pkey = -1;
-
-void uboot_push_packet_len(int len) {
-	PRINTK("pushed len = %d, nrx = %d\n", len, nrx);
-	if (len>=2000) {
-		printf("NE2000: packet too big\n");
-		return;
-	}
-	if (nrx >= NB) {
-		printf("losing packets in rx\n");
-		return;
-	}
-	plen[nrx] = len;
-	dp83902a_recv(&pbuf[nrx*2000], len);
-	nrx++;
-}
-
-void uboot_push_tx_done(int key, int val) {
-	PRINTK("pushed key = %d\n", key);
-	pkey = key;
-}
-
-int eth_init(bd_t *bd) {
-	static hw_info_t * r;
-	char ethaddr[20];
-
-	PRINTK("### eth_init\n");
-
-	if (!pbuf) {
-		pbuf = malloc(NB*2000);
-		if (!pbuf) {
-			printf("Cannot allocate rx buffers\n");
-			return -1;
-		}
-	}
-
-#ifdef CONFIG_DRIVER_NE2000_CCR
-	{
-		volatile unsigned char *p =  (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR;
-
-		PRINTK("CCR before is %x\n", *p);
-		*p = CONFIG_DRIVER_NE2000_VAL;
-		PRINTK("CCR after is %x\n", *p);
-	}
-#endif
-
-	nic_base = CONFIG_DRIVER_NE2000_BASE;
-	nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE;
-
-	r = get_prom();
-	if (!r)
-		return -1;
-
-	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-		 dev_addr[0], dev_addr[1],
-		 dev_addr[2], dev_addr[3],
-		 dev_addr[4], dev_addr[5]) ;
-	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
-	setenv ("ethaddr", ethaddr);
-
-
-#define DP_DATA		0x10
-	nic.data = nic.base + DP_DATA;
-	nic.tx_buf1 = 0x40;
-	nic.tx_buf2 = 0x48;
-	nic.rx_buf_start = 0x50;
-	nic.rx_buf_end = 0x80;
-
-	if (dp83902a_init() == false)
-		return -1;
-	dp83902a_start(dev_addr);
-	return 0;
-}
-
-void eth_halt() {
-
-	PRINTK("### eth_halt\n");
-
-	dp83902a_stop();
-}
-
-int eth_rx() {
-	int j, tmo;
-
-	PRINTK("### eth_rx\n");
-
-	tmo = get_timer (0) + TOUT * CFG_HZ;
-	while(1) {
-		dp83902a_poll();
-		if (nrx > 0) {
-			for(j=0; j<nrx; j++) {
-				NetReceive(&pbuf[j*2000], plen[j]);
-			}
-			nrx = 0;
-			return 1;
-		}
-		if (get_timer (0) >= tmo) {
-			printf("timeout during rx\n");
-			return 0;
-		}
-	}
-	return 0;
-}
-
-int eth_send(volatile void *packet, int length) {
-	int tmo;
-
-	PRINTK("### eth_send\n");
-
-	pkey = -1;
-
-	dp83902a_send((unsigned char *) packet, length, 666);
-	tmo = get_timer (0) + TOUT * CFG_HZ;
-	while(1) {
-		dp83902a_poll();
-		if (pkey != -1) {
-			PRINTK("Packet sucesfully sent\n");
-			return 0;
-		}
-		if (get_timer (0) >= tmo) {
-			printf("transmission error (timoeut)\n");
-			return 0;
-		}
-
-	}
-	return 0;
-}
-
-#endif
diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h
deleted file mode 100644
index 2955533d7a..0000000000
--- a/drivers/net/ne2000.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
-Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-
-==========================================================================
-
-      dev/dp83902a.h
-
-      National Semiconductor DP83902a ethernet chip
-
-==========================================================================
-####ECOSGPLCOPYRIGHTBEGIN####
- -------------------------------------------
- This file is part of eCos, the Embedded Configurable Operating System.
- Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
- eCos is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 or (at your option) any later version.
-
- eCos is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License along
- with eCos; if not, write to the Free Software Foundation, Inc.,
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
- As a special exception, if other files instantiate templates or use macros
- or inline functions from this file, or you compile this file and link it
- with other works to produce a work based on this file, this file does not
- by itself cause the resulting work to be covered by the GNU General Public
- License. However the source code for this file must still be made available
- in accordance with section (3) of the GNU General Public License.
-
- This exception does not invalidate any other reasons why a work based on
- this file might be covered by the GNU General Public License.
-
- Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
- at http://sources.redhat.com/ecos/ecos-license/ */
- -------------------------------------------
-####ECOSGPLCOPYRIGHTEND####
-####BSDCOPYRIGHTBEGIN####
-
- -------------------------------------------
-
- Portions of this software may have been derived from OpenBSD or other sources,
- and are covered by the appropriate copyright disclaimers included herein.
-
- -------------------------------------------
-
-####BSDCOPYRIGHTEND####
-==========================================================================
-#####DESCRIPTIONBEGIN####
-
- Author(s):    gthomas
- Contributors: gthomas, jskov
- Date:         2001-06-13
- Purpose:
- Description:
-
-####DESCRIPTIONEND####
-
-==========================================================================
-
-*/
-
-/*
- ------------------------------------------------------------------------
- Macros for accessing DP registers
- These can be overridden by the platform header
-*/
-
-#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
-#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)
-
-#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)))
-#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)
-
-
-/* here is all the data */
-
-#define cyg_uint8 unsigned char
-#define cyg_uint16 unsigned short
-#define bool int
-
-#define false 0
-#define true 1
-
-#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
-#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
-
-typedef struct dp83902a_priv_data {
-    cyg_uint8* base;
-    cyg_uint8* data;
-    cyg_uint8* reset;
-    int tx_next;           /* First free Tx page */
-    int tx_int;            /* Expecting interrupt from this buffer */
-    int rx_next;           /* First free Rx page */
-    int tx1, tx2;          /* Page numbers for Tx buffers */
-    unsigned long tx1_key, tx2_key;   /* Used to ack when packet sent */
-    int tx1_len, tx2_len;
-    bool tx_started, running, hardwired_esa;
-    cyg_uint8 esa[6];
-    void* plf_priv;
-
-    /* Buffer allocation */
-    int tx_buf1, tx_buf2;
-    int rx_buf_start, rx_buf_end;
-} dp83902a_priv_data_t;
-
-/*
- ------------------------------------------------------------------------
- Some forward declarations
-*/
-static void dp83902a_poll(void);
-
-/* ------------------------------------------------------------------------ */
-/* Register offsets */
-
-#define DP_CR          0x00
-#define DP_CLDA0       0x01
-#define DP_PSTART      0x01             /* write */
-#define DP_CLDA1       0x02
-#define DP_PSTOP       0x02             /* write */
-#define DP_BNDRY       0x03
-#define DP_TSR         0x04
-#define DP_TPSR        0x04             /* write */
-#define DP_NCR         0x05
-#define DP_TBCL        0x05             /* write */
-#define DP_FIFO        0x06
-#define DP_TBCH        0x06             /* write */
-#define DP_ISR         0x07
-#define DP_CRDA0       0x08
-#define DP_RSAL        0x08             /* write */
-#define DP_CRDA1       0x09
-#define DP_RSAH        0x09             /* write */
-#define DP_RBCL        0x0a             /* write */
-#define DP_RBCH        0x0b             /* write */
-#define DP_RSR         0x0c
-#define DP_RCR         0x0c             /* write */
-#define DP_FER         0x0d
-#define DP_TCR         0x0d             /* write */
-#define DP_CER         0x0e
-#define DP_DCR         0x0e             /* write */
-#define DP_MISSED      0x0f
-#define DP_IMR         0x0f             /* write */
-#define DP_DATAPORT    0x10             /* "eprom" data port */
-
-#define DP_P1_CR       0x00
-#define DP_P1_PAR0     0x01
-#define DP_P1_PAR1     0x02
-#define DP_P1_PAR2     0x03
-#define DP_P1_PAR3     0x04
-#define DP_P1_PAR4     0x05
-#define DP_P1_PAR5     0x06
-#define DP_P1_CURP     0x07
-#define DP_P1_MAR0     0x08
-#define DP_P1_MAR1     0x09
-#define DP_P1_MAR2     0x0a
-#define DP_P1_MAR3     0x0b
-#define DP_P1_MAR4     0x0c
-#define DP_P1_MAR5     0x0d
-#define DP_P1_MAR6     0x0e
-#define DP_P1_MAR7     0x0f
-
-#define DP_P2_CR       0x00
-#define DP_P2_PSTART   0x01
-#define DP_P2_CLDA0    0x01             /* write */
-#define DP_P2_PSTOP    0x02
-#define DP_P2_CLDA1    0x02             /* write */
-#define DP_P2_RNPP     0x03
-#define DP_P2_TPSR     0x04
-#define DP_P2_LNPP     0x05
-#define DP_P2_ACH      0x06
-#define DP_P2_ACL      0x07
-#define DP_P2_RCR      0x0c
-#define DP_P2_TCR      0x0d
-#define DP_P2_DCR      0x0e
-#define DP_P2_IMR      0x0f
-
-/* Command register - common to all pages */
-
-#define DP_CR_STOP    0x01   /* Stop: software reset */
-#define DP_CR_START   0x02   /* Start: initialize device */
-#define DP_CR_TXPKT   0x04   /* Transmit packet */
-#define DP_CR_RDMA    0x08   /* Read DMA  (recv data from device) */
-#define DP_CR_WDMA    0x10   /* Write DMA (send data to device) */
-#define DP_CR_SEND    0x18   /* Send packet */
-#define DP_CR_NODMA   0x20   /* Remote (or no) DMA */
-#define DP_CR_PAGE0   0x00   /* Page select */
-#define DP_CR_PAGE1   0x40
-#define DP_CR_PAGE2   0x80
-#define DP_CR_PAGEMSK 0x3F   /* Used to mask out page bits */
-
-/* Data configuration register */
-
-#define DP_DCR_WTS    0x01   /* 1=16 bit word transfers */
-#define DP_DCR_BOS    0x02   /* 1=Little Endian */
-#define DP_DCR_LAS    0x04   /* 1=Single 32 bit DMA mode */
-#define DP_DCR_LS     0x08   /* 1=normal mode, 0=loopback */
-#define DP_DCR_ARM    0x10   /* 0=no send command (program I/O) */
-#define DP_DCR_FIFO_1 0x00   /* FIFO threshold */
-#define DP_DCR_FIFO_2 0x20
-#define DP_DCR_FIFO_4 0x40
-#define DP_DCR_FIFO_6 0x60
-
-#define DP_DCR_INIT   (DP_DCR_LS|DP_DCR_FIFO_4)
-
-/* Interrupt status register */
-
-#define DP_ISR_RxP    0x01   /* Packet received */
-#define DP_ISR_TxP    0x02   /* Packet transmitted */
-#define DP_ISR_RxE    0x04   /* Receive error */
-#define DP_ISR_TxE    0x08   /* Transmit error */
-#define DP_ISR_OFLW   0x10   /* Receive overflow */
-#define DP_ISR_CNT    0x20   /* Tally counters need emptying */
-#define DP_ISR_RDC    0x40   /* Remote DMA complete */
-#define DP_ISR_RESET  0x80   /* Device has reset (shutdown, error) */
-
-/* Interrupt mask register */
-
-#define DP_IMR_RxP    0x01   /* Packet received */
-#define DP_IMR_TxP    0x02   /* Packet transmitted */
-#define DP_IMR_RxE    0x04   /* Receive error */
-#define DP_IMR_TxE    0x08   /* Transmit error */
-#define DP_IMR_OFLW   0x10   /* Receive overflow */
-#define DP_IMR_CNT    0x20   /* Tall counters need emptying */
-#define DP_IMR_RDC    0x40   /* Remote DMA complete */
-
-#define DP_IMR_All    0x3F   /* Everything but remote DMA */
-
-/* Receiver control register */
-
-#define DP_RCR_SEP    0x01   /* Save bad(error) packets */
-#define DP_RCR_AR     0x02   /* Accept runt packets */
-#define DP_RCR_AB     0x04   /* Accept broadcast packets */
-#define DP_RCR_AM     0x08   /* Accept multicast packets */
-#define DP_RCR_PROM   0x10   /* Promiscuous mode */
-#define DP_RCR_MON    0x20   /* Monitor mode - 1=accept no packets */
-
-/* Receiver status register */
-
-#define DP_RSR_RxP    0x01   /* Packet received */
-#define DP_RSR_CRC    0x02   /* CRC error */
-#define DP_RSR_FRAME  0x04   /* Framing error */
-#define DP_RSR_FO     0x08   /* FIFO overrun */
-#define DP_RSR_MISS   0x10   /* Missed packet */
-#define DP_RSR_PHY    0x20   /* 0=pad match, 1=mad match */
-#define DP_RSR_DIS    0x40   /* Receiver disabled */
-#define DP_RSR_DFR    0x80   /* Receiver processing deferred */
-
-/* Transmitter control register */
-
-#define DP_TCR_NOCRC  0x01   /* 1=inhibit CRC */
-#define DP_TCR_NORMAL 0x00   /* Normal transmitter operation */
-#define DP_TCR_LOCAL  0x02   /* Internal NIC loopback */
-#define DP_TCR_INLOOP 0x04   /* Full internal loopback */
-#define DP_TCR_OUTLOOP 0x08  /* External loopback */
-#define DP_TCR_ATD    0x10   /* Auto transmit disable */
-#define DP_TCR_OFFSET 0x20   /* Collision offset adjust */
-
-/* Transmit status register */
-
-#define DP_TSR_TxP    0x01   /* Packet transmitted */
-#define DP_TSR_COL    0x04   /* Collision (at least one) */
-#define DP_TSR_ABT    0x08   /* Aborted because of too many collisions */
-#define DP_TSR_CRS    0x10   /* Lost carrier */
-#define DP_TSR_FU     0x20   /* FIFO underrun */
-#define DP_TSR_CDH    0x40   /* Collision Detect Heartbeat */
-#define DP_TSR_OWC    0x80   /* Collision outside normal window */
-
-#define IEEE_8023_MAX_FRAME         1518    /* Largest possible ethernet frame */
-#define IEEE_8023_MIN_FRAME           64    /* Smallest possible ethernet frame */
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
deleted file mode 100644
index 89b3a8394e..0000000000
--- a/drivers/net/netarm_eth.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Copyright (C) 2004 IMMS gGmbH <www.imms.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * author(s): Thomas Elste, <info@elste.org>
- *            (some parts derived from uCLinux Netarm Ethernet Driver)
- */
-
-
-#include <common.h>
-
-#ifdef CONFIG_DRIVER_NETARMETH
-#include <command.h>
-#include <net.h>
-#include "netarm_eth.h"
-#include <asm/arch/netarm_registers.h>
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
-
-static int na_mii_poll_busy (void);
-
-static void na_get_mac_addr (void)
-{
-	unsigned short p[3];
-	char *m_addr;
-	char ethaddr[20];
-
-	m_addr = (char *) p;
-
-	p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
-	p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
-	p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
-
-	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-		 m_addr[0], m_addr[1],
-		 m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
-
-	printf ("HW-MAC Address:  %s\n", ethaddr);
-
-	/* set env, todo: check if already an adress is set */
-	setenv ("ethaddr", ethaddr);
-}
-
-
-static void na_mii_write (int reg, int value)
-{
-	int mii_addr;
-
-	/* Select register */
-	mii_addr = CFG_ETH_PHY_ADDR + reg;
-	SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
-	/* Write value */
-	SET_EADDR (NETARM_ETH_MII_WRITE, value);
-	na_mii_poll_busy ();
-}
-
-static unsigned int na_mii_read (int reg)
-{
-	int mii_addr, val;
-
-	/* Select register */
-	mii_addr = CFG_ETH_PHY_ADDR + reg;
-	SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
-	/* do one management cycle */
-	SET_EADDR (NETARM_ETH_MII_CMD,
-		   GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
-	na_mii_poll_busy ();
-	/* Return read value */
-	val = GET_EADDR (NETARM_ETH_MII_READ);
-	return val;
-}
-
-static int na_mii_poll_busy (void)
-{
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked ();
-	while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) {
-		if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
-			return 1;
-		}
-	}
-	printf ("na_mii_busy timeout\n");
-	return (0);
-}
-
-static int na_mii_identify_phy (void)
-{
-	int id_reg_a = 0;
-
-	/* get phy id register */
-	id_reg_a = na_mii_read (MII_PHY_ID);
-
-	if (id_reg_a == 0x0043) {
-		/* This must be an Enable or a Lucent LU3X31 PHY chip */
-		return 1;
-	} else if (id_reg_a == 0x0013) {
-		/* it is an Intel LXT971A */
-		return 1;
-	}
-	return (0);
-}
-
-static int na_mii_negotiate (void)
-{
-	int i = 0;
-
-	/* Enable auto-negotiation */
-	na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
-	/* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
-	/* Restart auto-negotiation */
-	na_mii_write (MII_PHY_CONTROL, 0x1200);
-
-	/* status register is 0xffff after setting the autoneg restart bit */
-	while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
-		i++;
-	}
-
-	/* na_mii_read uses the timer already, so we can't use it again for
-	   timeout checking.
-	   Instead we just try some times.
-	 */
-	for (i = 0; i < 40000; i++) {
-		if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
-			return 0;
-		}
-	}
-	/*
-	   printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
-	 */
-	return (1);
-}
-
-static unsigned int na_mii_check_speed (void)
-{
-	unsigned int status;
-
-	/* Read Status register */
-	status = na_mii_read (MII_PHY_STATUS);
-	/* Check link status.  If 0, default to 100 Mbps. */
-	if ((status & 0x0004) == 0) {
-		printf ("*Warning* no link detected, set default speed to 100Mbs\n");
-		return 1;
-	} else {
-		if ((na_mii_read (17) & 0x4000) != 0) {
-			printf ("100Mbs link detected\n");
-			return 1;
-		} else {
-			printf ("10Mbs link detected\n");
-			return 0;
-		}
-	}
-	return 0;
-}
-
-static int reset_eth (void)
-{
-	int pt;
-
-	na_get_mac_addr ();
-	pt = na_mii_identify_phy ();
-
-	/* reset the phy */
-	na_mii_write (MII_PHY_CONTROL, 0x8000);
-	reset_timer_masked ();
-	while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) {
-		if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
-			break;
-		}
-	}
-	if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY)
-		printf ("phy reset timeout\n");
-
-	/* set the PCS reg */
-	SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
-		   NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
-
-	na_mii_negotiate ();
-	na_mii_check_speed ();
-
-	/* Delay 10 millisecond.  (Maybe this should be 1 second.) */
-	udelay (10000);
-
-	/* Turn receive on.
-	   Enable statistics register autozero on read.
-	   Do not insert MAC address on transmit.
-	   Do not enable special test modes.  */
-	SET_EADDR (NETARM_ETH_STL_CFG,
-		   (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
-
-	/* Set the inter-packet gap delay to 0.96us for MII.
-	   The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
-	   Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
-	   Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
-	SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
-	SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
-
-	/* Add CRC to end of packets.
-	   Pad packets to minimum length of 64 bytes.
-	   Allow unlimited length transmit packets.
-	   Receive all broadcast packets.
-	   NOTE:  Multicast addressing is NOT enabled here currently. */
-	SET_EADDR (NETARM_ETH_MAC_CFG,
-		   (NETARM_ETH_MACC_CRCEN |
-		    NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
-	SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
-
-	/* enable fifos */
-	SET_EADDR (NETARM_ETH_GEN_CTRL,
-		   (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
-
-	return (0);
-}
-
-
-extern int eth_init (bd_t * bd)
-{
-	reset_eth ();
-	return 0;
-}
-
-extern void eth_halt (void)
-{
-	SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
-}
-
-/* Get a data block via Ethernet */
-extern int eth_rx (void)
-{
-	int i;
-	unsigned short rxlen;
-	unsigned int *addr;
-	unsigned int rxstatus, lastrxlen;
-	char *pa;
-
-	/* RXBR is 1, data block was received */
-	if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
-		return 0;
-
-	/* get status register and the length of received block */
-	rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
-	rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
-
-	if (rxlen == 0)
-		return 0;
-
-	/* clear RXBR to make fifo available */
-	SET_EADDR (NETARM_ETH_GEN_STAT,
-		   GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
-
-	/* clear TXBC to make fifo available */
-	/* According to NETARM50 data manual you just have to clear
-	   RXBR but that has no effect. Only after clearing TXBC the
-	   Fifo becomes readable. */
-	SET_EADDR (NETARM_ETH_GEN_STAT,
-		   GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
-
-	addr = (unsigned int *) NetRxPackets[0];
-	pa = (char *) NetRxPackets[0];
-
-	/* read the fifo */
-	for (i = 0; i < rxlen / 4; i++) {
-		*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
-		addr++;
-	}
-
-	if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
-		/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
-		lastrxlen =
-			(GET_EADDR (NETARM_ETH_GEN_STAT) &
-			 NETARM_ETH_GST_RXFDB) >> 28;
-		*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
-		switch (lastrxlen) {
-		case 1:
-			*addr &= 0xff000000;
-			break;
-		case 2:
-			*addr &= 0xffff0000;
-			break;
-		case 3:
-			*addr &= 0xffffff00;
-			break;
-		}
-	}
-
-	/* Pass the packet up to the protocol layers. */
-	NetReceive (NetRxPackets[0], rxlen);
-
-	return rxlen;
-}
-
-/* Send a data block via Ethernet. */
-extern int eth_send (volatile void *packet, int length)
-{
-	int i, length32;
-	char *pa;
-	unsigned int *pa32, lastp = 0, rest;
-
-	pa = (char *) packet;
-	pa32 = (unsigned int *) packet;
-	length32 = length / 4;
-	rest = length % 4;
-
-	/* make sure there's no garbage in the last word */
-	switch (rest) {
-	case 0:
-		lastp = pa32[length32];
-		length32--;
-		break;
-	case 1:
-		lastp = pa32[length32] & 0x000000ff;
-		break;
-	case 2:
-		lastp = pa32[length32] & 0x0000ffff;
-		break;
-	case 3:
-		lastp = pa32[length32] & 0x00ffffff;
-		break;
-	}
-
-	/* write to the fifo */
-	for (i = 0; i < length32; i++)
-		SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
-
-	/* the last word is written to an extra register, this
-	   starts the transmission */
-	SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
-
-	/* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
-	   went fine. But we can't use the timer for a timeout loop because
-	   of it is used already in upper layers. So we just try some times. */
-	i = 0;
-	while (i < 50000) {
-		if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
-		    == NETARM_ETH_TXSTAT_TXOK)
-			return 0;
-		i++;
-	}
-
-	printf ("eth_send timeout\n");
-	return 1;
-}
-
-#endif /* COMMANDS & CFG_NET */
-
-#endif /* CONFIG_DRIVER_NETARMETH */
diff --git a/drivers/net/netarm_eth.h b/drivers/net/netarm_eth.h
deleted file mode 100644
index 8edab82da3..0000000000
--- a/drivers/net/netarm_eth.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2003 IMMS gGmbH <www.imms.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * author(s): Thomas Elste, <info@elste.org>
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#ifdef CONFIG_DRIVER_NETARMETH
-
-#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val
-#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE))
-
-#define NA_MII_POLL_BUSY_DELAY 900
-
-/* MII negotiation timeout value
-   500 jiffies = 5 seconds */
-#define NA_MII_NEGOTIATE_DELAY 30
-
-/* Registers in the physical layer chip */
-#define MII_PHY_CONTROL		0
-#define MII_PHY_STATUS		1
-#define MII_PHY_ID              2
-#define MII_PHY_AUTONEGADV	4
-
-#endif /* CONFIG_DRIVER_NETARMETH */
diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c
deleted file mode 100644
index 860b142bc8..0000000000
--- a/drivers/net/ns9750_eth.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_eth.c,v 1.2 2004/02/24 14:09:39 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Ethernet driver for the NS9750. Uses DMA Engine with polling
- *	   interrupt status. But interrupts are not enabled.
- *	   Only one tx buffer descriptor and the RXA buffer descriptor are used
- *	   Currently no transmit lockup handling is included. eth_send has a 5s
- *	   timeout for sending frames. No retransmits are performed when an
- *	   error occurs.
- * @References: [1] NS9750 Hardware Reference, December 2003
- *		[2] Intel LXT971 Datasheet #249414 Rev. 02
- *		[3] NS7520 Linux Ethernet Driver
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#include <common.h>
-#include <net.h>		/* NetSendPacket */
-
-#include "ns9750_eth.h"		/* for Ethernet and PHY */
-
-#ifdef CONFIG_DRIVER_NS9750_ETHERNET
-
-/* some definition to make transistion to linux easier */
-
-#define NS9750_DRIVER_NAME	"eth"
-#define KERN_WARNING		"Warning:"
-#define KERN_ERR		"Error:"
-#define KERN_INFO		"Info:"
-
-
-#ifdef	DEBUG
-# define printk			printf
-
-# define DEBUG_INIT		0x0001
-# define DEBUG_MINOR		0x0002
-# define DEBUG_RX		0x0004
-# define DEBUG_TX		0x0008
-# define DEBUG_INT		0x0010
-# define DEBUG_POLL		0x0020
-# define DEBUG_LINK		0x0040
-# define DEBUG_MII		0x0100
-# define DEBUG_MII_LOW		0x0200
-# define DEBUG_MEM		0x0400
-# define DEBUG_ERROR		0x4000
-# define DEBUG_ERROR_CRIT	0x8000
-
-static int nDebugLvl = DEBUG_ERROR_CRIT;
-
-# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
-		printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
-# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
-		printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
-# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
-		printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
-# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
-		printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
-# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
-		printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
-# define ASSERT( expr, func ) if( !( expr ) ) { \
-		printf( "Assertion failed! %s:line %d %s\n", \
-		(int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
-		func }
-#else /* DEBUG */
-# define printk(...)
-# define DEBUG_ARGS0( FLG, a0 )
-# define DEBUG_ARGS1( FLG, a0, a1 )
-# define DEBUG_ARGS2( FLG, a0, a1, a2 )
-# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
-# define DEBUG_FN( n )
-# define ASSERT(expr, func)
-#endif /* DEBUG */
-
-#define NS9750_MII_NEG_DELAY		(5*CFG_HZ) /* in s */
-#define TX_TIMEOUT			(5*CFG_HZ) /* in s */
-
-/* @TODO move it to eeprom.h */
-#define FS_EEPROM_AUTONEG_MASK		0x7
-#define FS_EEPROM_AUTONEG_SPEED_MASK	0x1
-#define FS_EEPROM_AUTONEG_SPEED_10	0x0
-#define FS_EEPROM_AUTONEG_SPEED_100	0x1
-#define FS_EEPROM_AUTONEG_DUPLEX_MASK	0x2
-#define FS_EEPROM_AUTONEG_DUPLEX_HALF	0x0
-#define FS_EEPROM_AUTONEG_DUPLEX_FULL	0x2
-#define FS_EEPROM_AUTONEG_ENABLE_MASK	0x4
-#define FS_EEPROM_AUTONEG_DISABLE	0x0
-#define FS_EEPROM_AUTONEG_ENABLE	0x4
-
-/* buffer descriptors taken from [1] p.306 */
-typedef struct
-{
-	unsigned int* punSrc;
-	unsigned int unLen;	/* 11 bits */
-	unsigned int* punDest;	/* unused */
-	union {
-		unsigned int unReg;
-		struct {
-			unsigned uStatus : 16;
-			unsigned uRes : 12;
-			unsigned uFull : 1;
-			unsigned uEnable : 1;
-			unsigned uInt : 1;
-			unsigned uWrap : 1;
-		} bits;
-	} s;
-} rx_buffer_desc_t;
-
-typedef struct
-{
-	unsigned int* punSrc;
-	unsigned int unLen;	/* 10 bits */
-	unsigned int* punDest;	/* unused */
-	union {
-		unsigned int unReg; /* only 32bit accesses may done to NS9750
-				     * eth engine */
-		struct {
-			unsigned uStatus : 16;
-			unsigned uRes : 12;
-			unsigned uFull : 1;
-			unsigned uLast : 1;
-			unsigned uInt : 1;
-			unsigned uWrap : 1;
-		} bits;
-	} s;
-} tx_buffer_desc_t;
-
-static int ns9750_eth_reset( void );
-
-static void ns9750_link_force( void );
-static void ns9750_link_auto_negotiate( void );
-static void ns9750_link_update_egcr( void );
-static void ns9750_link_print_changed( void );
-
-/* the PHY stuff */
-
-static char ns9750_mii_identify_phy( void );
-static unsigned short ns9750_mii_read( unsigned short uiRegister );
-static void ns9750_mii_write( unsigned short uiRegister, unsigned short uiData );
-static unsigned int ns9750_mii_get_clock_divisor( unsigned int unMaxMDIOClk );
-static unsigned int ns9750_mii_poll_busy( void );
-
-static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
-static unsigned char ucLinkMode =      FS_EEPROM_AUTONEG_ENABLE;
-static unsigned int uiLastLinkStatus;
-static PhyType phyDetected = PHY_NONE;
-
-/* we use only one tx buffer descriptor */
-static tx_buffer_desc_t* pTxBufferDesc =
-	(tx_buffer_desc_t*) get_eth_reg_addr( NS9750_ETH_TXBD );
-
-/* we use only one rx buffer descriptor of the 4 */
-static rx_buffer_desc_t aRxBufferDesc[ 4 ];
-
-/***********************************************************************
- * @Function: eth_init
- * @Return: -1 on failure otherwise 0
- * @Descr: Initializes the ethernet engine and uses either FS Forth's default
- *	   MAC addr or the one in environment
- ***********************************************************************/
-
-int eth_init (bd_t * pbis)
-{
-	/* This default MAC Addr is reserved by FS Forth-Systeme for the case of
-	   EEPROM failures */
-	unsigned char aucMACAddr[6] = { 0x00, 0x04, 0xf3, 0x00, 0x06, 0x35 };
-	char *pcTmp = getenv ("ethaddr");
-	char *pcEnd;
-	int i;
-
-	DEBUG_FN (DEBUG_INIT);
-
-	/* no need to check for hardware */
-
-	if (!ns9750_eth_reset ())
-		return -1;
-
-	if (pcTmp != NULL)
-		for (i = 0; i < 6; i++) {
-			aucMACAddr[i] =
-				pcTmp ? simple_strtoul (pcTmp, &pcEnd,
-							16) : 0;
-			pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
-		}
-
-	/* configure ethernet address */
-
-	*get_eth_reg_addr (NS9750_ETH_SA1) =
-		aucMACAddr[5] << 8 | aucMACAddr[4];
-	*get_eth_reg_addr (NS9750_ETH_SA2) =
-		aucMACAddr[3] << 8 | aucMACAddr[2];
-	*get_eth_reg_addr (NS9750_ETH_SA3) =
-		aucMACAddr[1] << 8 | aucMACAddr[0];
-
-	/* enable hardware */
-
-	*get_eth_reg_addr (NS9750_ETH_MAC1) = NS9750_ETH_MAC1_RXEN;
-
-	/* the linux kernel may give packets < 60 bytes, for example arp */
-	*get_eth_reg_addr (NS9750_ETH_MAC2) = NS9750_ETH_MAC2_CRCEN |
-		NS9750_ETH_MAC2_PADEN | NS9750_ETH_MAC2_HUGE;
-
-	/* enable receive and transmit FIFO, use 10/100 Mbps MII */
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) =
-		NS9750_ETH_EGCR1_ETXWM |
-		NS9750_ETH_EGCR1_ERX |
-		NS9750_ETH_EGCR1_ERXDMA |
-		NS9750_ETH_EGCR1_ETX |
-		NS9750_ETH_EGCR1_ETXDMA | NS9750_ETH_EGCR1_ITXA;
-
-	/* prepare DMA descriptors */
-	for (i = 0; i < 4; i++) {
-		aRxBufferDesc[i].punSrc = 0;
-		aRxBufferDesc[i].unLen = 0;
-		aRxBufferDesc[i].s.bits.uWrap = 1;
-		aRxBufferDesc[i].s.bits.uInt = 1;
-		aRxBufferDesc[i].s.bits.uEnable = 0;
-		aRxBufferDesc[i].s.bits.uFull = 0;
-	}
-
-	/* NetRxPackets[ 0 ] is initialized before eth_init is called and never
-	   changes. NetRxPackets is 32bit aligned */
-	aRxBufferDesc[0].punSrc = (unsigned int *) NetRxPackets[0];
-	aRxBufferDesc[0].s.bits.uEnable = 1;
-	aRxBufferDesc[0].unLen = 1522;	/* as stated in [1] p.307 */
-
-	*get_eth_reg_addr (NS9750_ETH_RXAPTR) =
-		(unsigned int) &aRxBufferDesc[0];
-
-	/* [1] Tab. 221 states less than 5us */
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_ERXINIT;
-	while (!
-	       (*get_eth_reg_addr (NS9750_ETH_EGSR) & NS9750_ETH_EGSR_RXINIT))
-		/* wait for finish */
-		udelay (1);
-
-	/* @TODO do we need to clear RXINIT? */
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_ERXINIT;
-
-	*get_eth_reg_addr (NS9750_ETH_RXFREE) = 0x1;
-
-	return 0;
-}
-
-/***********************************************************************
- * @Function: eth_send
- * @Return: -1 on timeout otherwise 1
- * @Descr: sends one frame by DMA
- ***********************************************************************/
-
-int eth_send (volatile void *pPacket, int nLen)
-{
-	ulong ulTimeout;
-
-	DEBUG_FN (DEBUG_TX);
-
-	/* clear old status values */
-	*get_eth_reg_addr (NS9750_ETH_EINTR) &=
-		*get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_TX_MA;
-
-	/* prepare Tx Descriptors */
-
-	pTxBufferDesc->punSrc = (unsigned int *) pPacket;	/* pPacket is 32bit
-								 * aligned */
-	pTxBufferDesc->unLen = nLen;
-	/* only 32bit accesses allowed. wrap, full, interrupt and enabled to 1 */
-	pTxBufferDesc->s.unReg = 0xf0000000;
-	/* pTxBufferDesc is the first possible buffer descriptor */
-	*get_eth_reg_addr (NS9750_ETH_TXPTR) = 0x0;
-
-	/* enable processor for next frame */
-
-	*get_eth_reg_addr (NS9750_ETH_EGCR2) &= ~NS9750_ETH_EGCR2_TCLER;
-	*get_eth_reg_addr (NS9750_ETH_EGCR2) |= NS9750_ETH_EGCR2_TCLER;
-
-	ulTimeout = get_timer (0);
-
-	DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR,
-		     "Waiting for transmission to finish\n");
-	while (!
-	       (*get_eth_reg_addr (NS9750_ETH_EINTR) &
-		(NS9750_ETH_EINTR_TXDONE | NS9750_ETH_EINTR_TXERR))) {
-		/* do nothing, wait for completion */
-		if (get_timer (0) - ulTimeout > TX_TIMEOUT) {
-			DEBUG_ARGS0 (DEBUG_TX, "Transmit Timed out\n");
-			return -1;
-		}
-	}
-	DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR, "transmitted...\n");
-
-	return 0;
-}
-
-/***********************************************************************
- * @Function: eth_rx
- * @Return: size of last frame in bytes or 0 if no frame available
- * @Descr: gives one frame to U-Boot which has been copied by DMA engine already
- *	   to NetRxPackets[ 0 ].
- ***********************************************************************/
-
-int eth_rx (void)
-{
-	int nLen = 0;
-	unsigned int unStatus;
-
-	unStatus =
-		*get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_RX_MA;
-
-	if (!unStatus)
-		/* no packet available, return immediately */
-		return 0;
-
-	DEBUG_FN (DEBUG_RX);
-
-	/* unLen always < max(nLen) and discard checksum */
-	nLen = (int) aRxBufferDesc[0].unLen - 4;
-
-	/* acknowledge status register */
-	*get_eth_reg_addr (NS9750_ETH_EINTR) = unStatus;
-
-	aRxBufferDesc[0].unLen = 1522;
-	aRxBufferDesc[0].s.bits.uFull = 0;
-
-	/* Buffer A descriptor available again */
-	*get_eth_reg_addr (NS9750_ETH_RXFREE) |= 0x1;
-
-	/* NetReceive may call eth_send. Due to a possible bug of the NS9750 we
-	 * have to acknowledge the received frame before sending a new one */
-	if (unStatus & NS9750_ETH_EINTR_RXDONEA)
-		NetReceive (NetRxPackets[0], nLen);
-
-	return nLen;
-}
-
-/***********************************************************************
- * @Function: eth_halt
- * @Return: n/a
- * @Descr: stops the ethernet engine
- ***********************************************************************/
-
-void eth_halt (void)
-{
-	DEBUG_FN (DEBUG_INIT);
-
-	*get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_RXEN;
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~(NS9750_ETH_EGCR1_ERX |
-						  NS9750_ETH_EGCR1_ERXDMA |
-						  NS9750_ETH_EGCR1_ETX |
-						  NS9750_ETH_EGCR1_ETXDMA);
-}
-
-/***********************************************************************
- * @Function: ns9750_eth_reset
- * @Return: 0 on failure otherwise 1
- * @Descr: resets the ethernet interface and the PHY,
- *	   performs auto negotiation or fixed modes
- ***********************************************************************/
-
-static int ns9750_eth_reset (void)
-{
-	DEBUG_FN (DEBUG_MINOR);
-
-	/* Reset MAC */
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_MAC_HRST;
-	udelay (5);		/* according to [1], p.322 */
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_MAC_HRST;
-
-	/* reset and initialize PHY */
-
-	*get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_SRST;
-
-	/* we don't support hot plugging of PHY, therefore we don't reset
-	   phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
-	   incorrect the first open
-	   may detect the PHY correctly but succeding will fail
-	   For reseting the PHY and identifying we have to use the standard
-	   MDIO CLOCK value 2.5 MHz only after hardware reset
-	   After having identified the PHY we will do faster */
-
-	*get_eth_reg_addr (NS9750_ETH_MCFG) =
-		ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
-
-	/* reset PHY */
-	ns9750_mii_write (PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
-	ns9750_mii_write (PHY_COMMON_CTRL, 0);
-
-	/* @TODO check time */
-	udelay (3000);		/* [2] p.70 says at least 300us reset recovery time. But
-				   go sure, it didn't worked stable at higher timer
-				   frequencies under LxNETES-2.x */
-
-	/* MII clock has been setup to default, ns9750_mii_identify_phy should
-	   work for all */
-
-	if (!ns9750_mii_identify_phy ()) {
-		printk (KERN_ERR NS9750_DRIVER_NAME
-			": Unsupported PHY, aborting\n");
-		return 0;
-	}
-
-	/* now take the highest MDIO clock possible after detection */
-	*get_eth_reg_addr (NS9750_ETH_MCFG) =
-		ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
-
-
-	/* PHY has been detected, so there can be no abort reason and we can
-	   finish initializing ethernet */
-
-	uiLastLinkStatus = 0xff;	/* undefined */
-
-	if ((ucLinkMode & FS_EEPROM_AUTONEG_ENABLE_MASK) ==
-	    FS_EEPROM_AUTONEG_DISABLE)
-		/* use parameters defined */
-		ns9750_link_force ();
-	else
-		ns9750_link_auto_negotiate ();
-
-	if (phyDetected == PHY_LXT971A)
-		/* set LED2 to link mode */
-		ns9750_mii_write (PHY_LXT971_LED_CFG,
-				  PHY_LXT971_LED_CFG_LINK_ACT <<
-				  PHY_LXT971_LED_CFG_SHIFT_LED2);
-
-	return 1;
-}
-
-/***********************************************************************
- * @Function: ns9750_link_force
- * @Return: void
- * @Descr: configures eth and MII to use the link mode defined in
- *	   ucLinkMode
- ***********************************************************************/
-
-static void ns9750_link_force (void)
-{
-	unsigned short uiControl;
-
-	DEBUG_FN (DEBUG_LINK);
-
-	uiControl = ns9750_mii_read (PHY_COMMON_CTRL);
-	uiControl &= ~(PHY_COMMON_CTRL_SPD_MA |
-		       PHY_COMMON_CTRL_AUTO_NEG | PHY_COMMON_CTRL_DUPLEX);
-
-	uiLastLinkStatus = 0;
-
-	if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) ==
-	    FS_EEPROM_AUTONEG_SPEED_100) {
-		uiControl |= PHY_COMMON_CTRL_SPD_100;
-		uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX;
-	} else
-		uiControl |= PHY_COMMON_CTRL_SPD_10;
-
-	if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) ==
-	    FS_EEPROM_AUTONEG_DUPLEX_FULL) {
-		uiControl |= PHY_COMMON_CTRL_DUPLEX;
-		uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE;
-	}
-
-	ns9750_mii_write (PHY_COMMON_CTRL, uiControl);
-
-	ns9750_link_print_changed ();
-	ns9750_link_update_egcr ();
-}
-
-/***********************************************************************
- * @Function: ns9750_link_auto_negotiate
- * @Return: void
- * @Descr: performs auto-negotation of link.
- ***********************************************************************/
-
-static void ns9750_link_auto_negotiate (void)
-{
-	unsigned long ulStartJiffies;
-	unsigned short uiStatus;
-
-	DEBUG_FN (DEBUG_LINK);
-
-	/* run auto-negotation */
-	/* define what we are capable of */
-	ns9750_mii_write (PHY_COMMON_AUTO_ADV,
-			  PHY_COMMON_AUTO_ADV_100BTXFD |
-			  PHY_COMMON_AUTO_ADV_100BTX |
-			  PHY_COMMON_AUTO_ADV_10BTFD |
-			  PHY_COMMON_AUTO_ADV_10BT |
-			  PHY_COMMON_AUTO_ADV_802_3);
-	/* start auto-negotiation */
-	ns9750_mii_write (PHY_COMMON_CTRL,
-			  PHY_COMMON_CTRL_AUTO_NEG |
-			  PHY_COMMON_CTRL_RES_AUTO);
-
-	/* wait for completion */
-
-	ulStartJiffies = get_timer (0);
-	while (get_timer (ulStartJiffies) <  NS9750_MII_NEG_DELAY) {
-		uiStatus = ns9750_mii_read (PHY_COMMON_STAT);
-		if ((uiStatus &
-		     (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) ==
-		    (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
-			/* lucky we are, auto-negotiation succeeded */
-			ns9750_link_print_changed ();
-			ns9750_link_update_egcr ();
-			return;
-		}
-	}
-
-	DEBUG_ARGS0 (DEBUG_LINK, "auto-negotiation timed out\n");
-	/* ignore invalid link settings */
-}
-
-/***********************************************************************
- * @Function: ns9750_link_update_egcr
- * @Return: void
- * @Descr: updates the EGCR and MAC2 link status after mode change or
- *	   auto-negotation
- ***********************************************************************/
-
-static void ns9750_link_update_egcr (void)
-{
-	unsigned int unEGCR;
-	unsigned int unMAC2;
-	unsigned int unIPGT;
-
-	DEBUG_FN (DEBUG_LINK);
-
-	unEGCR = *get_eth_reg_addr (NS9750_ETH_EGCR1);
-	unMAC2 = *get_eth_reg_addr (NS9750_ETH_MAC2);
-	unIPGT = *get_eth_reg_addr (NS9750_ETH_IPGT) & ~NS9750_ETH_IPGT_MA;
-
-	unMAC2 &= ~NS9750_ETH_MAC2_FULLD;
-	if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
-	    == PHY_LXT971_STAT2_DUPLEX_MODE) {
-		unMAC2 |= NS9750_ETH_MAC2_FULLD;
-		unIPGT |= 0x15; /* see [1] p. 339 */
-	} else
-		unIPGT |= 0x12; /* see [1] p. 339 */
-
-	*get_eth_reg_addr (NS9750_ETH_MAC2) = unMAC2;
-	*get_eth_reg_addr (NS9750_ETH_EGCR1) = unEGCR;
-	*get_eth_reg_addr (NS9750_ETH_IPGT) = unIPGT;
-}
-
-/***********************************************************************
- * @Function: ns9750_link_print_changed
- * @Return: void
- * @Descr: checks whether the link status has changed and if so prints
- *	   the new mode
- ***********************************************************************/
-
-static void ns9750_link_print_changed (void)
-{
-	unsigned short uiStatus;
-	unsigned short uiControl;
-
-	DEBUG_FN (DEBUG_LINK);
-
-	uiControl = ns9750_mii_read (PHY_COMMON_CTRL);
-
-	if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
-	    PHY_COMMON_CTRL_AUTO_NEG) {
-		/* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
-		uiStatus = ns9750_mii_read (PHY_COMMON_STAT);
-
-		if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
-			printk (KERN_WARNING NS9750_DRIVER_NAME
-				": link down\n");
-			/* @TODO Linux: carrier_off */
-		} else {
-			/* @TODO Linux: carrier_on */
-			if (phyDetected == PHY_LXT971A) {
-				uiStatus = ns9750_mii_read (PHY_LXT971_STAT2);
-				uiStatus &= (PHY_LXT971_STAT2_100BTX |
-					     PHY_LXT971_STAT2_DUPLEX_MODE |
-					     PHY_LXT971_STAT2_AUTO_NEG);
-
-				/* mask out all uninteresting parts */
-			}
-			/* other PHYs must store there link information in
-			   uiStatus as PHY_LXT971 */
-		}
-	} else {
-		/* mode has been forced, so uiStatus should be the same as the
-		   last link status, enforce printing */
-		uiStatus = uiLastLinkStatus;
-		uiLastLinkStatus = 0xff;
-	}
-
-	if (uiStatus != uiLastLinkStatus) {
-		/* save current link status */
-		uiLastLinkStatus = uiStatus;
-
-		/* print new link status */
-
-		printk (KERN_INFO NS9750_DRIVER_NAME
-			": link mode %i Mbps %s duplex %s\n",
-			(uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
-			(uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
-			"half",
-			(uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
-			"");
-	}
-}
-
-/***********************************************************************
- * the MII low level stuff
- ***********************************************************************/
-
-/***********************************************************************
- * @Function: ns9750_mii_identify_phy
- * @Return: 1 if supported PHY has been detected otherwise 0
- * @Descr: checks for supported PHY and prints the IDs.
- ***********************************************************************/
-
-static char ns9750_mii_identify_phy (void)
-{
-	unsigned short uiID1;
-	unsigned short uiID2;
-	unsigned char *szName;
-	char cRes = 0;
-
-	DEBUG_FN (DEBUG_MII);
-
-	phyDetected = (PhyType) uiID1 = ns9750_mii_read (PHY_COMMON_ID1);
-
-	switch (phyDetected) {
-	case PHY_LXT971A:
-		szName = "LXT971A";
-		uiID2 = ns9750_mii_read (PHY_COMMON_ID2);
-		nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
-		cRes = 1;
-		break;
-	case PHY_NONE:
-	default:
-		/* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
-		   address or reset sets the wrong NS9750_ETH_MCFG_CLKS */
-
-		uiID2 = 0;
-		szName = "unknown";
-		nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
-		phyDetected = PHY_NONE;
-	}
-
-	printk (KERN_INFO NS9750_DRIVER_NAME
-		": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
-
-	return cRes;
-}
-
-/***********************************************************************
- * @Function: ns9750_mii_read
- * @Return: the data read from PHY register uiRegister
- * @Descr: the data read may be invalid if timed out. If so, a message
- *	   is printed but the invalid data is returned.
- *	   The fixed device address is being used.
- ***********************************************************************/
-
-static unsigned short ns9750_mii_read (unsigned short uiRegister)
-{
-	DEBUG_FN (DEBUG_MII_LOW);
-
-	/* write MII register to be read */
-	*get_eth_reg_addr (NS9750_ETH_MADR) =
-		NS9750_ETH_PHY_ADDRESS << 8 | uiRegister;
-
-	*get_eth_reg_addr (NS9750_ETH_MCMD) = NS9750_ETH_MCMD_READ;
-
-	if (!ns9750_mii_poll_busy ())
-		printk (KERN_WARNING NS9750_DRIVER_NAME
-			": MII still busy in read\n");
-	/* continue to read */
-
-	*get_eth_reg_addr (NS9750_ETH_MCMD) = 0;
-
-	return (unsigned short) (*get_eth_reg_addr (NS9750_ETH_MRDD));
-}
-
-
-/***********************************************************************
- * @Function: ns9750_mii_write
- * @Return: nothing
- * @Descr: writes the data to the PHY register. In case of a timeout,
- *	   no special handling is performed but a message printed
- *	   The fixed device address is being used.
- ***********************************************************************/
-
-static void ns9750_mii_write (unsigned short uiRegister,
-			      unsigned short uiData)
-{
-	DEBUG_FN (DEBUG_MII_LOW);
-
-	/* write MII register to be written */
-	*get_eth_reg_addr (NS9750_ETH_MADR) =
-		NS9750_ETH_PHY_ADDRESS << 8 | uiRegister;
-
-	*get_eth_reg_addr (NS9750_ETH_MWTD) = uiData;
-
-	if (!ns9750_mii_poll_busy ()) {
-		printf (KERN_WARNING NS9750_DRIVER_NAME
-			": MII still busy in write\n");
-	}
-}
-
-
-/***********************************************************************
- * @Function: ns9750_mii_get_clock_divisor
- * @Return: the clock divisor that should be used in NS9750_ETH_MCFG_CLKS
- * @Descr: if no clock divisor can be calculated for the
- *	   current SYSCLK and the maximum MDIO Clock, a warning is printed
- *	   and the greatest divisor is taken
- ***********************************************************************/
-
-static unsigned int ns9750_mii_get_clock_divisor (unsigned int unMaxMDIOClk)
-{
-	struct {
-		unsigned int unSysClkDivisor;
-		unsigned int unClks;	/* field for NS9750_ETH_MCFG_CLKS */
-	} PHYClockDivisors[] = {
-		{
-		4, NS9750_ETH_MCFG_CLKS_4}, {
-		6, NS9750_ETH_MCFG_CLKS_6}, {
-		8, NS9750_ETH_MCFG_CLKS_8}, {
-		10, NS9750_ETH_MCFG_CLKS_10}, {
-		20, NS9750_ETH_MCFG_CLKS_20}, {
-		30, NS9750_ETH_MCFG_CLKS_30}, {
-		40, NS9750_ETH_MCFG_CLKS_40}
-	};
-
-	int nIndexSysClkDiv;
-	int nArraySize =
-		sizeof (PHYClockDivisors) / sizeof (PHYClockDivisors[0]);
-	unsigned int unClks = NS9750_ETH_MCFG_CLKS_40;	/* defaults to
-							   greatest div */
-
-	DEBUG_FN (DEBUG_INIT);
-
-	for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
-	     nIndexSysClkDiv++) {
-		/* find first sysclock divisor that isn't higher than 2.5 MHz
-		   clock */
-		if (AHB_CLK_FREQ /
-		    PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
-		    unMaxMDIOClk) {
-			unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
-			break;
-		}
-	}
-
-	DEBUG_ARGS2 (DEBUG_INIT,
-		     "Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
-		     unClks, unMaxMDIOClk);
-
-	/* return greatest divisor */
-	return unClks;
-}
-
-/***********************************************************************
- * @Function: ns9750_mii_poll_busy
- * @Return: 0 if timed out otherwise the remaing timeout
- * @Descr: waits until the MII has completed a command or it times out
- *	   code may be interrupted by hard interrupts.
- *	   It is not checked what happens on multiple actions when
- *	   the first is still being busy and we timeout.
- ***********************************************************************/
-
-static unsigned int ns9750_mii_poll_busy (void)
-{
-	unsigned int unTimeout = 10000;
-
-	DEBUG_FN (DEBUG_MII_LOW);
-
-	while (((*get_eth_reg_addr (NS9750_ETH_MIND) & NS9750_ETH_MIND_BUSY)
-		== NS9750_ETH_MIND_BUSY) && unTimeout)
-		unTimeout--;
-
-	return unTimeout;
-}
-
-#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c
deleted file mode 100644
index 8168f870a1..0000000000
--- a/drivers/net/plb2800_eth.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * PLB2800 internal switch ethernet driver.
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
-	&& defined(CONFIG_PLB2800_ETHER)
-
-#include <malloc.h>
-#include <net.h>
-#include <asm/addrspace.h>
-
-
-#define NUM_RX_DESC	PKTBUFSRX
-#define TOUT_LOOP	1000000
-
-#define LONG_REF(addr) (*((volatile unsigned long*)addr))
-
-#define CMAC_CRX_CTRL	LONG_REF(0xb800c870)
-#define CMAC_CTX_CTRL	LONG_REF(0xb800c874)
-#define SYS_MAC_ADDR_0	LONG_REF(0xb800c878)
-#define SYS_MAC_ADDR_1	LONG_REF(0xb800c87c)
-#define MIPS_H_MASK	LONG_REF(0xB800C810)
-
-#define MA_LEARN	LONG_REF(0xb8008004)
-#define DA_LOOKUP	LONG_REF(0xb8008008)
-
-#define CMAC_CRX_CTRL_PD	0x00000001
-#define CMAC_CRX_CTRL_CG	0x00000002
-#define CMAC_CRX_CTRL_PL_SHIFT	2
-#define CMAC_CRIT		0x0
-#define CMAC_NON_CRIT		0x1
-#define MBOX_STAT_ID_SHF	28
-#define MBOX_STAT_CP		0x80000000
-#define MBOX_STAT_MB		0x00000001
-#define EN_MA_LEARN		0x02000000
-#define EN_DA_LKUP		0x01000000
-#define MA_DEST_SHF		11
-#define DA_DEST_SHF		11
-#define DA_STATE_SHF		19
-#define TSTAMP_MS		0x00000000
-#define SW_H_MBOX4_MASK		0x08000000
-#define SW_H_MBOX3_MASK		0x04000000
-#define SW_H_MBOX2_MASK		0x02000000
-#define SW_H_MBOX1_MASK		0x01000000
-
-typedef volatile struct {
-  unsigned int stat;
-  unsigned int cmd;
-  unsigned int cnt;
-  unsigned int adr;
-} mailbox_t;
-
-#define MBOX_REG(mb) ((mailbox_t*)(0xb800c830+(mb<<4)))
-
-typedef volatile struct {
-  unsigned int word0;
-  unsigned int word1;
-  unsigned int word2;
-} mbhdr_t;
-
-#define MBOX_MEM(mb) ((void*)(0xb800a000+((3-mb)<<11)))
-
-
-static int plb2800_eth_init(struct eth_device *dev, bd_t * bis);
-static int plb2800_eth_send(struct eth_device *dev, volatile void *packet,
-						  int length);
-static int plb2800_eth_recv(struct eth_device *dev);
-static void plb2800_eth_halt(struct eth_device *dev);
-
-static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr);
-static unsigned char * plb2800_get_mac_addr(void);
-
-static int rx_new;
-static int mac_addr_set = 0;
-
-
-int plb2800_eth_initialize(bd_t * bis)
-{
-	struct eth_device *dev;
-	ulong temp;
-
-#ifdef DEBUG
-	printf("Entered plb2800_eth_initialize()\n");
-#endif
-
-	if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
-	{
-		printf("Failed to allocate memory\n");
-		return 0;
-	}
-	memset(dev, 0, sizeof(*dev));
-
-	sprintf(dev->name, "PLB2800 Switch");
-	dev->init = plb2800_eth_init;
-	dev->halt = plb2800_eth_halt;
-	dev->send = plb2800_eth_send;
-	dev->recv = plb2800_eth_recv;
-
-	eth_register(dev);
-
-	/* bug fix */
-	*(ulong *)0xb800e800 = 0x838;
-
-	/* Set MBOX ownership */
-	temp = CMAC_CRIT << MBOX_STAT_ID_SHF;
-	MBOX_REG(0)->stat = temp;
-	MBOX_REG(1)->stat = temp;
-
-	temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF;
-	MBOX_REG(2)->stat = temp;
-	MBOX_REG(3)->stat = temp;
-
-	plb2800_set_mac_addr(dev, plb2800_get_mac_addr());
-
-	/* Disable all Mbox interrupt */
-	temp = MIPS_H_MASK;
-	temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ;
-	MIPS_H_MASK = temp;
-
-#ifdef DEBUG
-	printf("Leaving plb2800_eth_initialize()\n");
-#endif
-
-	return 1;
-}
-
-static int plb2800_eth_init(struct eth_device *dev, bd_t * bis)
-{
-#ifdef DEBUG
-	printf("Entering plb2800_eth_init()\n");
-#endif
-
-	plb2800_set_mac_addr(dev, dev->enetaddr);
-
-	rx_new = 0;
-
-#ifdef DEBUG
-	printf("Leaving plb2800_eth_init()\n");
-#endif
-
-	return 0;
-}
-
-
-static int plb2800_eth_send(struct eth_device *dev, volatile void *packet,
-						  int length)
-{
-	int                    i;
-	int                    res         = -1;
-	u32                    temp;
-	mailbox_t *            mb          = MBOX_REG(0);
-	char      *            mem         = MBOX_MEM(0);
-
-#ifdef DEBUG
-	printf("Entered plb2800_eth_send()\n");
-#endif
-
-	if (length <= 0)
-	{
-		printf ("%s: bad packet size: %d\n", dev->name, length);
-		goto Done;
-	}
-
-	if (length < 64)
-	{
-		length = 64;
-	}
-
-	temp = CMAC_CRX_CTRL_CG | ((length + 4) << CMAC_CRX_CTRL_PL_SHIFT);
-
-#ifdef DEBUG
-	printf("0 mb->stat = 0x%x\n",  mb->stat);
-#endif
-
-	for(i = 0; mb->stat & (MBOX_STAT_CP | MBOX_STAT_MB); i++)
-	{
-		if (i >= TOUT_LOOP)
-		{
-			printf("%s: tx buffer not ready\n", dev->name);
-			printf("1 mb->stat = 0x%x\n",  mb->stat);
-			goto Done;
-		}
-	}
-
-		/* For some strange reason, memcpy doesn't work, here!
-		 */
-	do
-	{
-		int words = (length >> 2) + 1;
-		unsigned int* dst = (unsigned int*)(mem);
-		unsigned int* src = (unsigned int*)(packet);
-		for (i = 0; i < words; i++)
-		{
-			*dst = *src;
-			dst++;
-			src++;
-		};
-	} while(0);
-
-	CMAC_CRX_CTRL = temp;
-	mb->cmd = MBOX_STAT_CP;
-
-#ifdef DEBUG
-	printf("2 mb->stat = 0x%x\n",  mb->stat);
-#endif
-
-	res = length;
-Done:
-
-#ifdef DEBUG
-	printf("Leaving plb2800_eth_send()\n");
-#endif
-
-	return res;
-}
-
-
-static int plb2800_eth_recv(struct eth_device *dev)
-{
-	int                    length  = 0;
-	mailbox_t            * mbox    = MBOX_REG(3);
-	unsigned char        * hdr     = MBOX_MEM(3);
-	unsigned int           stat;
-
-#ifdef DEBUG
-	printf("Entered plb2800_eth_recv()\n");
-#endif
-
-	for (;;)
-	{
-		stat = mbox->stat;
-
-		if (!(stat & MBOX_STAT_CP))
-		{
-			break;
-		}
-
-		length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7);
-		memcpy((void *)NetRxPackets[rx_new], hdr + 12, length);
-
-		stat &= ~MBOX_STAT_CP;
-		mbox->stat = stat;
-#ifdef DEBUG
-		{
-			int i;
-			for (i=0;i<length - 4;i++)
-			{
-				if (i % 16 == 0) printf("\n%04x: ", i);
-				printf("%02X ", NetRxPackets[rx_new][i]);
-			}
-			printf("\n");
-		}
-#endif
-
-		if (length)
-		{
-#ifdef DEBUG
-			printf("Received %d bytes\n", length);
-#endif
-			NetReceive((void*)(NetRxPackets[rx_new]),
-			            length - 4);
-		}
-		else
-		{
-			printf("Zero length!!!\n");
-		}
-
-		rx_new = (rx_new + 1) % NUM_RX_DESC;
-	}
-
-#ifdef DEBUG
-	printf("Leaving plb2800_eth_recv()\n");
-#endif
-
-	return length;
-}
-
-
-static void plb2800_eth_halt(struct eth_device *dev)
-{
-#ifdef DEBUG
-	printf("Entered plb2800_eth_halt()\n");
-#endif
-
-#ifdef DEBUG
-	printf("Leaving plb2800_eth_halt()\n");
-#endif
-}
-
-static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr)
-{
-	char packet[60];
-	ulong temp;
-	int ix;
-
-	if (mac_addr_set ||
-	    NULL == addr || memcmp(addr, "\0\0\0\0\0\0", 6) == 0)
-	{
-		return;
-	}
-
-	/* send one packet through CPU port
-	 * in order to learn system MAC address
-	 */
-
-	/* Set DA_LOOKUP register */
-	temp = EN_MA_LEARN | (0 << DA_STATE_SHF) | (63 << DA_DEST_SHF);
-	DA_LOOKUP = temp;
-
-	/* Set MA_LEARN register */
-	temp = 50 << MA_DEST_SHF; 	/* static entry */
-	MA_LEARN = temp;
-
-	/* set destination address */
-	for (ix=0;ix<6;ix++)
-		packet[ix] = 0xff;
-
-	/* set source address = system MAC address */
-	for (ix=0;ix<6;ix++)
-		packet[6+ix] = addr[ix];
-
-	/* set type field */
-	packet[12]=0xaa;
-	packet[13]=0x55;
-
-	/* set data field */
-	for(ix=14;ix<60;ix++)
-		packet[ix] = 0x00;
-
-#ifdef DEBUG
-	for (ix=0;ix<6;ix++)
-		printf("mac_addr[%d]=%02X\n", ix, (unsigned char)packet[6+ix]);
-#endif
-
-	/* set one packet */
-	plb2800_eth_send(dev, packet, sizeof(packet));
-
-	/* delay for a while */
-	for(ix=0;ix<65535;ix++)
-		temp = ~temp;
-
-	/* Set CMAC_CTX_CTRL register */
-	temp = TSTAMP_MS;	/* no autocast */
-	CMAC_CTX_CTRL = temp;
-
-	/* Set DA_LOOKUP register */
-	temp = EN_DA_LKUP;
-	DA_LOOKUP = temp;
-
-	mac_addr_set = 1;
-}
-
-static unsigned char * plb2800_get_mac_addr(void)
-{
-	static unsigned char addr[6];
-	char *tmp, *end;
-	int i;
-
-	tmp = getenv ("ethaddr");
-	if (NULL == tmp) return NULL;
-
-	for (i=0; i<6; i++) {
-		addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
-		if (tmp)
-			tmp = (*end) ? end+1 : end;
-	}
-
-	return addr;
-}
-
-#endif /* CONFIG_PLB2800_ETHER */
diff --git a/drivers/net/rtl8019.c b/drivers/net/rtl8019.c
deleted file mode 100644
index 62b9245517..0000000000
--- a/drivers/net/rtl8019.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Realtek 8019AS Ethernet
- * (C) Copyright 2002-2003
- * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code works in 8bit mode.
- * If you need to work in 16bit mode, PLS change it!
- */
-
-#include <common.h>
-#include <command.h>
-#include "rtl8019.h"
-#include <net.h>
-
-#ifdef CONFIG_DRIVER_RTL8019
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
-
-
-/* packet page register access functions */
-
-
-static unsigned char get_reg (unsigned int regno)
-{
-	return (*(unsigned char *) regno);
-}
-
-
-static void put_reg (unsigned int regno, unsigned char val)
-{
-	*(volatile unsigned char *) regno = val;
-}
-
-static void eth_reset (void)
-{
-	unsigned char ucTemp;
-
-	/* reset NIC */
-	ucTemp = get_reg (RTL8019_RESET);
-	put_reg (RTL8019_RESET, ucTemp);
-	put_reg (RTL8019_INTERRUPTSTATUS, 0xff);
-	udelay (2000);		/* wait for 2ms */
-}
-
-void rtl8019_get_enetaddr (uchar * addr)
-{
-	unsigned char i;
-	unsigned char temp;
-
-	eth_reset ();
-
-	put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
-	put_reg (RTL8019_DATACONFIGURATION, 0x48);
-	put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00);
-	put_reg (RTL8019_REMOTESTARTADDRESS1, 0x00);
-	put_reg (RTL8019_REMOTEBYTECOUNT0, 12);
-	put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
-	put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
-	printf ("MAC: ");
-	for (i = 0; i < 6; i++) {
-		temp = get_reg (RTL8019_DMA_DATA);
-		*addr++ = temp;
-		temp = get_reg (RTL8019_DMA_DATA);
-		printf ("%x:", temp);
-	}
-
-	while ((!get_reg (RTL8019_INTERRUPTSTATUS) & 0x40));
-	printf ("\b \n");
-	put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00);
-	put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-}
-
-
-void eth_halt (void)
-{
-	put_reg (RTL8019_COMMAND, 0x01);
-}
-
-int eth_init (bd_t * bd)
-{
-	eth_reset ();
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP);
-	put_reg (RTL8019_DATACONFIGURATION, 0x48);
-	put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00);
-	put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
-	put_reg (RTL8019_RECEIVECONFIGURATION, 0x00);	/*00; */
-	put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART);
-	put_reg (RTL8019_TRANSMITCONFIGURATION, 0x02);
-	put_reg (RTL8019_PAGESTART, RTL8019_PSTART);
-	put_reg (RTL8019_BOUNDARY, RTL8019_PSTART);
-	put_reg (RTL8019_PAGESTOP, RTL8019_PSTOP);
-	put_reg (RTL8019_INTERRUPTSTATUS, 0xff);
-	put_reg (RTL8019_INTERRUPTMASK, 0x11);	/*b; */
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE1STOP);
-	put_reg (RTL8019_PHYSICALADDRESS0, bd->bi_enetaddr[0]);
-	put_reg (RTL8019_PHYSICALADDRESS1, bd->bi_enetaddr[1]);
-	put_reg (RTL8019_PHYSICALADDRESS2, bd->bi_enetaddr[2]);
-	put_reg (RTL8019_PHYSICALADDRESS3, bd->bi_enetaddr[3]);
-	put_reg (RTL8019_PHYSICALADDRESS4, bd->bi_enetaddr[4]);
-	put_reg (RTL8019_PHYSICALADDRESS5, bd->bi_enetaddr[5]);
-	put_reg (RTL8019_MULTIADDRESS0, 0x00);
-	put_reg (RTL8019_MULTIADDRESS1, 0x00);
-	put_reg (RTL8019_MULTIADDRESS2, 0x00);
-	put_reg (RTL8019_MULTIADDRESS3, 0x00);
-	put_reg (RTL8019_MULTIADDRESS4, 0x00);
-	put_reg (RTL8019_MULTIADDRESS5, 0x00);
-	put_reg (RTL8019_MULTIADDRESS6, 0x00);
-	put_reg (RTL8019_MULTIADDRESS7, 0x00);
-	put_reg (RTL8019_CURRENT, RTL8019_PSTART);
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-	put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0);	/*58; */
-
-	return 0;
-}
-
-
-static unsigned char nic_to_pc (void)
-{
-	unsigned char rec_head_status;
-	unsigned char next_packet_pointer;
-	unsigned char packet_length0;
-	unsigned char packet_length1;
-	unsigned short rxlen = 0;
-	unsigned int i = 4;
-	unsigned char current_point;
-	unsigned char *addr;
-
-	/*
-	 * The RTL8019's first 4B is packet status,page of next packet
-	 * and packet length(2B).So we receive the fist 4B.
-	 */
-	put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY));
-	put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00);
-	put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
-	put_reg (RTL8019_REMOTEBYTECOUNT0, 0x04);
-
-	put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
-
-	rec_head_status = get_reg (RTL8019_DMA_DATA);
-	next_packet_pointer = get_reg (RTL8019_DMA_DATA);
-	packet_length0 = get_reg (RTL8019_DMA_DATA);
-	packet_length1 = get_reg (RTL8019_DMA_DATA);
-
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-	/*Packet length is in two 8bit registers */
-	rxlen = packet_length1;
-	rxlen = (((rxlen << 8) & 0xff00) + packet_length0);
-	rxlen -= 4;
-
-	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
-		printf ("packet too big!\n");
-
-	/*Receive the packet */
-	put_reg (RTL8019_REMOTESTARTADDRESS0, 0x04);
-	put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY));
-
-	put_reg (RTL8019_REMOTEBYTECOUNT0, (rxlen & 0xff));
-	put_reg (RTL8019_REMOTEBYTECOUNT1, ((rxlen >> 8) & 0xff));
-
-
-	put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
-
-	for (addr = (unsigned char *) NetRxPackets[0], i = rxlen; i > 0; i--)
-		*addr++ = get_reg (RTL8019_DMA_DATA);
-	/* Pass the packet up to the protocol layers. */
-	NetReceive (NetRxPackets[0], rxlen);
-
-	while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40);	/* wait for the op. */
-
-	/*
-	 * To test whether the packets are all received,get the
-	 * location of current point
-	 */
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE1);
-	current_point = get_reg (RTL8019_CURRENT);
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-	put_reg (RTL8019_BOUNDARY, next_packet_pointer);
-	return current_point;
-}
-
-/* Get a data block via Ethernet */
-extern int eth_rx (void)
-{
-	unsigned char temp, current_point;
-
-	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-
-	while (1) {
-		temp = get_reg (RTL8019_INTERRUPTSTATUS);
-
-		if (temp & 0x90) {
-			/*overflow */
-			put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP);
-			udelay (2000);
-			put_reg (RTL8019_REMOTEBYTECOUNT0, 0);
-			put_reg (RTL8019_REMOTEBYTECOUNT1, 0);
-			put_reg (RTL8019_TRANSMITCONFIGURATION, 2);
-			do {
-				current_point = nic_to_pc ();
-			} while (get_reg (RTL8019_BOUNDARY) != current_point);
-
-			put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0);
-		}
-
-		if (temp & 0x1) {
-			/*packet received */
-			do {
-				put_reg (RTL8019_INTERRUPTSTATUS, 0x01);
-				current_point = nic_to_pc ();
-			} while (get_reg (RTL8019_BOUNDARY) != current_point);
-		}
-
-		if (!(temp & 0x1))
-			return 0;
-		/* done and exit. */
-	}
-}
-
-/* Send a data block via Ethernet. */
-extern int eth_send (volatile void *packet, int length)
-{
-	volatile unsigned char *p;
-	unsigned int pn;
-
-	pn = length;
-	p = (volatile unsigned char *) packet;
-
-	while (get_reg (RTL8019_COMMAND) == RTL8019_TRANSMIT);
-
-	put_reg (RTL8019_REMOTESTARTADDRESS0, 0);
-	put_reg (RTL8019_REMOTESTARTADDRESS1, RTL8019_TPSTART);
-	put_reg (RTL8019_REMOTEBYTECOUNT0, (pn & 0xff));
-	put_reg (RTL8019_REMOTEBYTECOUNT1, ((pn >> 8) & 0xff));
-
-	put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMAWR);
-	while (pn > 0) {
-		put_reg (RTL8019_DMA_DATA, *p++);
-		pn--;
-	}
-
-	pn = length;
-
-	while (pn < 60) {	/*Padding */
-		put_reg (RTL8019_DMA_DATA, 0);
-		pn++;
-	}
-
-	while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40);
-
-	put_reg (RTL8019_INTERRUPTSTATUS, 0x40);
-	put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART);
-	put_reg (RTL8019_TRANSMITBYTECOUNT0, (pn & 0xff));
-	put_reg (RTL8019_TRANSMITBYTECOUNT1, ((pn >> 8 & 0xff)));
-	put_reg (RTL8019_COMMAND, RTL8019_TRANSMIT);
-
-	return 0;
-}
-
-#endif /* COMMANDS & CFG_NET */
-
-#endif /* CONFIG_DRIVER_RTL8019 */
diff --git a/drivers/net/rtl8019.h b/drivers/net/rtl8019.h
deleted file mode 100644
index 38116ad845..0000000000
--- a/drivers/net/rtl8019.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Realtek 8019AS Ethernet
- * (C) Copyright 2002-2003
- * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code works in 8bit mode.
- * If you need to work in 16bit mode, PLS change it!
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-
-#ifdef CONFIG_DRIVER_RTL8019
-
-#define		RTL8019_REG_00        		(RTL8019_BASE + 0x00)
-#define 	RTL8019_REG_01        		(RTL8019_BASE + 0x01)
-#define 	RTL8019_REG_02        		(RTL8019_BASE + 0x02)
-#define 	RTL8019_REG_03        		(RTL8019_BASE + 0x03)
-#define 	RTL8019_REG_04        		(RTL8019_BASE + 0x04)
-#define 	RTL8019_REG_05        		(RTL8019_BASE + 0x05)
-#define 	RTL8019_REG_06        		(RTL8019_BASE + 0x06)
-#define 	RTL8019_REG_07        		(RTL8019_BASE + 0x07)
-#define 	RTL8019_REG_08        		(RTL8019_BASE + 0x08)
-#define 	RTL8019_REG_09        		(RTL8019_BASE + 0x09)
-#define 	RTL8019_REG_0a        		(RTL8019_BASE + 0x0a)
-#define 	RTL8019_REG_0b        		(RTL8019_BASE + 0x0b)
-#define 	RTL8019_REG_0c        		(RTL8019_BASE + 0x0c)
-#define 	RTL8019_REG_0d        		(RTL8019_BASE + 0x0d)
-#define 	RTL8019_REG_0e       	 	(RTL8019_BASE + 0x0e)
-#define 	RTL8019_REG_0f        		(RTL8019_BASE + 0x0f)
-#define 	RTL8019_REG_10        		(RTL8019_BASE + 0x10)
-#define 	RTL8019_REG_1f        		(RTL8019_BASE + 0x1f)
-
-#define		RTL8019_COMMAND			RTL8019_REG_00
-#define		RTL8019_PAGESTART		RTL8019_REG_01
-#define		RTL8019_PAGESTOP		RTL8019_REG_02
-#define		RTL8019_BOUNDARY		RTL8019_REG_03
-#define		RTL8019_TRANSMITSTATUS		RTL8019_REG_04
-#define		RTL8019_TRANSMITPAGE		RTL8019_REG_04
-#define		RTL8019_TRANSMITBYTECOUNT0	RTL8019_REG_05
-#define		RTL8019_NCR 			RTL8019_REG_05
-#define		RTL8019_TRANSMITBYTECOUNT1 	RTL8019_REG_06
-#define		RTL8019_INTERRUPTSTATUS		RTL8019_REG_07
-#define		RTL8019_CURRENT 		RTL8019_REG_07
-#define		RTL8019_REMOTESTARTADDRESS0 	RTL8019_REG_08
-#define		RTL8019_CRDMA0  		RTL8019_REG_08
-#define		RTL8019_REMOTESTARTADDRESS1 	RTL8019_REG_09
-#define		RTL8019_CRDMA1 			RTL8019_REG_09
-#define		RTL8019_REMOTEBYTECOUNT0	RTL8019_REG_0a
-#define		RTL8019_REMOTEBYTECOUNT1	RTL8019_REG_0b
-#define		RTL8019_RECEIVESTATUS		RTL8019_REG_0c
-#define		RTL8019_RECEIVECONFIGURATION	RTL8019_REG_0c
-#define		RTL8019_TRANSMITCONFIGURATION	RTL8019_REG_0d
-#define		RTL8019_FAE_TALLY 		RTL8019_REG_0d
-#define		RTL8019_DATACONFIGURATION	RTL8019_REG_0e
-#define		RTL8019_CRC_TALLY 		RTL8019_REG_0e
-#define		RTL8019_INTERRUPTMASK		RTL8019_REG_0f
-#define		RTL8019_MISS_PKT_TALLY		RTL8019_REG_0f
-#define		RTL8019_PHYSICALADDRESS0	RTL8019_REG_01
-#define 	RTL8019_PHYSICALADDRESS1	RTL8019_REG_02
-#define		RTL8019_PHYSICALADDRESS2	RTL8019_REG_03
-#define		RTL8019_PHYSICALADDRESS3	RTL8019_REG_04
-#define		RTL8019_PHYSICALADDRESS4	RTL8019_REG_05
-#define		RTL8019_PHYSICALADDRESS5	RTL8019_REG_06
-#define		RTL8019_MULTIADDRESS0		RTL8019_REG_08
-#define		RTL8019_MULTIADDRESS1		RTL8019_REG_09
-#define		RTL8019_MULTIADDRESS2		RTL8019_REG_0a
-#define		RTL8019_MULTIADDRESS3		RTL8019_REG_0b
-#define		RTL8019_MULTIADDRESS4		RTL8019_REG_0c
-#define		RTL8019_MULTIADDRESS5		RTL8019_REG_0d
-#define		RTL8019_MULTIADDRESS6		RTL8019_REG_0e
-#define		RTL8019_MULTIADDRESS7		RTL8019_REG_0f
-#define		RTL8019_DMA_DATA		RTL8019_REG_10
-#define		RTL8019_RESET			RTL8019_REG_1f
-
-
-#define 	RTL8019_PAGE0               	0x22
-#define   	RTL8019_PAGE1               	0x62
-#define   	RTL8019_PAGE0DMAWRITE       	0x12
-#define   	RTL8019_PAGE2DMAWRITE       	0x92
-#define   	RTL8019_REMOTEDMAWR         	0x12
-#define   	RTL8019_REMOTEDMARD         	0x0A
-#define   	RTL8019_ABORTDMAWR          	0x32
-#define   	RTL8019_ABORTDMARD          	0x2A
-#define   	RTL8019_PAGE0STOP           	0x21
-#define   	RTL8019_PAGE1STOP           	0x61
-#define   	RTL8019_TRANSMIT            	0x26
-#define   	RTL8019_TXINPROGRESS        	0x04
-#define   	RTL8019_SEND		    	0x1A
-
-#define		RTL8019_PSTART			0x4c
-#define		RTL8019_PSTOP			0x80
-#define		RTL8019_TPSTART			0x40
-
-
-#endif /*end of CONFIG_DRIVER_RTL8019*/
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
deleted file mode 100644
index afe1a4fdaf..0000000000
--- a/drivers/net/rtl8139.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * rtl8139.c : U-Boot driver for the RealTek RTL8139
- *
- * Masami Komiya (mkomiya@sonare.it)
- *
- * Most part is taken from rtl8139.c of etherboot
- *
- */
-
-/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
-
-  ported from the linux driver written by Donald Becker
-  by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
-
-  This software may be used and distributed according to the terms
-  of the GNU Public License, incorporated herein by reference.
-
-  changes to the original driver:
-  - removed support for interrupts, switching to polling mode (yuck!)
-  - removed support for the 8129 chip (external MII)
-
-*/
-
-/*********************************************************************/
-/* Revision History						     */
-/*********************************************************************/
-
-/*
-  28 Dec 2002	ken_yap@users.sourceforge.net (Ken Yap)
-     Put in virt_to_bus calls to allow Etherboot relocation.
-
-  06 Apr 2001	ken_yap@users.sourceforge.net (Ken Yap)
-     Following email from Hyun-Joon Cha, added a disable routine, otherwise
-     NIC remains live and can crash the kernel later.
-
-  4 Feb 2000	espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
-     Shuffled things around, removed the leftovers from the 8129 support
-     that was in the Linux driver and added a bit more 8139 definitions.
-     Moved the 8K receive buffer to a fixed, available address outside the
-     0x98000-0x9ffff range.  This is a bit of a hack, but currently the only
-     way to make room for the Etherboot features that need substantial amounts
-     of code like the ANSI console support.  Currently the buffer is just below
-     0x10000, so this even conforms to the tagged boot image specification,
-     which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000.  My
-     interpretation of this "reserved" is that Etherboot may do whatever it
-     likes, as long as its environment is kept intact (like the BIOS
-     variables).  Hopefully fixed rtl_poll() once and for all.	The symptoms
-     were that if Etherboot was left at the boot menu for several minutes, the
-     first eth_poll failed.  Seems like I am the only person who does this.
-     First of all I fixed the debugging code and then set out for a long bug
-     hunting session.  It took me about a week full time work - poking around
-     various places in the driver, reading Don Becker's and Jeff Garzik's Linux
-     driver and even the FreeBSD driver (what a piece of crap!) - and
-     eventually spotted the nasty thing: the transmit routine was acknowledging
-     each and every interrupt pending, including the RxOverrun and RxFIFIOver
-     interrupts.  This confused the RTL8139 thoroughly.	 It destroyed the
-     Rx ring contents by dumping the 2K FIFO contents right where we wanted to
-     get the next packet.  Oh well, what fun.
-
-  18 Jan 2000	mdc@thinguin.org (Marty Connor)
-     Drastically simplified error handling.  Basically, if any error
-     in transmission or reception occurs, the card is reset.
-     Also, pointed all transmit descriptors to the same buffer to
-     save buffer space.	 This should decrease driver size and avoid
-     corruption because of exceeding 32K during runtime.
-
-  28 Jul 1999	(Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
-     rtl_poll was quite broken: it used the RxOK interrupt flag instead
-     of the RxBufferEmpty flag which often resulted in very bad
-     transmission performace - below 1kBytes/s.
-
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
-	defined(CONFIG_RTL8139)
-
-#define TICKS_PER_SEC	CFG_HZ
-#define TICKS_PER_MS	(TICKS_PER_SEC/1000)
-
-#define RTL_TIMEOUT	(1*TICKS_PER_SEC)
-
-#define ETH_FRAME_LEN		1514
-#define ETH_ALEN		6
-#define ETH_ZLEN		60
-
-/* PCI Tuning Parameters
-   Threshold is bytes transferred to chip before transmission starts. */
-#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
-#define RX_FIFO_THRESH	4	/* Rx buffer level before first PCI xfer.  */
-#define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 bytes */
-#define TX_DMA_BURST	4	/* Calculate as 16<<val. */
-#define NUM_TX_DESC	4	/* Number of Tx descriptor registers. */
-#define TX_BUF_SIZE	ETH_FRAME_LEN	/* FCS is added by the chip */
-#define RX_BUF_LEN_IDX 0	/* 0, 1, 2 is allowed - 8,16,32K rx buffer */
-#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
-
-#undef DEBUG_TX
-#undef DEBUG_RX
-
-#define currticks()	get_timer(0)
-#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
-
-/* Symbolic offsets to registers. */
-enum RTL8139_registers {
-	MAC0=0,			/* Ethernet hardware address. */
-	MAR0=8,			/* Multicast filter. */
-	TxStatus0=0x10,		/* Transmit status (four 32bit registers). */
-	TxAddr0=0x20,		/* Tx descriptors (also four 32bit). */
-	RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
-	ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
-	IntrMask=0x3C, IntrStatus=0x3E,
-	TxConfig=0x40, RxConfig=0x44,
-	Timer=0x48,		/* general-purpose counter. */
-	RxMissed=0x4C,		/* 24 bits valid, write clears. */
-	Cfg9346=0x50, Config0=0x51, Config1=0x52,
-	TimerIntrReg=0x54,	/* intr if gp counter reaches this value */
-	MediaStatus=0x58,
-	Config3=0x59,
-	MultiIntr=0x5C,
-	RevisionID=0x5E,	/* revision of the RTL8139 chip */
-	TxSummary=0x60,
-	MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
-	NWayExpansion=0x6A,
-	DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
-	NWayTestReg=0x70,
-	RxCnt=0x72,		/* packet received counter */
-	CSCR=0x74,		/* chip status and configuration register */
-	PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,	/* undocumented */
-	/* from 0x84 onwards are a number of power management/wakeup frame
-	 * definitions we will probably never need to know about.  */
-};
-
-enum ChipCmdBits {
-	CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
-
-/* Interrupt register bits, using my own meaningful names. */
-enum IntrStatusBits {
-	PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
-	RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
-	TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
-};
-enum TxStatusBits {
-	TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
-	TxOutOfWindow=0x20000000, TxAborted=0x40000000,
-	TxCarrierLost=0x80000000,
-};
-enum RxStatusBits {
-	RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
-	RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
-	RxBadAlign=0x0002, RxStatusOK=0x0001,
-};
-
-enum MediaStatusBits {
-	MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
-	MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
-};
-
-enum MIIBMCRBits {
-	BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
-	BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
-};
-
-enum CSCRBits {
-	CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
-	CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
-	CSCR_LinkDownCmd=0x0f3c0,
-};
-
-/* Bits in RxConfig. */
-enum rx_mode_bits {
-	RxCfgWrap=0x80,
-	AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
-	AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
-};
-
-static int ioaddr;
-static unsigned int cur_rx,cur_tx;
-
-/* The RTL8139 can only transmit from a contiguous, aligned memory block.  */
-static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
-static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
-
-static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
-static int read_eeprom(int location, int addr_len);
-static void rtl_reset(struct eth_device *dev);
-static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
-static int rtl_poll(struct eth_device *dev);
-static void rtl_disable(struct eth_device *dev);
-
-static struct pci_device_id supported[] = {
-       {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
-       {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
-       {}
-};
-
-int rtl8139_initialize(bd_t *bis)
-{
-	pci_dev_t devno;
-	int card_number = 0;
-	struct eth_device *dev;
-	u32 iobase;
-	int idx=0;
-
-	while(1){
-		/* Find RTL8139 */
-		if ((devno = pci_find_devices(supported, idx++)) < 0)
-			break;
-
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
-		iobase &= ~0xf;
-
-		debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
-
-		dev = (struct eth_device *)malloc(sizeof *dev);
-
-		sprintf (dev->name, "RTL8139#%d", card_number);
-
-		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
-		dev->init = rtl8139_probe;
-		dev->halt = rtl_disable;
-		dev->send = rtl_transmit;
-		dev->recv = rtl_poll;
-
-		eth_register (dev);
-
-		card_number++;
-
-		pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
-
-		udelay (10 * 1000);
-	}
-
-	return card_number;
-}
-
-static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
-{
-	int i;
-	int speed10, fullduplex;
-	int addr_len;
-	unsigned short *ap = (unsigned short *)dev->enetaddr;
-
-	ioaddr = dev->iobase;
-
-	/* Bring the chip out of low-power mode. */
-	outb(0x00, ioaddr + Config1);
-
-	addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
-	for (i = 0; i < 3; i++)
-		*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
-
-	speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
-	fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
-
-	rtl_reset(dev);
-
-	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
-		printf("Cable not connected or other link failure\n");
-		return(0);
-	}
-
-	return 1;
-}
-
-/* Serial EEPROM section. */
-
-/*  EEPROM_Ctrl bits. */
-#define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
-#define EE_CS		0x08	/* EEPROM chip select. */
-#define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
-#define EE_WRITE_0	0x00
-#define EE_WRITE_1	0x02
-#define EE_DATA_READ	0x01	/* EEPROM chip data out. */
-#define EE_ENB		(0x80 | EE_CS)
-
-/*
-	Delay between EEPROM clock transitions.
-	No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
-*/
-
-#define eeprom_delay()	inl(ee_addr)
-
-/* The EEPROM commands include the alway-set leading bit. */
-#define EE_WRITE_CMD	(5)
-#define EE_READ_CMD	(6)
-#define EE_ERASE_CMD	(7)
-
-static int read_eeprom(int location, int addr_len)
-{
-	int i;
-	unsigned int retval = 0;
-	long ee_addr = ioaddr + Cfg9346;
-	int read_cmd = location | (EE_READ_CMD << addr_len);
-
-	outb(EE_ENB & ~EE_CS, ee_addr);
-	outb(EE_ENB, ee_addr);
-	eeprom_delay();
-
-	/* Shift the read command bits out. */
-	for (i = 4 + addr_len; i >= 0; i--) {
-		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
-		outb(EE_ENB | dataval, ee_addr);
-		eeprom_delay();
-		outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
-	}
-	outb(EE_ENB, ee_addr);
-	eeprom_delay();
-
-	for (i = 16; i > 0; i--) {
-		outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
-		retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
-		outb(EE_ENB, ee_addr);
-		eeprom_delay();
-	}
-
-	/* Terminate the EEPROM access. */
-	outb(~EE_CS, ee_addr);
-	eeprom_delay();
-	return retval;
-}
-
-static const unsigned int rtl8139_rx_config =
-	(RX_BUF_LEN_IDX << 11) |
-	(RX_FIFO_THRESH << 13) |
-	(RX_DMA_BURST << 8);
-
-static void set_rx_mode(struct eth_device *dev) {
-	unsigned int mc_filter[2];
-	int rx_mode;
-	/* !IFF_PROMISC */
-	rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
-	mc_filter[1] = mc_filter[0] = 0xffffffff;
-
-	outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
-
-	outl(mc_filter[0], ioaddr + MAR0 + 0);
-	outl(mc_filter[1], ioaddr + MAR0 + 4);
-}
-
-static void rtl_reset(struct eth_device *dev)
-{
-	int i;
-
-	outb(CmdReset, ioaddr + ChipCmd);
-
-	cur_rx = 0;
-	cur_tx = 0;
-
-	/* Give the chip 10ms to finish the reset. */
-	for (i=0; i<100; ++i){
-		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-		udelay (100); /* wait 100us */
-	}
-
-
-	for (i = 0; i < ETH_ALEN; i++)
-		outb(dev->enetaddr[i], ioaddr + MAC0 + i);
-
-	/* Must enable Tx/Rx before setting transfer thresholds! */
-	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
-	outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
-		ioaddr + RxConfig);		/* accept no frames yet!  */
-	outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
-
-	/* The Linux driver changes Config1 here to use a different LED pattern
-	 * for half duplex or full/autodetect duplex (for full/autodetect, the
-	 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
-	 * TX/RX, Link100, Link10).  This is messy, because it doesn't match
-	 * the inscription on the mounting bracket.  It should not be changed
-	 * from the configuration EEPROM default, because the card manufacturer
-	 * should have set that to match the card.  */
-
-#ifdef	DEBUG_RX
-	printf("rx ring address is %X\n",(unsigned long)rx_ring);
-#endif
-	outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
-
-	/* If we add multicast support, the MAR0 register would have to be
-	 * initialized to 0xffffffffffffffff (two 32 bit accesses).  Etherboot
-	 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast.	*/
-
-	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
-
-	outl(rtl8139_rx_config, ioaddr + RxConfig);
-
-	/* Start the chip's Tx and Rx process. */
-	outl(0, ioaddr + RxMissed);
-
-	/* set_rx_mode */
-	set_rx_mode(dev);
-
-	/* Disable all known interrupts by setting the interrupt mask. */
-	outw(0, ioaddr + IntrMask);
-}
-
-static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
-{
-	unsigned int status, to;
-	unsigned long txstatus;
-	unsigned int len = length;
-
-	ioaddr = dev->iobase;
-
-	memcpy((char *)tx_buffer, (char *)packet, (int)length);
-
-#ifdef	DEBUG_TX
-	printf("sending %d bytes\n", len);
-#endif
-
-	/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
-	 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
-	while (len < ETH_ZLEN) {
-		tx_buffer[len++] = '\0';
-	}
-
-	outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
-	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
-		ioaddr + TxStatus0 + cur_tx*4);
-
-	to = currticks() + RTL_TIMEOUT;
-
-	do {
-		status = inw(ioaddr + IntrStatus);
-		/* Only acknlowledge interrupt sources we can properly handle
-		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
-		 * rtl_poll() function.	 */
-		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
-		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
-	} while (currticks() < to);
-
-	txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
-
-	if (status & TxOK) {
-		cur_tx = (cur_tx + 1) % NUM_TX_DESC;
-#ifdef	DEBUG_TX
-		printf("tx done (%d ticks), status %hX txstatus %X\n",
-			to-currticks(), status, txstatus);
-#endif
-		return length;
-	} else {
-#ifdef	DEBUG_TX
-		printf("tx timeout/error (%d ticks), status %hX txstatus %X\n",
-			currticks()-to, status, txstatus);
-#endif
-		rtl_reset(dev);
-
-		return 0;
-	}
-}
-
-static int rtl_poll(struct eth_device *dev)
-{
-	unsigned int status;
-	unsigned int ring_offs;
-	unsigned int rx_size, rx_status;
-	int length=0;
-
-	ioaddr = dev->iobase;
-
-	if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
-		return 0;
-	}
-
-	status = inw(ioaddr + IntrStatus);
-	/* See below for the rest of the interrupt acknowledges.  */
-	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
-
-#ifdef	DEBUG_RX
-	printf("rtl_poll: int %hX ", status);
-#endif
-
-	ring_offs = cur_rx % RX_BUF_LEN;
-	rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs));
-	rx_size = rx_status >> 16;
-	rx_status &= 0xffff;
-
-	if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
-	    (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
-		printf("rx error %hX\n", rx_status);
-		rtl_reset(dev); /* this clears all interrupts still pending */
-		return 0;
-	}
-
-	/* Received a good packet */
-	length = rx_size - 4;	/* no one cares about the FCS */
-	if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
-		int semi_count = RX_BUF_LEN - ring_offs - 4;
-		unsigned char rxdata[RX_BUF_LEN];
-
-		memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
-		memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
-
-		NetReceive(rxdata, length);
-#ifdef	DEBUG_RX
-		printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
-#endif
-	} else {
-		NetReceive(rx_ring + ring_offs + 4, length);
-#ifdef	DEBUG_RX
-		printf("rx packet %d bytes", rx_size-4);
-#endif
-	}
-
-	cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
-	outw(cur_rx - 16, ioaddr + RxBufPtr);
-	/* See RTL8139 Programming Guide V0.1 for the official handling of
-	 * Rx overflow situations.  The document itself contains basically no
-	 * usable information, except for a few exception handling rules.  */
-	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
-	return length;
-}
-
-static void rtl_disable(struct eth_device *dev)
-{
-	int i;
-
-	ioaddr = dev->iobase;
-
-	/* reset the chip */
-	outb(CmdReset, ioaddr + ChipCmd);
-
-	/* Give the chip 10ms to finish the reset. */
-	for (i=0; i<100; ++i){
-		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-		udelay (100); /* wait 100us */
-	}
-}
-#endif	/* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
deleted file mode 100644
index f9dcf9dc7c..0000000000
--- a/drivers/net/rtl8169.c
+++ /dev/null
@@ -1,876 +0,0 @@
-/*
- * rtl8169.c : U-Boot driver for the RealTek RTL8169
- *
- * Masami Komiya (mkomiya@sonare.it)
- *
- * Most part is taken from r8169.c of etherboot
- *
- */
-
-/**************************************************************************
-*    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
-*    Written 2003 by Timothy Legge <tlegge@rogers.com>
-*
-*    This program is free software; you can redistribute it and/or modify
-*    it under the terms of the GNU General Public License as published by
-*    the Free Software Foundation; either version 2 of the License, or
-*    (at your option) any later version.
-*
-*    This program is distributed in the hope that it will be useful,
-*    but WITHOUT ANY WARRANTY; without even the implied warranty of
-*    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-*    GNU General Public License for more details.
-*
-*    You should have received a copy of the GNU General Public License
-*    along with this program; if not, write to the Free Software
-*    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-*    Portions of this code based on:
-*	r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
-*		for Linux kernel 2.4.x.
-*
-*    Written 2002 ShuChen <shuchen@realtek.com.tw>
-*	  See Linux Driver for full information
-*
-*    Linux Driver Version 1.27a, 10.02.2002
-*
-*    Thanks to:
-*	Jean Chen of RealTek Semiconductor Corp. for
-*	providing the evaluation NIC used to develop
-*	this driver.  RealTek's support for Etherboot
-*	is appreciated.
-*
-*    REVISION HISTORY:
-*    ================
-*
-*    v1.0	11-26-2003	timlegge	Initial port of Linux driver
-*    v1.5	01-17-2004	timlegge	Initial driver output cleanup
-*
-*    Indent Options: indent -kr -i8
-***************************************************************************/
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
-	defined(CONFIG_RTL8169)
-
-#undef DEBUG_RTL8169
-#undef DEBUG_RTL8169_TX
-#undef DEBUG_RTL8169_RX
-
-#define drv_version "v1.5"
-#define drv_date "01-17-2004"
-
-static u32 ioaddr;
-
-/* Condensed operations for readability. */
-#define virt_to_le32desc(addr)	cpu_to_le32(virt_to_bus(addr))
-#define le32desc_to_virt(addr)	bus_to_virt(le32_to_cpu(addr))
-
-#define currticks()	get_timer(0)
-#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
-
-/* media options */
-#define MAX_UNITS 8
-static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
-
-/* MAC address length*/
-#define MAC_ADDR_LEN	6
-
-/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
-#define MAX_ETH_FRAME_SIZE	1536
-
-#define TX_FIFO_THRESH 256	/* In bytes */
-
-#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer.	 */
-#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
-#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
-#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */
-#define RxPacketMaxSize 0x0800	/* Maximum size supported is 16K-1 */
-#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
-
-#define NUM_TX_DESC	1	/* Number of Tx descriptor registers */
-#define NUM_RX_DESC	4	/* Number of Rx descriptor registers */
-#define RX_BUF_SIZE	1536	/* Rx Buffer size */
-#define RX_BUF_LEN	8192
-
-#define RTL_MIN_IO_SIZE 0x80
-#define TX_TIMEOUT  (6*HZ)
-
-/* write/read MMIO register */
-#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
-#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
-#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
-#define RTL_R8(reg)		readb (ioaddr + (reg))
-#define RTL_R16(reg)		readw (ioaddr + (reg))
-#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
-
-#define ETH_FRAME_LEN	MAX_ETH_FRAME_SIZE
-#define ETH_ALEN	MAC_ADDR_LEN
-#define ETH_ZLEN	60
-
-enum RTL8169_registers {
-	MAC0 = 0,		/* Ethernet hardware address. */
-	MAR0 = 8,		/* Multicast filter. */
-	TxDescStartAddr = 0x20,
-	TxHDescStartAddr = 0x28,
-	FLASH = 0x30,
-	ERSR = 0x36,
-	ChipCmd = 0x37,
-	TxPoll = 0x38,
-	IntrMask = 0x3C,
-	IntrStatus = 0x3E,
-	TxConfig = 0x40,
-	RxConfig = 0x44,
-	RxMissed = 0x4C,
-	Cfg9346 = 0x50,
-	Config0 = 0x51,
-	Config1 = 0x52,
-	Config2 = 0x53,
-	Config3 = 0x54,
-	Config4 = 0x55,
-	Config5 = 0x56,
-	MultiIntr = 0x5C,
-	PHYAR = 0x60,
-	TBICSR = 0x64,
-	TBI_ANAR = 0x68,
-	TBI_LPAR = 0x6A,
-	PHYstatus = 0x6C,
-	RxMaxSize = 0xDA,
-	CPlusCmd = 0xE0,
-	RxDescStartAddr = 0xE4,
-	EarlyTxThres = 0xEC,
-	FuncEvent = 0xF0,
-	FuncEventMask = 0xF4,
-	FuncPresetState = 0xF8,
-	FuncForceEvent = 0xFC,
-};
-
-enum RTL8169_register_content {
-	/*InterruptStatusBits */
-	SYSErr = 0x8000,
-	PCSTimeout = 0x4000,
-	SWInt = 0x0100,
-	TxDescUnavail = 0x80,
-	RxFIFOOver = 0x40,
-	RxUnderrun = 0x20,
-	RxOverflow = 0x10,
-	TxErr = 0x08,
-	TxOK = 0x04,
-	RxErr = 0x02,
-	RxOK = 0x01,
-
-	/*RxStatusDesc */
-	RxRES = 0x00200000,
-	RxCRC = 0x00080000,
-	RxRUNT = 0x00100000,
-	RxRWT = 0x00400000,
-
-	/*ChipCmdBits */
-	CmdReset = 0x10,
-	CmdRxEnb = 0x08,
-	CmdTxEnb = 0x04,
-	RxBufEmpty = 0x01,
-
-	/*Cfg9346Bits */
-	Cfg9346_Lock = 0x00,
-	Cfg9346_Unlock = 0xC0,
-
-	/*rx_mode_bits */
-	AcceptErr = 0x20,
-	AcceptRunt = 0x10,
-	AcceptBroadcast = 0x08,
-	AcceptMulticast = 0x04,
-	AcceptMyPhys = 0x02,
-	AcceptAllPhys = 0x01,
-
-	/*RxConfigBits */
-	RxCfgFIFOShift = 13,
-	RxCfgDMAShift = 8,
-
-	/*TxConfigBits */
-	TxInterFrameGapShift = 24,
-	TxDMAShift = 8,		/* DMA burst value (0-7) is shift this many bits */
-
-	/*rtl8169_PHYstatus */
-	TBI_Enable = 0x80,
-	TxFlowCtrl = 0x40,
-	RxFlowCtrl = 0x20,
-	_1000bpsF = 0x10,
-	_100bps = 0x08,
-	_10bps = 0x04,
-	LinkStatus = 0x02,
-	FullDup = 0x01,
-
-	/*GIGABIT_PHY_registers */
-	PHY_CTRL_REG = 0,
-	PHY_STAT_REG = 1,
-	PHY_AUTO_NEGO_REG = 4,
-	PHY_1000_CTRL_REG = 9,
-
-	/*GIGABIT_PHY_REG_BIT */
-	PHY_Restart_Auto_Nego = 0x0200,
-	PHY_Enable_Auto_Nego = 0x1000,
-
-	/* PHY_STAT_REG = 1; */
-	PHY_Auto_Neco_Comp = 0x0020,
-
-	/* PHY_AUTO_NEGO_REG = 4; */
-	PHY_Cap_10_Half = 0x0020,
-	PHY_Cap_10_Full = 0x0040,
-	PHY_Cap_100_Half = 0x0080,
-	PHY_Cap_100_Full = 0x0100,
-
-	/* PHY_1000_CTRL_REG = 9; */
-	PHY_Cap_1000_Full = 0x0200,
-
-	PHY_Cap_Null = 0x0,
-
-	/*_MediaType*/
-	_10_Half = 0x01,
-	_10_Full = 0x02,
-	_100_Half = 0x04,
-	_100_Full = 0x08,
-	_1000_Full = 0x10,
-
-	/*_TBICSRBit*/
-	TBILinkOK = 0x02000000,
-};
-
-static struct {
-	const char *name;
-	u8 version;		/* depend on RTL8169 docs */
-	u32 RxConfigMask;	/* should clear the bits supported by this chip */
-} rtl_chip_info[] = {
-	{"RTL-8169", 0x00, 0xff7e1880,},
-	{"RTL-8169", 0x04, 0xff7e1880,},
-};
-
-enum _DescStatusBit {
-	OWNbit = 0x80000000,
-	EORbit = 0x40000000,
-	FSbit = 0x20000000,
-	LSbit = 0x10000000,
-};
-
-struct TxDesc {
-	u32 status;
-	u32 vlan_tag;
-	u32 buf_addr;
-	u32 buf_Haddr;
-};
-
-struct RxDesc {
-	u32 status;
-	u32 vlan_tag;
-	u32 buf_addr;
-	u32 buf_Haddr;
-};
-
-/* Define the TX Descriptor */
-static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
-/*	__attribute__ ((aligned(256))); */
-
-/* Create a static buffer of size RX_BUF_SZ for each
-TX Descriptor.	All descriptors point to a
-part of this buffer */
-static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
-
-/* Define the RX Descriptor */
-static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
-  /*  __attribute__ ((aligned(256))); */
-
-/* Create a static buffer of size RX_BUF_SZ for each
-RX Descriptor	All descriptors point to a
-part of this buffer */
-static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
-
-struct rtl8169_private {
-	void *mmio_addr;	/* memory map physical address */
-	int chipset;
-	unsigned long cur_rx;	/* Index into the Rx descriptor buffer of next Rx pkt. */
-	unsigned long cur_tx;	/* Index into the Tx descriptor buffer of next Rx pkt. */
-	unsigned long dirty_tx;
-	unsigned char *TxDescArrays;	/* Index of Tx Descriptor buffer */
-	unsigned char *RxDescArrays;	/* Index of Rx Descriptor buffer */
-	struct TxDesc *TxDescArray;	/* Index of 256-alignment Tx Descriptor buffer */
-	struct RxDesc *RxDescArray;	/* Index of 256-alignment Rx Descriptor buffer */
-	unsigned char *RxBufferRings;	/* Index of Rx Buffer  */
-	unsigned char *RxBufferRing[NUM_RX_DESC];	/* Index of Rx Buffer array */
-	unsigned char *Tx_skbuff[NUM_TX_DESC];
-} tpx;
-
-static struct rtl8169_private *tpc;
-
-static const u16 rtl8169_intr_mask =
-    SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
-    TxOK | RxErr | RxOK;
-static const unsigned int rtl8169_rx_config =
-    (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
-
-static struct pci_device_id supported[] = {
-	{PCI_VENDOR_ID_REALTEK, 0x8169},
-	{}
-};
-
-void mdio_write(int RegAddr, int value)
-{
-	int i;
-
-	RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
-	udelay(1000);
-
-	for (i = 2000; i > 0; i--) {
-		/* Check if the RTL8169 has completed writing to the specified MII register */
-		if (!(RTL_R32(PHYAR) & 0x80000000)) {
-			break;
-		} else {
-			udelay(100);
-		}
-	}
-}
-
-int mdio_read(int RegAddr)
-{
-	int i, value = -1;
-
-	RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
-	udelay(1000);
-
-	for (i = 2000; i > 0; i--) {
-		/* Check if the RTL8169 has completed retrieving data from the specified MII register */
-		if (RTL_R32(PHYAR) & 0x80000000) {
-			value = (int) (RTL_R32(PHYAR) & 0xFFFF);
-			break;
-		} else {
-			udelay(100);
-		}
-	}
-	return value;
-}
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static int rtl8169_init_board(struct eth_device *dev)
-{
-	int i;
-	u32 tmp;
-
-#ifdef DEBUG_RTL8169
-	printf ("%s\n", __FUNCTION__);
-#endif
-	ioaddr = dev->iobase;
-
-	/* Soft reset the chip. */
-	RTL_W8(ChipCmd, CmdReset);
-
-	/* Check that the chip has finished the reset. */
-	for (i = 1000; i > 0; i--)
-		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
-			break;
-		else
-			udelay(10);
-
-	/* identify chip attached to board */
-	tmp = RTL_R32(TxConfig);
-	tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
-
-	for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
-		if (tmp == rtl_chip_info[i].version) {
-			tpc->chipset = i;
-			goto match;
-		}
-	}
-
-	/* if unknown chip, assume array element #0, original RTL-8169 in this case */
-	printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
-	printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig));
-	tpc->chipset = 0;
-
-match:
-	return 0;
-}
-
-/**************************************************************************
-RECV - Receive a frame
-***************************************************************************/
-static int rtl_recv(struct eth_device *dev)
-{
-	/* return true if there's an ethernet packet ready to read */
-	/* nic->packet should contain data on return */
-	/* nic->packetlen should contain length of data */
-	int cur_rx;
-	int length = 0;
-
-#ifdef DEBUG_RTL8169_RX
-	printf ("%s\n", __FUNCTION__);
-#endif
-	ioaddr = dev->iobase;
-
-	cur_rx = tpc->cur_rx;
-	if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
-		if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
-			unsigned char rxdata[RX_BUF_LEN];
-			length = (int) (tpc->RxDescArray[cur_rx].
-						status & 0x00001FFF) - 4;
-
-			memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
-			NetReceive(rxdata, length);
-
-			if (cur_rx == NUM_RX_DESC - 1)
-				tpc->RxDescArray[cur_rx].status =
-				    (OWNbit | EORbit) + RX_BUF_SIZE;
-			else
-				tpc->RxDescArray[cur_rx].status =
-				    OWNbit + RX_BUF_SIZE;
-			tpc->RxDescArray[cur_rx].buf_addr =
-			    virt_to_bus(tpc->RxBufferRing[cur_rx]);
-		} else {
-			puts("Error Rx");
-		}
-		cur_rx = (cur_rx + 1) % NUM_RX_DESC;
-		tpc->cur_rx = cur_rx;
-		return 1;
-
-	}
-	tpc->cur_rx = cur_rx;
-	return (0);		/* initially as this is called to flush the input */
-}
-
-#define HZ 1000
-/**************************************************************************
-SEND - Transmit a frame
-***************************************************************************/
-static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
-{
-	/* send the packet to destination */
-
-	u32 to;
-	u8 *ptxb;
-	int entry = tpc->cur_tx % NUM_TX_DESC;
-	u32 len = length;
-
-#ifdef DEBUG_RTL8169_TX
-	int stime = currticks();
-	printf ("%s\n", __FUNCTION__);
-	printf("sending %d bytes\n", len);
-#endif
-
-	ioaddr = dev->iobase;
-
-	/* point to the current txb incase multiple tx_rings are used */
-	ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
-	memcpy(ptxb, (char *)packet, (int)length);
-
-	while (len < ETH_ZLEN)
-		ptxb[len++] = '\0';
-
-	tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
-	if (entry != (NUM_TX_DESC - 1)) {
-		tpc->TxDescArray[entry].status =
-		    (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ?
-						len : ETH_ZLEN);
-	} else {
-		tpc->TxDescArray[entry].status =
-		    (OWNbit | EORbit | FSbit | LSbit) |
-		    ((len > ETH_ZLEN) ? length : ETH_ZLEN);
-	}
-	RTL_W8(TxPoll, 0x40);	/* set polling bit */
-
-	tpc->cur_tx++;
-	to = currticks() + TX_TIMEOUT;
-	while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));	/* wait */
-
-	if (currticks() >= to) {
-#ifdef DEBUG_RTL8169_TX
-		puts ("tx timeout/error\n");
-		printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
-#endif
-		return 0;
-	} else {
-#ifdef DEBUG_RTL8169_TX
-		puts("tx done\n");
-#endif
-		return length;
-	}
-}
-
-static void rtl8169_set_rx_mode(struct eth_device *dev)
-{
-	u32 mc_filter[2];	/* Multicast hash filter */
-	int rx_mode;
-	u32 tmp = 0;
-
-#ifdef DEBUG_RTL8169
-	printf ("%s\n", __FUNCTION__);
-#endif
-
-	/* IFF_ALLMULTI */
-	/* Too many to filter perfectly -- accept all multicasts. */
-	rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
-	mc_filter[1] = mc_filter[0] = 0xffffffff;
-
-	tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
-				   rtl_chip_info[tpc->chipset].RxConfigMask);
-
-	RTL_W32(RxConfig, tmp);
-	RTL_W32(MAR0 + 0, mc_filter[0]);
-	RTL_W32(MAR0 + 4, mc_filter[1]);
-}
-
-static void rtl8169_hw_start(struct eth_device *dev)
-{
-	u32 i;
-
-#ifdef DEBUG_RTL8169
-	int stime = currticks();
-	printf ("%s\n", __FUNCTION__);
-#endif
-
-
-	RTL_W8(Cfg9346, Cfg9346_Unlock);
-	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
-	RTL_W8(EarlyTxThres, EarlyTxThld);
-
-	/* For gigabit rtl8169 */
-	RTL_W16(RxMaxSize, RxPacketMaxSize);
-
-	/* Set Rx Config register */
-	i = rtl8169_rx_config | (RTL_R32(RxConfig) &
-				 rtl_chip_info[tpc->chipset].RxConfigMask);
-	RTL_W32(RxConfig, i);
-
-	/* Set DMA burst size and Interframe Gap Time */
-	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
-				(InterFrameGap << TxInterFrameGapShift));
-
-
-	tpc->cur_rx = 0;
-
-	RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
-	RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
-	RTL_W8(Cfg9346, Cfg9346_Lock);
-	udelay(10);
-
-	RTL_W32(RxMissed, 0);
-
-	rtl8169_set_rx_mode(dev);
-
-	/* no early-rx interrupts */
-	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
-
-#ifdef DEBUG_RTL8169
-	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
-#endif
-}
-
-static void rtl8169_init_ring(struct eth_device *dev)
-{
-	int i;
-
-#ifdef DEBUG_RTL8169
-	int stime = currticks();
-	printf ("%s\n", __FUNCTION__);
-#endif
-
-	tpc->cur_rx = 0;
-	tpc->cur_tx = 0;
-	tpc->dirty_tx = 0;
-	memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
-	memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
-
-	for (i = 0; i < NUM_TX_DESC; i++) {
-		tpc->Tx_skbuff[i] = &txb[i];
-	}
-
-	for (i = 0; i < NUM_RX_DESC; i++) {
-		if (i == (NUM_RX_DESC - 1))
-			tpc->RxDescArray[i].status =
-			    (OWNbit | EORbit) + RX_BUF_SIZE;
-		else
-			tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
-
-		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
-		tpc->RxDescArray[i].buf_addr =
-		    virt_to_bus(tpc->RxBufferRing[i]);
-	}
-
-#ifdef DEBUG_RTL8169
-	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
-#endif
-}
-
-/**************************************************************************
-RESET - Finish setting up the ethernet interface
-***************************************************************************/
-static void rtl_reset(struct eth_device *dev, bd_t *bis)
-{
-	int i;
-	u8 diff;
-	u32 TxPhyAddr, RxPhyAddr;
-
-#ifdef DEBUG_RTL8169
-	int stime = currticks();
-	printf ("%s\n", __FUNCTION__);
-#endif
-
-	tpc->TxDescArrays = tx_ring;
-	if (tpc->TxDescArrays == 0)
-		puts("Allot Error");
-	/* Tx Desscriptor needs 256 bytes alignment; */
-	TxPhyAddr = virt_to_bus(tpc->TxDescArrays);
-	diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
-	TxPhyAddr += diff;
-	tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff);
-
-	tpc->RxDescArrays = rx_ring;
-	/* Rx Desscriptor needs 256 bytes alignment; */
-	RxPhyAddr = virt_to_bus(tpc->RxDescArrays);
-	diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
-	RxPhyAddr += diff;
-	tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff);
-
-	if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) {
-		puts("Allocate RxDescArray or TxDescArray failed\n");
-		return;
-	}
-
-	rtl8169_init_ring(dev);
-	rtl8169_hw_start(dev);
-	/* Construct a perfect filter frame with the mac address as first match
-	 * and broadcast for all others */
-	for (i = 0; i < 192; i++)
-		txb[i] = 0xFF;
-
-	txb[0] = dev->enetaddr[0];
-	txb[1] = dev->enetaddr[1];
-	txb[2] = dev->enetaddr[2];
-	txb[3] = dev->enetaddr[3];
-	txb[4] = dev->enetaddr[4];
-	txb[5] = dev->enetaddr[5];
-
-#ifdef DEBUG_RTL8169
-	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
-#endif
-}
-
-/**************************************************************************
-HALT - Turn off ethernet interface
-***************************************************************************/
-static void rtl_halt(struct eth_device *dev)
-{
-	int i;
-
-#ifdef DEBUG_RTL8169
-	printf ("%s\n", __FUNCTION__);
-#endif
-
-	ioaddr = dev->iobase;
-
-	/* Stop the chip's Tx and Rx DMA processes. */
-	RTL_W8(ChipCmd, 0x00);
-
-	/* Disable interrupts by clearing the interrupt mask. */
-	RTL_W16(IntrMask, 0x0000);
-
-	RTL_W32(RxMissed, 0);
-
-	tpc->TxDescArrays = NULL;
-	tpc->RxDescArrays = NULL;
-	tpc->TxDescArray = NULL;
-	tpc->RxDescArray = NULL;
-	for (i = 0; i < NUM_RX_DESC; i++) {
-		tpc->RxBufferRing[i] = NULL;
-	}
-}
-
-/**************************************************************************
-INIT - Look for an adapter, this routine's visible to the outside
-***************************************************************************/
-
-#define board_found 1
-#define valid_link 0
-static int rtl_init(struct eth_device *dev, bd_t *bis)
-{
-	static int board_idx = -1;
-	static int printed_version = 0;
-	int i, rc;
-	int option = -1, Cap10_100 = 0, Cap1000 = 0;
-
-#ifdef DEBUG_RTL8169
-	printf ("%s\n", __FUNCTION__);
-#endif
-
-	ioaddr = dev->iobase;
-
-	board_idx++;
-
-	printed_version = 1;
-
-	/* point to private storage */
-	tpc = &tpx;
-
-	rc = rtl8169_init_board(dev);
-	if (rc)
-		return rc;
-
-	/* Get MAC address.  FIXME: read EEPROM */
-	for (i = 0; i < MAC_ADDR_LEN; i++)
-		dev->enetaddr[i] = RTL_R8(MAC0 + i);
-
-#ifdef DEBUG_RTL8169
-	printf("MAC Address");
-	for (i = 0; i < MAC_ADDR_LEN; i++)
-		printf(":%02x", dev->enetaddr[i]);
-	putc('\n');
-#endif
-
-#ifdef DEBUG_RTL8169
-	/* Print out some hardware info */
-	printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
-#endif
-
-	/* if TBI is not endbled */
-	if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
-		int val = mdio_read(PHY_AUTO_NEGO_REG);
-
-		option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
-		/* Force RTL8169 in 10/100/1000 Full/Half mode. */
-		if (option > 0) {
-#ifdef DEBUG_RTL8169
-			printf("%s: Force-mode Enabled.\n", dev->name);
-#endif
-			Cap10_100 = 0, Cap1000 = 0;
-			switch (option) {
-			case _10_Half:
-				Cap10_100 = PHY_Cap_10_Half;
-				Cap1000 = PHY_Cap_Null;
-				break;
-			case _10_Full:
-				Cap10_100 = PHY_Cap_10_Full;
-				Cap1000 = PHY_Cap_Null;
-				break;
-			case _100_Half:
-				Cap10_100 = PHY_Cap_100_Half;
-				Cap1000 = PHY_Cap_Null;
-				break;
-			case _100_Full:
-				Cap10_100 = PHY_Cap_100_Full;
-				Cap1000 = PHY_Cap_Null;
-				break;
-			case _1000_Full:
-				Cap10_100 = PHY_Cap_Null;
-				Cap1000 = PHY_Cap_1000_Full;
-				break;
-			default:
-				break;
-			}
-			mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F));	/* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
-			mdio_write(PHY_1000_CTRL_REG, Cap1000);
-		} else {
-#ifdef DEBUG_RTL8169
-			printf("%s: Auto-negotiation Enabled.\n",
-			       dev->name);
-#endif
-			/* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
-			mdio_write(PHY_AUTO_NEGO_REG,
-				   PHY_Cap_10_Half | PHY_Cap_10_Full |
-				   PHY_Cap_100_Half | PHY_Cap_100_Full |
-				   (val & 0x1F));
-
-			/* enable 1000 Full Mode */
-			mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
-
-		}
-
-		/* Enable auto-negotiation and restart auto-nigotiation */
-		mdio_write(PHY_CTRL_REG,
-			   PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
-		udelay(100);
-
-		/* wait for auto-negotiation process */
-		for (i = 10000; i > 0; i--) {
-			/* check if auto-negotiation complete */
-			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
-				udelay(100);
-				option = RTL_R8(PHYstatus);
-				if (option & _1000bpsF) {
-#ifdef DEBUG_RTL8169
-					printf("%s: 1000Mbps Full-duplex operation.\n",
-					     dev->name);
-#endif
-				} else {
-#ifdef DEBUG_RTL8169
-					printf
-					    ("%s: %sMbps %s-duplex operation.\n",
-					     dev->name,
-					     (option & _100bps) ? "100" :
-					     "10",
-					     (option & FullDup) ? "Full" :
-					     "Half");
-#endif
-				}
-				break;
-			} else {
-				udelay(100);
-			}
-		}		/* end for-loop to wait for auto-negotiation process */
-
-	} else {
-		udelay(100);
-#ifdef DEBUG_RTL8169
-		printf
-		    ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
-		     dev->name,
-		     (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
-#endif
-	}
-
-	return 1;
-}
-
-int rtl8169_initialize(bd_t *bis)
-{
-	pci_dev_t devno;
-	int card_number = 0;
-	struct eth_device *dev;
-	u32 iobase;
-	int idx=0;
-
-	while(1){
-		/* Find RTL8169 */
-		if ((devno = pci_find_devices(supported, idx++)) < 0)
-			break;
-
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
-		iobase &= ~0xf;
-
-		debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
-
-		dev = (struct eth_device *)malloc(sizeof *dev);
-
-		sprintf (dev->name, "RTL8169#%d", card_number);
-
-		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
-
-		dev->init = rtl_reset;
-		dev->halt = rtl_halt;
-		dev->send = rtl_send;
-		dev->recv = rtl_recv;
-
-		eth_register (dev);
-
-		rtl_init(dev, bis);
-
-		card_number++;
-	}
-	return card_number;
-}
-
-#endif
diff --git a/drivers/net/s3c4510b_eth.c b/drivers/net/s3c4510b_eth.c
deleted file mode 100644
index 48901aa12f..0000000000
--- a/drivers/net/s3c4510b_eth.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/***********************************************************************
- *
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description:   Ethernet interface for Samsung S3C4510B SoC
- */
-
-#include <common.h>
-
-#ifdef CONFIG_DRIVER_S3C4510_ETH
-
-#include <command.h>
-#include <net.h>
-#include <asm/hardware.h>
-#include "s3c4510b_eth.h"
-
-static TX_FrameDescriptor    txFDbase[ETH_MaxTxFrames];
-static MACFrame           txFrameBase[ETH_MaxTxFrames];
-static RX_FrameDescriptor    rxFDbase[PKTBUFSRX];
-static ETH                      m_eth;
-
-static s32 TxFDinit( ETH *eth) {
-
-	s32 i;
-	MACFrame *txFrmBase;
-
-	/* disable cache for access to the TX buffers */
-	txFrmBase = (MACFrame *)( (u32)txFrameBase | CACHE_DISABLE_MASK);
-
-	/* store start of Tx descriptors and set current */
-	eth->m_curTX_FD  =  (TX_FrameDescriptor *) ((u32)txFDbase | CACHE_DISABLE_MASK);
-	eth->m_baseTX_FD = eth->m_curTX_FD;
-
-	for ( i = 0; i < ETH_MaxTxFrames; i++) {
-		eth->m_baseTX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)&txFrmBase[i];
-		eth->m_baseTX_FD[i].m_frameDataPtr.bf.owner   = 0x0; /* CPU owner */
-		eth->m_baseTX_FD[i].m_opt.ui                  = 0x0;
-		eth->m_baseTX_FD[i].m_status.ui               = 0x0;
-		eth->m_baseTX_FD[i].m_nextFD                  = &eth->m_baseTX_FD[i+1];
-	}
-
-	/* make the list circular */
-	eth->m_baseTX_FD[i-1].m_nextFD          = &eth->m_baseTX_FD[0];
-
-	PUT_REG( REG_BDMATXPTR, (u32)eth->m_curTX_FD);
-
-	return 0;
-}
-
-static s32 RxFDinit( ETH *eth) {
-
-	s32 i;
-	/*  MACFrame *rxFrmBase; */
-
-	/* disable cache for access to the RX buffers */
-	/*  rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */
-
-	/* store start of Rx descriptors and set current */
-	eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | CACHE_DISABLE_MASK);
-	eth->m_baseRX_FD = eth->m_curRX_FD;
-	for ( i = 0; i < PKTBUFSRX; i++) {
-		eth->m_baseRX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)NetRxPackets[i] | CACHE_DISABLE_MASK;
-		eth->m_baseRX_FD[i].m_frameDataPtr.bf.owner   = 0x1; /* BDMA owner */
-		eth->m_baseRX_FD[i].m_reserved                = 0x0;
-		eth->m_baseRX_FD[i].m_status.ui               = 0x0;
-		eth->m_baseRX_FD[i].m_nextFD                  = &eth->m_baseRX_FD[i+1];
-	}
-
-	/* make the list circular */
-	eth->m_baseRX_FD[i-1].m_nextFD                  = &eth->m_baseRX_FD[0];
-
-	PUT_REG( REG_BDMARXPTR, (u32)eth->m_curRX_FD);
-
-	return 0;
-}
-
-/*
- * Public u-boot interface functions below
- */
-
-int eth_init(bd_t *bis)
-{
-
-	ETH *eth = &m_eth;
-
-	/* store our MAC address */
-	eth->m_mac = bis->bi_enetaddr;
-
-	/* setup DBMA and MAC */
-	PUT_REG( REG_BDMARXCON, ETH_BRxRS);   /* reset BDMA RX machine */
-	PUT_REG( REG_BDMATXCON, ETH_BTxRS);   /* reset BDMA TX machine */
-	PUT_REG( REG_MACCON   , ETH_SwReset); /* reset MAC machine */
-	PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame));
-	PUT_REG( REG_MACCON   , 0);           /* reset MAC machine */
-
-	/* init frame descriptors */
-	TxFDinit( eth);
-	RxFDinit( eth);
-
-	/* init the CAM with our MAC address */
-	PUT_REG( REG_CAM_BASE,       (eth->m_mac[0] << 24) |
-		(eth->m_mac[1] << 16) |
-		(eth->m_mac[2] <<  8) |
-		(eth->m_mac[3]));
-	PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) |
-		(eth->m_mac[5] << 16));
-
-	/* enable CAM address 1 -- the MAC we just loaded */
-	PUT_REG( REG_CAMEN, 0x1);
-
-	PUT_REG( REG_CAMCON,
-		ETH_BroadAcc |	/* accept broadcast packetes */
-		ETH_CompEn); /* enable compare mode (check against the CAM) */
-
-	/* configure the BDMA Transmitter control */
-	PUT_REG( REG_BDMATXCON,
-		ETH_BTxBRST   |	/* BDMA Tx burst size 16 words  */
-		ETH_BTxMSL110 |	/* BDMA Tx wait to fill 6/8 of the BDMA */
-		ETH_BTxSTSKO  |	/* BDMA Tx interrupt(Stop) on non-owner TX FD */
-		ETH_BTxEn);	/* BDMA Tx Enable  */
-
-	/* configure the MAC Transmitter control */
-	PUT_REG( REG_MACTXCON,
-		ETH_EnComp | /* interrupt when the MAC transmits or discards packet */
-		ETH_TxEn);	/* MAC transmit enable */
-
-	/* configure the BDMA Receiver control */
-	PUT_REG( REG_BDMARXCON,
-		ETH_BRxBRST   |	/* BDMA Rx Burst Size 16 words */
-		ETH_BRxSTSKO  |	/* BDMA Rx interrupt(Stop) on non-owner RX FD */
-		ETH_BRxMAINC  |	/* BDMA Rx Memory Address increment */
-		ETH_BRxDIE    |	/* BDMA Rx Every Received Frame Interrupt Enable */
-		ETH_BRxNLIE   |	/* BDMA Rx NULL List Interrupt Enable */
-		ETH_BRxNOIE   |	/* BDMA Rx Not Owner Interrupt Enable */
-		ETH_BRxLittle |	/* BDMA Rx Little endian */
-		ETH_BRxEn);	/* BDMA Rx Enable */
-
-	/* configure the MAC Receiver control */
-	PUT_REG( REG_MACRXCON,
-		ETH_RxEn);	/* MAC ETH_RxEn */
-
-	return 0;
-
-}
-
-/* Send a packet	*/
-s32 eth_send(volatile void *packet, s32 length)
-{
-
-	u32 i;
-	ETH *eth = &m_eth;
-
-	if ( eth->m_curTX_FD->m_frameDataPtr.bf.owner) {
-		printf("eth_send(): TX Frame.  CPU not owner.\n");
-		return -1;
-	}
-
-	/* copy user data into frame data pointer */
-	memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr),
-	       (void *)packet,
-	       length);
-
-	/* Set TX Frame flags */
-	eth->m_curTX_FD->m_opt.bf.widgetAlign  = 0;
-	eth->m_curTX_FD->m_opt.bf.frameDataDir = 1;
-	eth->m_curTX_FD->m_opt.bf.littleEndian = 1;
-	eth->m_curTX_FD->m_opt.bf.macTxIrqEnbl = 1;
-	eth->m_curTX_FD->m_opt.bf.no_crc       = 0;
-	eth->m_curTX_FD->m_opt.bf.no_padding   = 0;
-
-	/* Set TX Frame length */
-	eth->m_curTX_FD->m_status.bf.len       = length;
-
-	/* Change ownership to BDMA */
-	eth->m_curTX_FD->m_frameDataPtr.bf.owner = 1;
-
-	/* Enable MAC and BDMA Tx control register */
-	SET_REG( REG_BDMATXCON, ETH_BTxEn);
-	SET_REG( REG_MACTXCON,  ETH_TxEn);
-
-	/* poll on TX completion status */
-	while ( !eth->m_curTX_FD->m_status.bf.complete) {
-		/* sleep  */
-		for ( i = 0; i < 0x10000; i ++);
-	}
-
-	/* Change the Tx frame descriptor for next use */
-	eth->m_curTX_FD = eth->m_curTX_FD->m_nextFD;
-
-	return 0;
-}
-
-/* Check for received packets	*/
-s32 eth_rx (void)
-{
-	s32 nLen = 0;
-	ETH *eth = &m_eth;
-
-	/* check if packet ready */
-	if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) {
-		/* process all waiting packets */
-		while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) {
-			nLen = eth->m_curRX_FD->m_status.bf.len;
-			/* call back u-boot -- may call eth_send() */
-			NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen);
-			/* set owner back to CPU */
-			eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1;
-			/* clear status */
-			eth->m_curRX_FD->m_status.ui = 0x0;
-			/* advance to next descriptor */
-			eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD;
-			/* clear received frame bit */
-			PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF);
-		}
-	}
-
-	return nLen;
-}
-
-/* Halt ethernet engine */
-void eth_halt(void)
-{
-	/* disable MAC */
-	PUT_REG( REG_MACCON, ETH_HaltReg);
-}
-
-#endif
diff --git a/drivers/net/s3c4510b_eth.h b/drivers/net/s3c4510b_eth.h
deleted file mode 100644
index cbddba71a4..0000000000
--- a/drivers/net/s3c4510b_eth.h
+++ /dev/null
@@ -1,302 +0,0 @@
-#ifndef __S3C4510B_ETH_H
-#define __S3C4510B_ETH_H
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * MODULE:        $Id:$
- * Description:   Ethernet interface
- * Runtime Env:   ARM7TDMI
- * Change History:
- *     03-02-04    Create (Curt Brune) curt@cucy.com
- *
- */
-
-#define __packed    __attribute__ ((packed))
-
-#define ETH_MAC_ADDR_SIZE           (6)    /*  dst,src addr is 6bytes each */
-#define ETH_MaxTxFrames             (16)   /*  Max number of Tx Frames */
-
-/*  Buffered DMA Receiver Control Register  */
-#define ETH_BRxBRST     0x0000F  /*  BDMA Rx Burst Size * BRxBRST  */
-				 /*  = Burst Data Size 16 */
-#define ETH_BRxSTSKO    0x00020  /*  BDMA Rx Stop/Skip  Frame or Interrupt(=1)  */
-				 /*  case of not OWNER the current Frame  */
-#define ETH_BRxMAINC    0x00040  /*  BDMA Rx Memory Address Inc/Dec  */
-#define ETH_BRxDIE      0x00080  /*  BDMA Rx Every Received Frame Interrupt Enable */
-#define ETH_BRxNLIE     0x00100  /*  BDMA Rx NULL List Interrupt Enable  */
-#define ETH_BRxNOIE     0x00200  /*  BDMA Rx Not Owner Interrupt Enable */
-#define ETH_BRxMSOIE    0x00400  /*  BDMA Rx Maximum Size over Interrupr Enable  */
-#define ETH_BRxLittle   0x00800  /*  BDMA Rx Big/Little Endian  */
-#define ETH_BRxBig      0x00000  /*  BDMA Rx Big/Little Endian */
-#define ETH_BRxWA01     0x01000  /*  BDMA Rx Word Alignment- one invalid byte  */
-#define ETH_BRxWA10     0x02000  /*  BDMA Rx Word Alignment- two invalid byte */
-#define ETH_BRxWA11     0x03000  /*  BDMA Rx Word Alignment- three invalid byte  */
-#define ETH_BRxEn       0x04000  /*  BDMA Rx Enable */
-#define ETH_BRxRS       0x08000  /*  BDMA Rx Reset */
-#define ETH_RxEmpty     0x10000  /*  BDMA Rx Buffer empty interrupt  */
-#define ETH_BRxEarly    0x20000  /*  BDMA Rx Early notify Interrupt */
-
-/*  Buffered DMA Trasmit Control Register(BDMATXCON)  */
-#define ETH_BTxBRST     0x0000F  /*  BDMA Tx Burst Size = 16  */
-#define ETH_BTxSTSKO    0x00020  /*  BDMA Tx Stop/Skip Frame or Interrupt in case */
-				 /*  of not Owner the current frame  */
-#define ETH_BTxCPIE     0x00080  /*  BDMA Tx Complete to send control  */
-				 /*  packet Enable */
-#define ETH_BTxNOIE     0x00200  /*  BDMA Tx Buffer Not Owner */
-#define ETH_BTxEmpty    0x00400  /*  BDMA Tx Buffer Empty Interrupt  */
-
-/*  BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in.  */
-#define ETH_BTxMSL000   0x00000  /*  No wait to fill the BDMA  */
-#define ETH_BTxMSL001   0x00800  /*  wait to fill 1/8 of the BDMA  */
-#define ETH_BTxMSL010   0x01000  /*  wait to fill 2/8 of the BDMA */
-#define ETH_BTxMSL011   0x01800  /*  wait to fill 3/8 of the BDMA */
-#define ETH_BTxMSL100   0x02000  /*  wait to fill 4/8 of the BDMA */
-#define ETH_BTxMSL101   0x02800  /*  wait to fill 5/8 of the BDMA */
-#define ETH_BTxMSL110   0x03000  /*  wait to fill 6/8 of the BDMA */
-#define ETH_BTxMSL111   0x03800  /*  wait to fill 7/8 of the BDMA */
-#define ETH_BTxEn       0x04000  /*  BDMA Tx Enable  */
-#define ETH_BTxRS       0x08000  /*  BDMA Tx Reset  */
-
-/*  BDMA Status Register  */
-#define ETH_S_BRxRDF    0x00001  /*  BDMA Rx Done Every Received Frame  */
-#define ETH_S_BRxNL     0x00002  /*  BDMA Rx NULL List  */
-#define ETH_S_BRxNO     0x00004  /*  BDMA Rx Not Owner  */
-#define ETH_S_BRxMSO    0x00008  /*  BDMA Rx Maximum Size Over  */
-#define ETH_S_BRxEmpty  0x00010  /*  BDMA Rx Buffer Empty  */
-#define ETH_S_BRxSEarly 0x00020  /*  Early Notify  */
-#define ETH_S_BRxFRF    0x00080  /*  One more frame data in BDMA receive buffer  */
-#define ETH_S_BTxCCP    0x10000  /*  BDMA Tx Complete to send Control Packet  */
-#define ETH_S_BTxNL     0x20000  /*  BDMA Tx Null List  */
-#define ETH_S_BTxNO     0x40000  /*  BDMA Tx Not Owner */
-#define ETH_S_BTxEmpty  0x100000 /*  BDMA Tx Buffer Empty  */
-
-/*  MAC Control Register  */
-#define ETH_HaltReg     0x0001   /*  stop transmission and reception  */
-				 /*  after completion of any current packets  */
-#define ETH_HaltImm     0x0002   /*  Stop transmission and reception immediately  */
-#define ETH_SwReset     0x0004   /*  reset all Ethernet controller state machines */
-				 /*  and FIFOs  */
-#define ETH_FullDup     0x0008   /*  allow transmission to begin while reception */
-				 /*  is occurring  */
-#define ETH_MACLoop     0x0010   /*  MAC loopback */
-#define ETH_ConnM00     0x0000   /*  Automatic-default  */
-#define ETH_ConnM01     0x0020   /*  Force 10Mbits endec */
-#define ETH_ConnM10     0x0040   /*  Force MII (rate determined by MII clock  */
-#define ETH_MIIOFF      0x0040   /*  Force MII (rate determined by MII clock  */
-#define ETH_Loop10      0x0080   /*  Loop 10Mbps  */
-#define ETH_MissRoll    0x0400   /*  Missed error counter rolled over  */
-#define ETH_MDCOFF      0x1000   /*  MII Station Management Clock Off */
-#define ETH_EnMissRoll  0x2000   /*  Interrupt when missed error counter rolls  */
-				 /*  over  */
-#define ETH_Link10      0x8000   /*  Link status 10Mbps  */
-
-/*  CAM control register(CAMCON)  */
-#define ETH_StationAcc  0x0001   /*  Accept any packet with a unicast station  */
-				 /*  address  */
-#define ETH_GroupAcc    0x0002   /*  Accept any packet with multicast-group  */
-				 /*  station address   */
-#define ETH_BroadAcc    0x0004   /*  Accept any packet with a broadcast station */
-				 /*  address  */
-#define ETH_NegCAM      0x0008   /*  0: Accept packets CAM recognizes,  */
-				 /*     reject others */
-				 /*  1: reject packets CAM recognizes,  */
-				 /*     accept others  */
-#define ETH_CompEn      0x0010   /*  Compare Enable mode */
-
-/*  Transmit Control Register(MACTXCON) */
-#define ETH_TxEn        0x0001   /*  transmit Enable  */
-#define ETH_TxHalt      0x0002   /*  Transmit Halt Request  */
-#define ETH_NoPad       0x0004   /*  suppress Padding  */
-#define ETH_NoCRC       0x0008   /*  Suppress CRC  */
-#define ETH_FBack       0x0010   /*  Fast Back-off */
-#define ETH_NoDef       0x0020   /*  Disable the defer counter */
-#define ETH_SdPause     0x0040   /*  Send Pause */
-#define ETH_MII10En     0x0080   /*  MII 10Mbps mode enable */
-#define ETH_EnUnder     0x0100   /*  Enable Underrun */
-#define ETH_EnDefer     0x0200   /*  Enable Deferral */
-#define ETH_EnNCarr     0x0400   /*  Enable No Carrier  */
-#define ETH_EnExColl    0x0800   /*  interrupt if 16 collision occur  */
-				 /*  in the same packet  */
-#define ETH_EnLateColl  0x1000   /*  interrupt if collision occurs after  */
-				 /*  512 bit times(64 bytes times)  */
-#define ETH_EnTxPar     0x2000   /*  interrupt if the MAC transmit FIFO  */
-				 /*  has a parity error  */
-#define ETH_EnComp      0x4000   /*  interrupt when the MAC transmits or  */
-				 /*  discards one packet  */
-
-/*  Transmit Status Register(MACTXSTAT) */
-#define ETH_ExColl      0x0010   /*  Excessive collision  */
-#define ETH_TxDeffered  0x0020   /*  set if 16 collisions occur for same packet */
-#define ETH_Paused      0x0040   /*  packet waited because of pause during  */
-				 /*  transmission  */
-#define ETH_IntTx       0x0080   /*  set if transmission of packet causes an  */
-				 /*  interrupt condiftion  */
-#define ETH_Under       0x0100   /*  MAC transmit FIFO becomes empty during  */
-				 /*  transmission  */
-#define ETH_Defer       0x0200   /*  MAC defers for MAC deferral  */
-#define ETH_NCarr       0x0400   /*  No carrier sense detected during the  */
-				 /*  transmission of a packet  */
-#define ETH_SQE         0x0800   /*  Signal Quality Error */
-#define ETH_LateColl    0x1000   /*  a collision occures after 512 bit times  */
-#define ETH_TxPar       0x2000   /*  MAC transmit FIFO has detected a parity error */
-#define ETH_Comp        0x4000   /*  MAC transmit or discards one packet  */
-#define ETH_TxHalted    0x8000   /*  Transmission was halted by clearing  */
-				 /*  TxEn or Halt immedite  */
-
-/*  Receive Control Register (MACRXCON)  */
-#define ETH_RxEn        0x0001
-#define ETH_RxHalt      0x0002
-#define ETH_LongEn      0x0004
-#define ETH_ShortEn     0x0008
-#define ETH_StripCRC    0x0010
-#define ETH_PassCtl     0x0020
-#define ETH_IgnoreCRC   0x0040
-#define ETH_EnAlign     0x0100
-#define ETH_EnCRCErr    0x0200
-#define ETH_EnOver      0x0400
-#define ETH_EnLongErr   0x0800
-#define ETH_EnRxPar     0x2000
-#define ETH_EnGood      0x4000
-
-/*  Receive Status Register(MACRXSTAT) */
-#define ETH_MCtlRecd    0x0020
-#define ETH_MIntRx      0x0040
-#define ETH_MRx10Stat   0x0080
-#define ETH_MAllignErr  0x0100
-#define ETH_MCRCErr     0x0200
-#define ETH_MOverflow   0x0400
-#define ETH_MLongErr    0x0800
-#define ETH_MRxPar      0x2000
-#define ETH_MRxGood     0x4000
-#define ETH_MRxHalted   0x8000
-
-/*  type of ethernet packets */
-#define ETH_TYPE_ARP  (0x0806)
-#define ETH_TYPE_IP   (0x0800)
-
-#define ETH_HDR_SIZE  (14)
-
-/*  bit field for frame data pointer word */
-typedef struct __BF_FrameDataPtr {
-	u32 dataPtr:31;
-	u32   owner: 1;
-} BF_FrameDataPtr;
-
-typedef union _FrameDataPtr {
-	u32             ui;
-	BF_FrameDataPtr bf;
-} FrameDataPtr;
-
-typedef struct __BF_TX_Options {
-	u32    no_padding: 1;
-	u32        no_crc: 1;
-	u32  macTxIrqEnbl: 1;
-	u32  littleEndian: 1;
-	u32  frameDataDir: 1;
-	u32   widgetAlign: 2;
-	u32      reserved:25;
-} BF_TX_Options;
-
-typedef union _TX_Options {
-	u32    ui;
-	BF_TX_Options   bf;
-} TX_Options;
-
-typedef struct __BF_RX_Status {
-	u32           len:16;	/*  frame length */
-	u32     reserved1: 3;
-	u32       overMax: 1;
-	u32     reserved2: 1;
-	u32       ctrlRcv: 1;
-	u32         intRx: 1;
-	u32      rx10stat: 1;
-	u32      alignErr: 1;
-	u32        crcErr: 1;
-	u32      overFlow: 1;
-	u32       longErr: 1;
-	u32     reserved3: 1;
-	u32     parityErr: 1;
-	u32          good: 1;
-	u32        halted: 1;
-} BF_RX_Status;
-
-typedef union _RX_Status {
-	u32             ui;
-	BF_RX_Status    bf;
-} RX_Status;
-
-typedef struct __BF_TX_Status {
-	u32           len:16;	/*  frame length */
-	u32     txCollCnt: 4;
-	u32        exColl: 1;
-	u32       txDefer: 1;
-	u32        paused: 1;
-	u32         intTx: 1;
-	u32      underRun: 1;
-	u32         defer: 1;
-	u32     noCarrier: 1;
-	u32         SQErr: 1;
-	u32      lateColl: 1;
-	u32     parityErr: 1;
-	u32      complete: 1;
-	u32        halted: 1;
-} BF_TX_Status;
-
-typedef union _TX_Status {
-	u32    ui;
-	BF_TX_Status    bf;
-} TX_Status;
-
-/*  TX descriptor structure  */
-typedef struct __TX_FrameDescriptor {
-	volatile FrameDataPtr  m_frameDataPtr;
-	TX_Options                      m_opt;
-	volatile TX_Status           m_status;
-	struct __TX_FrameDescriptor *m_nextFD;
-} TX_FrameDescriptor;
-
-/*  RX descriptor structure  */
-typedef struct __RX_FrameDescriptor {
-	volatile FrameDataPtr  m_frameDataPtr;
-	u32                        m_reserved;
-	volatile RX_Status           m_status;
-	struct __RX_FrameDescriptor *m_nextFD;
-} RX_FrameDescriptor;
-
-/*  MAC Frame Structure */
-typedef struct __MACFrame {
-	u8     m_dstAddr[6] __packed;
-	u8     m_srcAddr[6] __packed;
-	u16  m_lengthOrType __packed;
-	u8  m_payload[1506] __packed;
-} MACFrame;
-
-/* Ethernet Control block */
-typedef struct __ETH {
-	TX_FrameDescriptor   *m_curTX_FD; /*  pointer to current TX frame descriptor */
-	TX_FrameDescriptor  *m_baseTX_FD; /*  pointer to base TX frame descriptor    */
-	RX_FrameDescriptor   *m_curRX_FD; /*  pointer to current RX frame descriptor */
-	RX_FrameDescriptor  *m_baseRX_FD; /*  pointer to base RX frame descriptor    */
-	u8                        *m_mac; /*  pointer to our MAC address             */
-} ETH;
-
-#endif
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
deleted file mode 100644
index ff021cbc85..0000000000
--- a/drivers/net/smc91111.c
+++ /dev/null
@@ -1,1097 +0,0 @@
-/*------------------------------------------------------------------------
- . smc91111.c
- . This is a driver for SMSC's 91C111 single-chip Ethernet device.
- .
- . (C) Copyright 2002
- . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- . Rolf Offermanns <rof@sysgo.de>
- .
- . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- .	 Developed by Simple Network Magic Corporation (SNMC)
- . Copyright (C) 1996 by Erik Stahlman (ES)
- .
- . This program is free software; you can redistribute it and/or modify
- . it under the terms of the GNU General Public License as published by
- . the Free Software Foundation; either version 2 of the License, or
- . (at your option) any later version.
- .
- . This program is distributed in the hope that it will be useful,
- . but WITHOUT ANY WARRANTY; without even the implied warranty of
- . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- . GNU General Public License for more details.
- .
- . You should have received a copy of the GNU General Public License
- . along with this program; if not, write to the Free Software
- . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- .
- . Information contained in this file was obtained from the LAN91C111
- . manual from SMC.  To get a copy, if you really want one, you can find
- . information under www.smsc.com.
- .
- .
- . "Features" of the SMC chip:
- .   Integrated PHY/MAC for 10/100BaseT Operation
- .   Supports internal and external MII
- .   Integrated 8K packet memory
- .   EEPROM interface for configuration
- .
- . Arguments:
- .	io	= for the base address
- .	irq	= for the IRQ
- .
- . author:
- .	Erik Stahlman				( erik@vt.edu )
- .	Daris A Nevil				( dnevil@snmc.com )
- .
- .
- . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
- .
- . Sources:
- .    o	  SMSC LAN91C111 databook (www.smsc.com)
- .    o	  smc9194.c by Erik Stahlman
- .    o	  skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
- .
- . History:
- .	06/19/03  Richard Woodruff Made u-boot environment aware and added mac addr checks.
- .	10/17/01  Marco Hasewinkel Modify for DNP/1110
- .	07/25/01  Woojung Huh	   Modify for ADS Bitsy
- .	04/25/01  Daris A Nevil	   Initial public release through SMSC
- .	03/16/01  Daris A Nevil	   Modified smc9194.c for use with LAN91C111
- ----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include "smc91111.h"
-#include <net.h>
-
-#ifdef CONFIG_DRIVER_SMC91111
-
-/* Use power-down feature of the chip */
-#define POWER_DOWN	0
-
-#define NO_AUTOPROBE
-
-#define SMC_DEBUG 0
-
-#if SMC_DEBUG > 1
-static const char version[] =
-	"smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
-#endif
-
-/*------------------------------------------------------------------------
- .
- . Configuration options, for the experienced user to change.
- .
- -------------------------------------------------------------------------*/
-
-/*
- . Wait time for memory to be free.  This probably shouldn't be
- . tuned that much, as waiting for this means nothing else happens
- . in the system
-*/
-#define MEMORY_WAIT_TIME 16
-
-
-#if (SMC_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if SMC_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef SMC_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-
-/*------------------------------------------------------------------------
- .
- . The internal workings of the driver.	 If you are changing anything
- . here with the SMC stuff, you should have the datasheet and know
- . what you are doing.
- .
- -------------------------------------------------------------------------*/
-#define CARDNAME "LAN91C111"
-
-/* Memory sizing constant */
-#define LAN91C111_MEMORY_MULTIPLIER	(1024*2)
-
-#ifndef CONFIG_SMC91111_BASE
-#define CONFIG_SMC91111_BASE 0x20000300
-#endif
-
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
-#define SMC_DEV_NAME "SMC91111"
-#define SMC_PHY_ADDR 0x0000
-#define SMC_ALLOC_MAX_TRY 5
-#define SMC_TX_TIMEOUT 30
-
-#define SMC_PHY_CLOCK_DELAY 1000
-
-#define ETH_ZLEN 60
-
-#ifdef	CONFIG_SMC_USE_32_BIT
-#define USE_32_BIT  1
-#else
-#undef USE_32_BIT
-#endif
-
-/*
- . Configures the PHY through the MII Management interface
-*/
-#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure(void);
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-/*
- ------------------------------------------------------------
- .
- . Internal routines
- .
- ------------------------------------------------------------
-*/
-
-#ifdef CONFIG_SMC_USE_IOFUNCS
-/*
- * input and output functions
- *
- * Implemented due to inx,outx macros accessing the device improperly
- * and putting the device into an unkown state.
- *
- * For instance, on Sharp LPD7A400 SDK, affects were chip memory
- * could not be free'd (hence the alloc failures), duplicate packets,
- * packets being corrupt (shifted) on the wire, etc.  Switching to the
- * inx,outx functions fixed this problem.
- */
-static inline word SMC_inw(dword offset);
-static inline void SMC_outw(word value, dword offset);
-static inline byte SMC_inb(dword offset);
-static inline void SMC_outb(byte value, dword offset);
-static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
-static inline void SMC_outsw(dword offset, uchar* buf, dword len);
-
-#define barrier() __asm__ __volatile__("": : :"memory")
-
-static inline word SMC_inw(dword offset)
-{
-	word v;
-	v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
-	barrier(); *(volatile u32*)(0xc0000000);
-	return v;
-}
-
-static inline void SMC_outw(word value, dword offset)
-{
-	*((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
-	barrier(); *(volatile u32*)(0xc0000000);
-}
-
-static inline byte SMC_inb(dword offset)
-{
-	word  _w;
-
-	_w = SMC_inw(offset & ~((dword)1));
-	return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
-}
-
-static inline void SMC_outb(byte value, dword offset)
-{
-	word  _w;
-
-	_w = SMC_inw(offset & ~((dword)1));
-	if (offset & 1)
-			*((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
-	else
-			*((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
-}
-
-static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
-{
-	volatile word *p = (volatile word *)buf;
-
-	while (len-- > 0) {
-		*p++ = SMC_inw(offset);
-		barrier();
-		*((volatile u32*)(0xc0000000));
-	}
-}
-
-static inline void SMC_outsw(dword offset, uchar* buf, dword len)
-{
-	volatile word *p = (volatile word *)buf;
-
-	while (len-- > 0) {
-		SMC_outw(*p++, offset);
-		barrier();
-		*(volatile u32*)(0xc0000000);
-	}
-}
-#endif  /* CONFIG_SMC_USE_IOFUNCS */
-
-/***********************************************
- * Show available memory		       *
- ***********************************************/
-void dump_memory_info(void)
-{
-	word mem_info;
-	word old_bank;
-
-	old_bank = SMC_inw(BANK_SELECT)&0xF;
-
-	SMC_SELECT_BANK(0);
-	mem_info = SMC_inw( MIR_REG );
-	PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
-
-	SMC_SELECT_BANK(old_bank);
-}
-/*
- . A rather simple routine to print out a packet for debugging purposes.
-*/
-#if SMC_DEBUG > 2
-static void print_packet( byte *, int );
-#endif
-
-#define tx_done(dev) 1
-
-/* Routines to Read and Write the PHY Registers across the
-   MII Management Interface
-*/
-
-#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register(byte phyreg);
-static void smc_write_phy_register(byte phyreg, word phydata);
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
-static int poll4int (byte mask, int timeout)
-{
-	int tmo = get_timer (0) + timeout * CFG_HZ;
-	int is_timeout = 0;
-	word old_bank = SMC_inw (BSR_REG);
-
-	PRINTK2 ("Polling...\n");
-	SMC_SELECT_BANK (2);
-	while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
-		if (get_timer (0) >= tmo) {
-			is_timeout = 1;
-			break;
-		}
-	}
-
-	/* restore old bank selection */
-	SMC_SELECT_BANK (old_bank);
-
-	if (is_timeout)
-		return 1;
-	else
-		return 0;
-}
-
-/* Only one release command at a time, please */
-static inline void smc_wait_mmu_release_complete (void)
-{
-	int count = 0;
-
-	/* assume bank 2 selected */
-	while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
-		udelay (1);	/* Wait until not busy */
-		if (++count > 200)
-			break;
-	}
-}
-
-/*
- . Function: smc_reset( void )
- . Purpose:
- .	This sets the SMC91111 chip to its normal state, hopefully from whatever
- .	mess that any other DOS driver has put it in.
- .
- . Maybe I should reset more registers to defaults in here?  SOFTRST  should
- . do that for me.
- .
- . Method:
- .	1.  send a SOFT RESET
- .	2.  wait for it to finish
- .	3.  enable autorelease mode
- .	4.  reset the memory management unit
- .	5.  clear all interrupts
- .
-*/
-static void smc_reset (void)
-{
-	PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
-
-	/* This resets the registers mostly to defaults, but doesn't
-	   affect EEPROM.  That seems unnecessary */
-	SMC_SELECT_BANK (0);
-	SMC_outw (RCR_SOFTRST, RCR_REG);
-
-	/* Setup the Configuration Register */
-	/* This is necessary because the CONFIG_REG is not affected */
-	/* by a soft reset */
-
-	SMC_SELECT_BANK (1);
-#if defined(CONFIG_SMC91111_EXT_PHY)
-	SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
-#else
-	SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
-#endif
-
-
-	/* Release from possible power-down state */
-	/* Configuration register is not affected by Soft Reset */
-	SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
-
-	SMC_SELECT_BANK (0);
-
-	/* this should pause enough for the chip to be happy */
-	udelay (10);
-
-	/* Disable transmit and receive functionality */
-	SMC_outw (RCR_CLEAR, RCR_REG);
-	SMC_outw (TCR_CLEAR, TCR_REG);
-
-	/* set the control register */
-	SMC_SELECT_BANK (1);
-	SMC_outw (CTL_DEFAULT, CTL_REG);
-
-	/* Reset the MMU */
-	SMC_SELECT_BANK (2);
-	smc_wait_mmu_release_complete ();
-	SMC_outw (MC_RESET, MMU_CMD_REG);
-	while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
-		udelay (1);	/* Wait until not busy */
-
-	/* Note:  It doesn't seem that waiting for the MMU busy is needed here,
-	   but this is a place where future chipsets _COULD_ break.  Be wary
-	   of issuing another MMU command right after this */
-
-	/* Disable all interrupts */
-	SMC_outb (0, IM_REG);
-}
-
-/*
- * Open and Initialize the board
- *
- * Set up everything, reset the card, etc ..
- *
- */
-static int smc91111_eth_open (struct eth_device *eth, bd_t * bd)
-{
-	PRINTK2 ("%s: smc91111_open\n", SMC_DEV_NAME);
-
-	SMC_SELECT_BANK( 0 );
-	/* see the header file for options in TCR/RCR DEFAULT*/
-	SMC_outw( TCR_DEFAULT, TCR_REG );
-	SMC_outw( RCR_DEFAULT, RCR_REG );
-
-	/* Configure the PHY */
-#ifndef CONFIG_SMC91111_EXT_PHY
-	smc_phy_configure ();
-#endif
-
-	return 0;
-}
-
-/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
-
-#if (SMC_DEBUG > 2 )
-
-/*------------------------------------------------------------
- . Debugging function for viewing MII Management serial bitstream
- .-------------------------------------------------------------*/
-static void smc_dump_mii_stream (byte * bits, int size)
-{
-	int i;
-
-	printf ("BIT#:");
-	for (i = 0; i < size; ++i) {
-		printf ("%d", i % 10);
-	}
-
-	printf ("\nMDOE:");
-	for (i = 0; i < size; ++i) {
-		if (bits[i] & MII_MDOE)
-			printf ("1");
-		else
-			printf ("0");
-	}
-
-	printf ("\nMDO :");
-	for (i = 0; i < size; ++i) {
-		if (bits[i] & MII_MDO)
-			printf ("1");
-		else
-			printf ("0");
-	}
-
-	printf ("\nMDI :");
-	for (i = 0; i < size; ++i) {
-		if (bits[i] & MII_MDI)
-			printf ("1");
-		else
-			printf ("0");
-	}
-
-	printf ("\n");
-}
-#endif
-
-/*------------------------------------------------------------
- . Reads a register from the MII Management serial interface
- .-------------------------------------------------------------*/
-#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register (byte phyreg)
-{
-	int oldBank;
-	int i;
-	byte mask;
-	word mii_reg;
-	byte bits[64];
-	int clk_idx = 0;
-	int input_idx;
-	word phydata;
-	byte phyaddr = SMC_PHY_ADDR;
-
-	/* 32 consecutive ones on MDO to establish sync */
-	for (i = 0; i < 32; ++i)
-		bits[clk_idx++] = MII_MDOE | MII_MDO;
-
-	/* Start code <01> */
-	bits[clk_idx++] = MII_MDOE;
-	bits[clk_idx++] = MII_MDOE | MII_MDO;
-
-	/* Read command <10> */
-	bits[clk_idx++] = MII_MDOE | MII_MDO;
-	bits[clk_idx++] = MII_MDOE;
-
-	/* Output the PHY address, msb first */
-	mask = (byte) 0x10;
-	for (i = 0; i < 5; ++i) {
-		if (phyaddr & mask)
-			bits[clk_idx++] = MII_MDOE | MII_MDO;
-		else
-			bits[clk_idx++] = MII_MDOE;
-
-		/* Shift to next lowest bit */
-		mask >>= 1;
-	}
-
-	/* Output the phy register number, msb first */
-	mask = (byte) 0x10;
-	for (i = 0; i < 5; ++i) {
-		if (phyreg & mask)
-			bits[clk_idx++] = MII_MDOE | MII_MDO;
-		else
-			bits[clk_idx++] = MII_MDOE;
-
-		/* Shift to next lowest bit */
-		mask >>= 1;
-	}
-
-	/* Tristate and turnaround (2 bit times) */
-	bits[clk_idx++] = 0;
-	/*bits[clk_idx++] = 0; */
-
-	/* Input starts at this bit time */
-	input_idx = clk_idx;
-
-	/* Will input 16 bits */
-	for (i = 0; i < 16; ++i)
-		bits[clk_idx++] = 0;
-
-	/* Final clock bit */
-	bits[clk_idx++] = 0;
-
-	/* Save the current bank */
-	oldBank = SMC_inw (BANK_SELECT);
-
-	/* Select bank 3 */
-	SMC_SELECT_BANK (3);
-
-	/* Get the current MII register value */
-	mii_reg = SMC_inw (MII_REG);
-
-	/* Turn off all MII Interface bits */
-	mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
-
-	/* Clock all 64 cycles */
-	for (i = 0; i < sizeof bits; ++i) {
-		/* Clock Low - output data */
-		SMC_outw (mii_reg | bits[i], MII_REG);
-		udelay (SMC_PHY_CLOCK_DELAY);
-
-
-		/* Clock Hi - input data */
-		SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
-		udelay (SMC_PHY_CLOCK_DELAY);
-		bits[i] |= SMC_inw (MII_REG) & MII_MDI;
-	}
-
-	/* Return to idle state */
-	/* Set clock to low, data to low, and output tristated */
-	SMC_outw (mii_reg, MII_REG);
-	udelay (SMC_PHY_CLOCK_DELAY);
-
-	/* Restore original bank select */
-	SMC_SELECT_BANK (oldBank);
-
-	/* Recover input data */
-	phydata = 0;
-	for (i = 0; i < 16; ++i) {
-		phydata <<= 1;
-
-		if (bits[input_idx++] & MII_MDI)
-			phydata |= 0x0001;
-	}
-
-#if (SMC_DEBUG > 2 )
-	printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
-		phyaddr, phyreg, phydata);
-	smc_dump_mii_stream (bits, sizeof bits);
-#endif
-
-	return (phydata);
-}
-
-
-/*------------------------------------------------------------
- . Writes a register to the MII Management serial interface
- .-------------------------------------------------------------*/
-static void smc_write_phy_register (byte phyreg, word phydata)
-{
-	int oldBank;
-	int i;
-	word mask;
-	word mii_reg;
-	byte bits[65];
-	int clk_idx = 0;
-	byte phyaddr = SMC_PHY_ADDR;
-
-	/* 32 consecutive ones on MDO to establish sync */
-	for (i = 0; i < 32; ++i)
-		bits[clk_idx++] = MII_MDOE | MII_MDO;
-
-	/* Start code <01> */
-	bits[clk_idx++] = MII_MDOE;
-	bits[clk_idx++] = MII_MDOE | MII_MDO;
-
-	/* Write command <01> */
-	bits[clk_idx++] = MII_MDOE;
-	bits[clk_idx++] = MII_MDOE | MII_MDO;
-
-	/* Output the PHY address, msb first */
-	mask = (byte) 0x10;
-	for (i = 0; i < 5; ++i) {
-		if (phyaddr & mask)
-			bits[clk_idx++] = MII_MDOE | MII_MDO;
-		else
-			bits[clk_idx++] = MII_MDOE;
-
-		/* Shift to next lowest bit */
-		mask >>= 1;
-	}
-
-	/* Output the phy register number, msb first */
-	mask = (byte) 0x10;
-	for (i = 0; i < 5; ++i) {
-		if (phyreg & mask)
-			bits[clk_idx++] = MII_MDOE | MII_MDO;
-		else
-			bits[clk_idx++] = MII_MDOE;
-
-		/* Shift to next lowest bit */
-		mask >>= 1;
-	}
-
-	/* Tristate and turnaround (2 bit times) */
-	bits[clk_idx++] = 0;
-	bits[clk_idx++] = 0;
-
-	/* Write out 16 bits of data, msb first */
-	mask = 0x8000;
-	for (i = 0; i < 16; ++i) {
-		if (phydata & mask)
-			bits[clk_idx++] = MII_MDOE | MII_MDO;
-		else
-			bits[clk_idx++] = MII_MDOE;
-
-		/* Shift to next lowest bit */
-		mask >>= 1;
-	}
-
-	/* Final clock bit (tristate) */
-	bits[clk_idx++] = 0;
-
-	/* Save the current bank */
-	oldBank = SMC_inw (BANK_SELECT);
-
-	/* Select bank 3 */
-	SMC_SELECT_BANK (3);
-
-	/* Get the current MII register value */
-	mii_reg = SMC_inw (MII_REG);
-
-	/* Turn off all MII Interface bits */
-	mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
-
-	/* Clock all cycles */
-	for (i = 0; i < sizeof bits; ++i) {
-		/* Clock Low - output data */
-		SMC_outw (mii_reg | bits[i], MII_REG);
-		udelay (SMC_PHY_CLOCK_DELAY);
-
-
-		/* Clock Hi - input data */
-		SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
-		udelay (SMC_PHY_CLOCK_DELAY);
-		bits[i] |= SMC_inw (MII_REG) & MII_MDI;
-	}
-
-	/* Return to idle state */
-	/* Set clock to low, data to low, and output tristated */
-	SMC_outw (mii_reg, MII_REG);
-	udelay (SMC_PHY_CLOCK_DELAY);
-
-	/* Restore original bank select */
-	SMC_SELECT_BANK (oldBank);
-
-#if (SMC_DEBUG > 2 )
-	printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
-		phyaddr, phyreg, phydata);
-	smc_dump_mii_stream (bits, sizeof bits);
-#endif
-}
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-/*------------------------------------------------------------
- . Configures the specified PHY using Autonegotiation. Calls
- . smc_phy_fixed() if the user has requested a certain config.
- .-------------------------------------------------------------*/
-#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure ()
-{
-	int timeout;
-	byte phyaddr;
-	word my_phy_caps;	/* My PHY capabilities */
-	word my_ad_caps;	/* My Advertised capabilities */
-	word status = 0;	/*;my status = 0 */
-	int failed = 0;
-
-	PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
-
-
-	/* Get the detected phy address */
-	phyaddr = SMC_PHY_ADDR;
-
-	/* Reset the PHY, setting all other bits to zero */
-	smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
-
-	/* Wait for the reset to complete, or time out */
-	timeout = 3000000;	/* Wait up to 3 seconds */
-	while (timeout--) {
-		if (!(smc_read_phy_register (PHY_CNTL_REG)
-		      & PHY_CNTL_RST)) {
-			/* reset complete */
-			break;
-		}
-
-		udelay(1);	/* wait 500 millisecs */
-	}
-
-	if (timeout < 1) {
-		printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
-		goto smc_phy_configure_exit;
-	}
-
-	/* Read PHY Register 18, Status Output */
-	/* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
-
-	/* Enable PHY Interrupts (for register 18) */
-	/* Interrupts listed here are disabled */
-	smc_write_phy_register (PHY_MASK_REG, 0xffff);
-
-	/* Configure the Receive/Phy Control register */
-	SMC_SELECT_BANK (0);
-	SMC_outw (RPC_DEFAULT, RPC_REG);
-
-	/* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
-	my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
-	my_ad_caps = PHY_AD_CSMA;	/* I am CSMA capable */
-
-	if (my_phy_caps & PHY_STAT_CAP_T4)
-		my_ad_caps |= PHY_AD_T4;
-
-	if (my_phy_caps & PHY_STAT_CAP_TXF)
-		my_ad_caps |= PHY_AD_TX_FDX;
-
-	if (my_phy_caps & PHY_STAT_CAP_TXH)
-		my_ad_caps |= PHY_AD_TX_HDX;
-
-	if (my_phy_caps & PHY_STAT_CAP_TF)
-		my_ad_caps |= PHY_AD_10_FDX;
-
-	if (my_phy_caps & PHY_STAT_CAP_TH)
-		my_ad_caps |= PHY_AD_10_HDX;
-
-	/* Update our Auto-Neg Advertisement Register */
-	smc_write_phy_register (PHY_AD_REG, my_ad_caps);
-
-	/* Read the register back.  Without this, it appears that when */
-	/* auto-negotiation is restarted, sometimes it isn't ready and */
-	/* the link does not come up. */
-	smc_read_phy_register(PHY_AD_REG);
-
-	PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
-	PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
-
-	/* Restart auto-negotiation process in order to advertise my caps */
-	smc_write_phy_register (PHY_CNTL_REG,
-				PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
-
-	/* Wait for the auto-negotiation to complete.  This may take from */
-	/* 2 to 3 seconds. */
-	/* Wait for the reset to complete, or time out */
-	timeout = 10000000;
-	while (timeout--) {
-
-		status = smc_read_phy_register (PHY_STAT_REG);
-		if (status & PHY_STAT_ANEG_ACK) {
-			/* auto-negotiate complete */
-			break;
-		}
-
-		udelay(1);
-
-		/* Restart auto-negotiation if remote fault */
-		if (status & PHY_STAT_REM_FLT) {
-			printf ("%s: PHY remote fault detected\n",
-				SMC_DEV_NAME);
-
-			/* Restart auto-negotiation */
-			printf ("%s: PHY restarting auto-negotiation\n",
-				SMC_DEV_NAME);
-			smc_write_phy_register (PHY_CNTL_REG,
-						PHY_CNTL_ANEG_EN |
-						PHY_CNTL_ANEG_RST |
-						PHY_CNTL_SPEED |
-						PHY_CNTL_DPLX);
-		}
-	}
-
-	if (timeout < 1) {
-		printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
-		failed = 1;
-	}
-
-	/* Fail if we detected an auto-negotiate remote fault */
-	if (status & PHY_STAT_REM_FLT) {
-		printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
-		failed = 1;
-	}
-
-	/* Re-Configure the Receive/Phy Control register */
-	SMC_outw (RPC_DEFAULT, RPC_REG);
-
-smc_phy_configure_exit:	;
-
-}
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
-#if SMC_DEBUG > 2
-static void print_packet( byte * buf, int length )
-{
-	int i;
-	int remainder;
-	int lines;
-
-	printf("Packet of length %d \n", length );
-
-#if SMC_DEBUG > 3
-	lines = length / 16;
-	remainder = length % 16;
-
-	for ( i = 0; i < lines ; i ++ ) {
-		int cur;
-
-		for ( cur = 0; cur < 8; cur ++ ) {
-			byte a, b;
-
-			a = *(buf ++ );
-			b = *(buf ++ );
-			printf("%02x%02x ", a, b );
-		}
-		printf("\n");
-	}
-	for ( i = 0; i < remainder/2 ; i++ ) {
-		byte a, b;
-
-		a = *(buf ++ );
-		b = *(buf ++ );
-		printf("%02x%02x ", a, b );
-	}
-	printf("\n");
-#endif
-}
-#endif
-
-static int smc91111_eth_init(struct eth_device *eth, bd_t *bd) {
-	smc_reset ();
-	return 0;
-}
-
-static void smc91111_eth_halt(struct eth_device *eth) {
-	/* no more interrupts for me */
-	SMC_SELECT_BANK( 2 );
-	SMC_outb( 0, IM_REG );
-
-	/* and tell the card to stay away from that nasty outside world */
-	SMC_SELECT_BANK( 0 );
-	SMC_outb( RCR_CLEAR, RCR_REG );
-	SMC_outb( TCR_CLEAR, TCR_REG );
-}
-
-static int smc91111_eth_rx(struct eth_device *eth) {
-	int	packet_number;
-	word	status;
-	word	packet_length;
-	int	is_error = 0;
-#ifdef USE_32_BIT
-	dword stat_len;
-#endif
-
-	SMC_SELECT_BANK(2);
-
-	packet_number = SMC_inw( RXFIFO_REG );
-
-	if ( packet_number & RXFIFO_REMPTY )
-		return 0;
-
-	PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
-	/*  start reading from the start of the packet */
-	SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
-
-	/* First two words are status and packet_length */
-#ifdef USE_32_BIT
-	stat_len = SMC_inl(SMC91111_DATA_REG);
-	status = stat_len & 0xffff;
-	packet_length = stat_len >> 16;
-#else
-	status		= SMC_inw( SMC91111_DATA_REG );
-	packet_length	= SMC_inw( SMC91111_DATA_REG );
-#endif
-
-	packet_length &= 0x07ff;  /* mask off top bits */
-
-	PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
-
-	if ( !(status & RS_ERRORS ) ){
-		/* Adjust for having already read the first two words */
-		packet_length -= 4; /*4; */
-
-#ifdef USE_32_BIT
-		PRINTK3(" Reading %d dwords (and %d bytes) \n",
-			packet_length >> 2, packet_length & 3 );
-		/* QUESTION:  Like in the TX routine, do I want
-		   to send the DWORDs or the bytes first, or some
-		   mixture.  A mixture might improve already slow PIO
-		   performance	*/
-		SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
-		/* read the left over bytes */
-		if (packet_length & 3) {
-			int i;
-
-			byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
-			dword leftover = SMC_inl(SMC91111_DATA_REG);
-			for (i=0; i<(packet_length & 3); i++)
-				*tail++ = (byte) (leftover >> (8*i)) & 0xff;
-		}
-#else
-		PRINTK3(" Reading %d words and %d byte(s) \n",
-			(packet_length >> 1 ), packet_length & 1 );
-		SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
-
-#endif /* USE_32_BIT */
-		NetReceive(NetRxPackets[0], packet_length);
-
-	} else {
-		/* error ... */
-		/* TODO ? */
-		is_error = 1;
-	}
-
-	/*  error or good, tell the card to get rid of this packet */
-	SMC_outw( MC_RELEASE, MMU_CMD_REG );
-
-	return 0;
-}
-
-static int smc91111_eth_send(struct eth_device *eth, volatile void *packet, int packet_length) {
-	byte packet_no;
-	unsigned long ioaddr;
-	byte *buf;
-	int length;
-	int numPages;
-	int try = 0;
-	int time_out;
-	byte status;
-
-	SMC_SELECT_BANK (2);
-
-	PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
-
-	length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
-
-	/* allocate memory
-	 ** The MMU wants the number of pages to be the number of 256 bytes
-	 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
-	 **
-	 ** The 91C111 ignores the size bits, but the code is left intact
-	 ** for backwards and future compatibility.
-	 **
-	 ** Pkt size for allocating is data length +6 (for additional status
-	 ** words, length and ctl!)
-	 **
-	 ** If odd size then last byte is included in this header.
-	 */
-	numPages = ((length & 0xfffe) + 6);
-	numPages >>= 8;		/* Divide by 256 */
-
-	if (numPages > 7) {
-		printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
-		return 0;
-	}
-
-	/* now, try to allocate the memory */
-	SMC_SELECT_BANK (2);
-	SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
-
-	try++;
-	time_out = MEMORY_WAIT_TIME;
-	do {
-		status = SMC_inb (SMC91111_INT_REG);
-		if (status & IM_ALLOC_INT) {
-			/* acknowledge the interrupt */
-			SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
-			break;
-		}
-	} while (--time_out);
-
-	if (!time_out) {
-		PRINTK2 ("%s: memory allocation, try %d failed ...\n");
-		return -1;
-	}
-
-	/* I can send the packet now.. */
-
-	ioaddr = SMC_BASE_ADDRESS;
-
-	buf = (byte *) packet;
-
-	/* If I get here, I _know_ there is a packet slot waiting for me */
-	packet_no = SMC_inb (AR_REG);
-	if (packet_no & AR_FAILED) {
-		/* or isn't there?  BAD CHIP! */
-		printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
-		return 0;
-	}
-
-	/* we have a packet address, so tell the card to use it */
-	SMC_outb (packet_no, PN_REG);
-
-	/* point to the beginning of the packet */
-	SMC_outw (PTR_AUTOINC, PTR_REG);
-
-	PRINTK3 ("%s: Trying to xmit packet of length %x\n",
-		 SMC_DEV_NAME, length);
-
-	/* send the packet length ( +6 for status, length and ctl byte )
-	   and the status word ( set to zeros ) */
-#ifdef USE_32_BIT
-	SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
-#else
-	SMC_outw (0, SMC91111_DATA_REG);
-	/* send the packet length ( +6 for status words, length, and ctl */
-	SMC_outw ((length + 6), SMC91111_DATA_REG);
-#endif
-
-	/* send the actual data
-	   . I _think_ it's faster to send the longs first, and then
-	   . mop up by sending the last word.  It depends heavily
-	   . on alignment, at least on the 486.	 Maybe it would be
-	   . a good idea to check which is optimal?  But that could take
-	   . almost as much time as is saved?
-	 */
-#ifdef USE_32_BIT
-	SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
-
-	if (length & 0x2)
-		SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
-			  SMC91111_DATA_REG);
-#else
-	SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
-#endif /* USE_32_BIT */
-
-	/* Send the last byte, if there is one.	  */
-	if ((length & 1) == 0) {
-		SMC_outw (0, SMC91111_DATA_REG);
-	} else {
-		SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
-	}
-
-	/* and let the chipset deal with it */
-	SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
-
-	return length;
-}
-
-static int smc91111_get_mac_address (struct eth_device *eth, uchar *mac)
-{
-	int i;
-	int valid_mac = 0;
-
-	SMC_SELECT_BANK (1);
-	for (i=0; i<6; i++) {
-		mac[i] = SMC_inb ((ADDR0_REG + i));
-		valid_mac |= mac[i];
-	}
-
-	printf ("MAC from EEPROM: %02X:%02X:%02X:%02X:%02X:%02X",
-			mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
-	return (valid_mac ? 0 : 1);
-}
-
-static int smc91111_set_mac_address (struct eth_device *eth, uchar *mac)
-{
-	int i;
-
-	SMC_SELECT_BANK (1);
-
-	for (i = 0; i < 6; i++)
-		SMC_outb (mac[i], (ADDR0_REG + i));
-
-	return 0;
-}
-
-struct eth_device smc91111_eth = {
-	.init = smc91111_eth_init,
-	.open = smc91111_eth_open,
-	.send = smc91111_eth_send,
-	.recv = smc91111_eth_rx,
-	.halt = smc91111_eth_halt,
-	.get_mac_address = smc91111_get_mac_address,
-	.set_mac_address = smc91111_set_mac_address,
-};
-
-#endif /* CONFIG_DRIVER_SMC91111 */
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
deleted file mode 100644
index e31a2a5458..0000000000
--- a/drivers/net/smc91111.h
+++ /dev/null
@@ -1,698 +0,0 @@
-/*------------------------------------------------------------------------
- . smc91111.h - macros for the LAN91C111 Ethernet Driver
- .
- . (C) Copyright 2002
- . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- . Rolf Offermanns <rof@sysgo.de>
- . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- .       Developed by Simple Network Magic Corporation (SNMC)
- . Copyright (C) 1996 by Erik Stahlman (ES)
- .
- . This program is free software; you can redistribute it and/or modify
- . it under the terms of the GNU General Public License as published by
- . the Free Software Foundation; either version 2 of the License, or
- . (at your option) any later version.
- .
- . This program is distributed in the hope that it will be useful,
- . but WITHOUT ANY WARRANTY; without even the implied warranty of
- . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- . GNU General Public License for more details.
- .
- . You should have received a copy of the GNU General Public License
- . along with this program; if not, write to the Free Software
- . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- .
- . This file contains register information and access macros for
- . the LAN91C111 single chip ethernet controller.  It is a modified
- . version of the smc9194.h file.
- .
- . Information contained in this file was obtained from the LAN91C111
- . manual from SMC.  To get a copy, if you really want one, you can find
- . information under www.smsc.com.
- .
- . Authors
- . 	Erik Stahlman				( erik@vt.edu )
- .	Daris A Nevil				( dnevil@snmc.com )
- .
- . History
- . 03/16/01		Daris A Nevil	Modified for use with LAN91C111 device
- .
- ---------------------------------------------------------------------------*/
-#ifndef _SMC91111_H_
-#define _SMC91111_H_
-
-#include <asm/types.h>
-#include <config.h>
-
-/*
- * This function may be called by the board specific initialisation code
- * in order to override the default mac address.
- */
-
-void smc_set_mac_addr (const unsigned char *addr);
-
-
-/* I want some simple types */
-
-typedef unsigned char			byte;
-typedef unsigned short			word;
-typedef unsigned long int 		dword;
-
-/*
- . DEBUGGING LEVELS
- .
- . 0 for normal operation
- . 1 for slightly more details
- . >2 for various levels of increasingly useless information
- .    2 for interrupt tracking, status flags
- .    3 for packet info
- .    4 for complete packet dumps
-*/
-/*#define SMC_DEBUG 0 */
-
-/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
-
-#define	SMC_IO_EXTENT	16
-
-#ifdef CONFIG_PXA250
-
-#ifdef CONFIG_XSENGINE
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
-#define SMC_inb(p)	({ \
-	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
-	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
-	if (__p & 2) __v >>= 8; \
-	else __v &= 0xff; \
-	__v; })
-#elif defined(CONFIG_XAENIAX)
-#define SMC_inl(r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inw(z)	({ \
-	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \
-	unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
-	if (__p & 3) __v >>= 16; \
-	else __v &= 0xffff; \
-	__v; })
-#define SMC_inb(p)	({ \
-	unsigned int ___v = SMC_inw((p) & ~1); \
-	if (p & 1) ___v >>= 8; \
-	else ___v &= 0xff; \
-	___v; })
-#else
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inb(p)	({ \
-	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
-	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
-	if (__p & 1) __v >>= 8; \
-	else __v &= 0xff; \
-	__v; })
-#endif
-
-#ifdef CONFIG_XSENGINE
-#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
-#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d)
-#elif defined (CONFIG_XAENIAX)
-#define SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#define SMC_outw(d,p)	({ \
-	dword __dwo = SMC_inl((p) & ~3); \
-	dword __dwn = (word)(d); \
-	__dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
-	__dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
-	SMC_outl(__dwo, (p) & ~3); \
-})
-#else
-#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
-#endif
-
-#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
-				word __w = SMC_inw((r)&~1);  \
-				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
-				__w |= ((r)&1) ? __d<<8 : __d;  \
-				SMC_outw(__w,(r)&~1);  \
-			})
-
-#define SMC_outsl(r,b,l)	({	int __i; \
-					dword *__b2; \
-					__b2 = (dword *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outl( *(__b2 + __i), r); \
-					} \
-				})
-
-#define SMC_outsw(r,b,l)	({	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outw( *(__b2 + __i), r); \
-					} \
-				})
-
-#define SMC_insl(r,b,l) 	({	int __i ;  \
-					dword *__b2;  \
-			    		__b2 = (dword *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inl(r);  \
-					  SMC_inl(0);  \
-					};  \
-				})
-
-#define SMC_insw(r,b,l) 	({	int __i ;  \
-					word *__b2;  \
-			    		__b2 = (word *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inw(r);  \
-					  SMC_inw(0);  \
-					};  \
-				})
-
-#define SMC_insb(r,b,l) 	({	int __i ;  \
-					byte *__b2;  \
-			    		__b2 = (byte *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inb(r);  \
-					  SMC_inb(0);  \
-					};  \
-				})
-
-#else /* if not CONFIG_PXA250 */
-
-#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
-/*
- * We have only 16 Bit PCMCIA access on Socket 0
- */
-
-#ifdef CONFIG_ADNPESC1
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
-#elif CONFIG_BLACKFIN
-#define	SMC_inw(r) 	({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;})
-#else
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
-#endif
-#define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
-
-#ifdef CONFIG_ADNPESC1
-#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
-#elif CONFIG_BLACKFIN
-#define	SMC_outw(d,r)	{(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");}
-#else
-#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
-#endif
-#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
-				word __w = SMC_inw((r)&~1);  \
-				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
-				__w |= ((r)&1) ? __d<<8 : __d;  \
-				SMC_outw(__w,(r)&~1);  \
-			})
-#define SMC_outsw(r,b,l)	({	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outw( *(__b2 + __i), r); \
-					} \
-				})
-
-#define SMC_insw(r,b,l) 	({	int __i ;  \
-					word *__b2;  \
-			    		__b2 = (word *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inw(r);  \
-					  SMC_inw(0);  \
-					};  \
-				})
-
-#endif  /* CONFIG_SMC_USE_IOFUNCS */
-
-#if defined(CONFIG_SMC_USE_32_BIT)
-
-#ifdef CONFIG_XSENGINE
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
-#else
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#endif
-
-#define SMC_insl(r,b,l) 	({	int __i ;  \
-					dword *__b2;  \
-			    		__b2 = (dword *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inl(r);  \
-					  SMC_inl(0);  \
-					};  \
-				})
-
-#ifdef CONFIG_XSENGINE
-#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
-#else
-#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#endif
-#define SMC_outsl(r,b,l)	({	int __i; \
-					dword *__b2; \
-					__b2 = (dword *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outl( *(__b2 + __i), r); \
-					} \
-				})
-
-#endif /* CONFIG_SMC_USE_32_BIT */
-
-#endif
-
-/*---------------------------------------------------------------
- .
- . A description of the SMSC registers is probably in order here,
- . although for details, the SMC datasheet is invaluable.
- .
- . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
- . are accessed by writing a number into the BANK_SELECT register
- . ( I also use a SMC_SELECT_BANK macro for this ).
- .
- . The banks are configured so that for most purposes, bank 2 is all
- . that is needed for simple run time tasks.
- -----------------------------------------------------------------------*/
-
-/*
- . Bank Select Register:
- .
- .		yyyy yyyy 0000 00xx
- .		xx 		= bank number
- .		yyyy yyyy	= 0x33, for identification purposes.
-*/
-#define	BANK_SELECT		14
-
-/* Transmit Control Register */
-/* BANK 0  */
-#define	TCR_REG 	0x0000 	/* transmit control register */
-#define TCR_ENABLE	0x0001	/* When 1 we can transmit */
-#define TCR_LOOP	0x0002	/* Controls output pin LBK */
-#define TCR_FORCOL	0x0004	/* When 1 will force a collision */
-#define TCR_PAD_EN	0x0080	/* When 1 will pad tx frames < 64 bytes w/0 */
-#define TCR_NOCRC	0x0100	/* When 1 will not append CRC to tx frames */
-#define TCR_MON_CSN	0x0400	/* When 1 tx monitors carrier */
-#define TCR_FDUPLX    	0x0800  /* When 1 enables full duplex operation */
-#define TCR_STP_SQET	0x1000	/* When 1 stops tx if Signal Quality Error */
-#define	TCR_EPH_LOOP	0x2000	/* When 1 enables EPH block loopback */
-#define	TCR_SWFDUP	0x8000	/* When 1 enables Switched Full Duplex mode */
-
-#define	TCR_CLEAR	0	/* do NOTHING */
-/* the default settings for the TCR register : */
-/* QUESTION: do I want to enable padding of short packets ? */
-#define	TCR_DEFAULT  	TCR_ENABLE
-
-
-/* EPH Status Register */
-/* BANK 0  */
-#define EPH_STATUS_REG	0x0002
-#define ES_TX_SUC	0x0001	/* Last TX was successful */
-#define ES_SNGL_COL	0x0002	/* Single collision detected for last tx */
-#define ES_MUL_COL	0x0004	/* Multiple collisions detected for last tx */
-#define ES_LTX_MULT	0x0008	/* Last tx was a multicast */
-#define ES_16COL	0x0010	/* 16 Collisions Reached */
-#define ES_SQET		0x0020	/* Signal Quality Error Test */
-#define ES_LTXBRD	0x0040	/* Last tx was a broadcast */
-#define ES_TXDEFR	0x0080	/* Transmit Deferred */
-#define ES_LATCOL	0x0200	/* Late collision detected on last tx */
-#define ES_LOSTCARR	0x0400	/* Lost Carrier Sense */
-#define ES_EXC_DEF	0x0800	/* Excessive Deferral */
-#define ES_CTR_ROL	0x1000	/* Counter Roll Over indication */
-#define ES_LINK_OK	0x4000	/* Driven by inverted value of nLNK pin */
-#define ES_TXUNRN	0x8000	/* Tx Underrun */
-
-
-/* Receive Control Register */
-/* BANK 0  */
-#define	RCR_REG		0x0004
-#define	RCR_RX_ABORT	0x0001	/* Set if a rx frame was aborted */
-#define	RCR_PRMS	0x0002	/* Enable promiscuous mode */
-#define	RCR_ALMUL	0x0004	/* When set accepts all multicast frames */
-#define RCR_RXEN	0x0100	/* IFF this is set, we can receive packets */
-#define	RCR_STRIP_CRC	0x0200	/* When set strips CRC from rx packets */
-#define	RCR_ABORT_ENB	0x0200	/* When set will abort rx on collision */
-#define	RCR_FILT_CAR	0x0400	/* When set filters leading 12 bit s of carrier */
-#define RCR_SOFTRST	0x8000 	/* resets the chip */
-
-/* the normal settings for the RCR register : */
-#define	RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
-#define RCR_CLEAR	0x0	/* set it to a base state */
-
-/* Counter Register */
-/* BANK 0  */
-#define	COUNTER_REG	0x0006
-
-/* Memory Information Register */
-/* BANK 0  */
-#define	MIR_REG		0x0008
-
-/* Receive/Phy Control Register */
-/* BANK 0  */
-#define	RPC_REG		0x000A
-#define	RPC_SPEED	0x2000	/* When 1 PHY is in 100Mbps mode. */
-#define	RPC_DPLX	0x1000	/* When 1 PHY is in Full-Duplex Mode */
-#define	RPC_ANEG	0x0800	/* When 1 PHY is in Auto-Negotiate Mode */
-#define	RPC_LSXA_SHFT	5	/* Bits to shift LS2A,LS1A,LS0A to lsb */
-#define	RPC_LSXB_SHFT	2	/* Bits to get LS2B,LS1B,LS0B to lsb */
-#define RPC_LED_100_10	(0x00)	/* LED = 100Mbps OR's with 10Mbps link detect */
-#define RPC_LED_RES	(0x01)	/* LED = Reserved */
-#define RPC_LED_10	(0x02)	/* LED = 10Mbps link detect */
-#define RPC_LED_FD	(0x03)	/* LED = Full Duplex Mode */
-#define RPC_LED_TX_RX	(0x04)	/* LED = TX or RX packet occurred */
-#define RPC_LED_100	(0x05)	/* LED = 100Mbps link dectect */
-#define RPC_LED_TX	(0x06)	/* LED = TX packet occurred */
-#define RPC_LED_RX	(0x07)	/* LED = RX packet occurred */
-#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
-/* buggy schematic: LEDa -> yellow, LEDb --> green */
-#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
-			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
-			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
-#elif defined(CONFIG_ADNPESC1)
-/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
-#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
-			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
-			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
-#else
-/* SMSC reference design: LEDa --> green, LEDb --> yellow */
-#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
-			| (RPC_LED_100_10 << RPC_LSXA_SHFT)	\
-			| (RPC_LED_TX_RX << RPC_LSXB_SHFT)	)
-#endif
-
-/* Bank 0 0x000C is reserved */
-
-/* Bank Select Register */
-/* All Banks */
-#define BSR_REG	0x000E
-
-
-/* Configuration Reg */
-/* BANK 1 */
-#define CONFIG_REG	0x0000
-#define CONFIG_EXT_PHY	0x0200	/* 1=external MII, 0=internal Phy */
-#define CONFIG_GPCNTRL	0x0400	/* Inverse value drives pin nCNTRL */
-#define CONFIG_NO_WAIT	0x1000	/* When 1 no extra wait states on ISA bus */
-#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
-
-/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
-#define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)
-
-
-/* Base Address Register */
-/* BANK 1 */
-#define	BASE_REG	0x0002
-
-
-/* Individual Address Registers */
-/* BANK 1 */
-#define	ADDR0_REG	0x0004
-#define	ADDR1_REG	0x0006
-#define	ADDR2_REG	0x0008
-
-
-/* General Purpose Register */
-/* BANK 1 */
-#define	GP_REG		0x000A
-
-
-/* Control Register */
-/* BANK 1 */
-#define	CTL_REG		0x000C
-#define CTL_RCV_BAD	0x4000 /* When 1 bad CRC packets are received */
-#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
-#define	CTL_LE_ENABLE	0x0080 /* When 1 enables Link Error interrupt */
-#define	CTL_CR_ENABLE	0x0040 /* When 1 enables Counter Rollover interrupt */
-#define	CTL_TE_ENABLE	0x0020 /* When 1 enables Transmit Error interrupt */
-#define	CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
-#define	CTL_RELOAD	0x0002 /* When set reads EEPROM into registers */
-#define	CTL_STORE	0x0001 /* When set stores registers into EEPROM */
-#define CTL_DEFAULT     (0x1A10) /* Autorelease enabled*/
-
-/* MMU Command Register */
-/* BANK 2 */
-#define MMU_CMD_REG	0x0000
-#define MC_BUSY		1	/* When 1 the last release has not completed */
-#define MC_NOP		(0<<5)	/* No Op */
-#define	MC_ALLOC	(1<<5) 	/* OR with number of 256 byte packets */
-#define	MC_RESET	(2<<5)	/* Reset MMU to initial state */
-#define	MC_REMOVE	(3<<5) 	/* Remove the current rx packet */
-#define MC_RELEASE  	(4<<5) 	/* Remove and release the current rx packet */
-#define MC_FREEPKT  	(5<<5) 	/* Release packet in PNR register */
-#define MC_ENQUEUE	(6<<5)	/* Enqueue the packet for transmit */
-#define MC_RSTTXFIFO	(7<<5)	/* Reset the TX FIFOs */
-
-
-/* Packet Number Register */
-/* BANK 2 */
-#define	PN_REG		0x0002
-
-
-/* Allocation Result Register */
-/* BANK 2 */
-#define	AR_REG		0x0003
-#define AR_FAILED	0x80	/* Alocation Failed */
-
-
-/* RX FIFO Ports Register */
-/* BANK 2 */
-#define RXFIFO_REG	0x0004	/* Must be read as a word */
-#define RXFIFO_REMPTY	0x8000	/* RX FIFO Empty */
-
-
-/* TX FIFO Ports Register */
-/* BANK 2 */
-#define TXFIFO_REG	RXFIFO_REG	/* Must be read as a word */
-#define TXFIFO_TEMPTY	0x80	/* TX FIFO Empty */
-
-
-/* Pointer Register */
-/* BANK 2 */
-#define PTR_REG		0x0006
-#define	PTR_RCV		0x8000 /* 1=Receive area, 0=Transmit area */
-#define	PTR_AUTOINC 	0x4000 /* Auto increment the pointer on each access */
-#define PTR_READ	0x2000 /* When 1 the operation is a read */
-#define PTR_NOTEMPTY	0x0800 /* When 1 _do not_ write fifo DATA REG */
-
-
-/* Data Register */
-/* BANK 2 */
-#define	SMC91111_DATA_REG	0x0008
-
-
-/* Interrupt Status/Acknowledge Register */
-/* BANK 2 */
-#define	SMC91111_INT_REG	0x000C
-
-
-/* Interrupt Mask Register */
-/* BANK 2 */
-#define IM_REG		0x000D
-#define	IM_MDINT	0x80 /* PHY MI Register 18 Interrupt */
-#define	IM_ERCV_INT	0x40 /* Early Receive Interrupt */
-#define	IM_EPH_INT	0x20 /* Set by Etheret Protocol Handler section */
-#define	IM_RX_OVRN_INT	0x10 /* Set by Receiver Overruns */
-#define	IM_ALLOC_INT	0x08 /* Set when allocation request is completed */
-#define	IM_TX_EMPTY_INT	0x04 /* Set if the TX FIFO goes empty */
-#define	IM_TX_INT	0x02 /* Transmit Interrrupt */
-#define IM_RCV_INT	0x01 /* Receive Interrupt */
-
-
-/* Multicast Table Registers */
-/* BANK 3 */
-#define	MCAST_REG1	0x0000
-#define	MCAST_REG2	0x0002
-#define	MCAST_REG3	0x0004
-#define	MCAST_REG4	0x0006
-
-
-/* Management Interface Register (MII) */
-/* BANK 3 */
-#define	MII_REG		0x0008
-#define MII_MSK_CRS100	0x4000 /* Disables CRS100 detection during tx half dup */
-#define MII_MDOE	0x0008 /* MII Output Enable */
-#define MII_MCLK	0x0004 /* MII Clock, pin MDCLK */
-#define MII_MDI		0x0002 /* MII Input, pin MDI */
-#define MII_MDO		0x0001 /* MII Output, pin MDO */
-
-
-/* Revision Register */
-/* BANK 3 */
-#define	REV_REG		0x000A /* ( hi: chip id   low: rev # ) */
-
-
-/* Early RCV Register */
-/* BANK 3 */
-/* this is NOT on SMC9192 */
-#define	ERCV_REG	0x000C
-#define ERCV_RCV_DISCRD	0x0080 /* When 1 discards a packet being received */
-#define ERCV_THRESHOLD	0x001F /* ERCV Threshold Mask */
-
-/* External Register */
-/* BANK 7 */
-#define	EXT_REG		0x0000
-
-
-#define CHIP_9192	3
-#define CHIP_9194	4
-#define CHIP_9195	5
-#define CHIP_9196	6
-#define CHIP_91100	7
-#define CHIP_91100FD	8
-#define CHIP_91111FD	9
-
-
-/*
- . Transmit status bits
-*/
-#define TS_SUCCESS 0x0001
-#define TS_LOSTCAR 0x0400
-#define TS_LATCOL  0x0200
-#define TS_16COL   0x0010
-
-/*
- . Receive status bits
-*/
-#define RS_ALGNERR	0x8000
-#define RS_BRODCAST	0x4000
-#define RS_BADCRC	0x2000
-#define RS_ODDFRAME	0x1000	/* bug: the LAN91C111 never sets this on receive */
-#define RS_TOOLONG	0x0800
-#define RS_TOOSHORT	0x0400
-#define RS_MULTICAST	0x0001
-#define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
-
-
-/* PHY Types */
-enum {
-	PHY_LAN83C183 = 1,	/* LAN91C111 Internal PHY */
-	PHY_LAN83C180
-};
-
-
-/* PHY Register Addresses (LAN91C111 Internal PHY) */
-
-/* PHY Control Register */
-#define PHY_CNTL_REG		0x00
-#define PHY_CNTL_RST		0x8000	/* 1=PHY Reset */
-#define PHY_CNTL_LPBK		0x4000	/* 1=PHY Loopback */
-#define PHY_CNTL_SPEED		0x2000	/* 1=100Mbps, 0=10Mpbs */
-#define PHY_CNTL_ANEG_EN	0x1000 /* 1=Enable Auto negotiation */
-#define PHY_CNTL_PDN		0x0800	/* 1=PHY Power Down mode */
-#define PHY_CNTL_MII_DIS	0x0400	/* 1=MII 4 bit interface disabled */
-#define PHY_CNTL_ANEG_RST	0x0200 /* 1=Reset Auto negotiate */
-#define PHY_CNTL_DPLX		0x0100	/* 1=Full Duplex, 0=Half Duplex */
-#define PHY_CNTL_COLTST		0x0080	/* 1= MII Colision Test */
-
-/* PHY Status Register */
-#define PHY_STAT_REG		0x01
-#define PHY_STAT_CAP_T4		0x8000	/* 1=100Base-T4 capable */
-#define PHY_STAT_CAP_TXF	0x4000	/* 1=100Base-X full duplex capable */
-#define PHY_STAT_CAP_TXH	0x2000	/* 1=100Base-X half duplex capable */
-#define PHY_STAT_CAP_TF		0x1000	/* 1=10Mbps full duplex capable */
-#define PHY_STAT_CAP_TH		0x0800	/* 1=10Mbps half duplex capable */
-#define PHY_STAT_CAP_SUPR	0x0040	/* 1=recv mgmt frames with not preamble */
-#define PHY_STAT_ANEG_ACK	0x0020	/* 1=ANEG has completed */
-#define PHY_STAT_REM_FLT	0x0010	/* 1=Remote Fault detected */
-#define PHY_STAT_CAP_ANEG	0x0008	/* 1=Auto negotiate capable */
-#define PHY_STAT_LINK		0x0004	/* 1=valid link */
-#define PHY_STAT_JAB		0x0002	/* 1=10Mbps jabber condition */
-#define PHY_STAT_EXREG		0x0001	/* 1=extended registers implemented */
-
-/* PHY Identifier Registers */
-#define PHY_ID1_REG		0x02	/* PHY Identifier 1 */
-#define PHY_ID2_REG		0x03	/* PHY Identifier 2 */
-
-/* PHY Auto-Negotiation Advertisement Register */
-#define PHY_AD_REG		0x04
-#define PHY_AD_NP		0x8000	/* 1=PHY requests exchange of Next Page */
-#define PHY_AD_ACK		0x4000	/* 1=got link code word from remote */
-#define PHY_AD_RF		0x2000	/* 1=advertise remote fault */
-#define PHY_AD_T4		0x0200	/* 1=PHY is capable of 100Base-T4 */
-#define PHY_AD_TX_FDX		0x0100	/* 1=PHY is capable of 100Base-TX FDPLX */
-#define PHY_AD_TX_HDX		0x0080	/* 1=PHY is capable of 100Base-TX HDPLX */
-#define PHY_AD_10_FDX		0x0040	/* 1=PHY is capable of 10Base-T FDPLX */
-#define PHY_AD_10_HDX		0x0020	/* 1=PHY is capable of 10Base-T HDPLX */
-#define PHY_AD_CSMA		0x0001	/* 1=PHY is capable of 802.3 CMSA */
-
-/* PHY Auto-negotiation Remote End Capability Register */
-#define PHY_RMT_REG		0x05
-/* Uses same bit definitions as PHY_AD_REG */
-
-/* PHY Configuration Register 1 */
-#define PHY_CFG1_REG		0x10
-#define PHY_CFG1_LNKDIS		0x8000	/* 1=Rx Link Detect Function disabled */
-#define PHY_CFG1_XMTDIS		0x4000	/* 1=TP Transmitter Disabled */
-#define PHY_CFG1_XMTPDN		0x2000	/* 1=TP Transmitter Powered Down */
-#define PHY_CFG1_BYPSCR		0x0400	/* 1=Bypass scrambler/descrambler */
-#define PHY_CFG1_UNSCDS		0x0200	/* 1=Unscramble Idle Reception Disable */
-#define PHY_CFG1_EQLZR		0x0100	/* 1=Rx Equalizer Disabled */
-#define PHY_CFG1_CABLE		0x0080	/* 1=STP(150ohm), 0=UTP(100ohm) */
-#define PHY_CFG1_RLVL0		0x0040	/* 1=Rx Squelch level reduced by 4.5db */
-#define PHY_CFG1_TLVL_SHIFT	2	/* Transmit Output Level Adjust */
-#define PHY_CFG1_TLVL_MASK	0x003C
-#define PHY_CFG1_TRF_MASK	0x0003	/* Transmitter Rise/Fall time */
-
-
-/* PHY Configuration Register 2 */
-#define PHY_CFG2_REG		0x11
-#define PHY_CFG2_APOLDIS	0x0020	/* 1=Auto Polarity Correction disabled */
-#define PHY_CFG2_JABDIS		0x0010	/* 1=Jabber disabled */
-#define PHY_CFG2_MREG		0x0008	/* 1=Multiple register access (MII mgt) */
-#define PHY_CFG2_INTMDIO	0x0004	/* 1=Interrupt signaled with MDIO pulseo */
-
-/* PHY Status Output (and Interrupt status) Register */
-#define PHY_INT_REG		0x12	/* Status Output (Interrupt Status) */
-#define PHY_INT_INT		0x8000	/* 1=bits have changed since last read */
-#define	PHY_INT_LNKFAIL		0x4000	/* 1=Link Not detected */
-#define PHY_INT_LOSSSYNC	0x2000	/* 1=Descrambler has lost sync */
-#define PHY_INT_CWRD		0x1000	/* 1=Invalid 4B5B code detected on rx */
-#define PHY_INT_SSD		0x0800	/* 1=No Start Of Stream detected on rx */
-#define PHY_INT_ESD		0x0400	/* 1=No End Of Stream detected on rx */
-#define PHY_INT_RPOL		0x0200	/* 1=Reverse Polarity detected */
-#define PHY_INT_JAB		0x0100	/* 1=Jabber detected */
-#define PHY_INT_SPDDET		0x0080	/* 1=100Base-TX mode, 0=10Base-T mode */
-#define PHY_INT_DPLXDET		0x0040	/* 1=Device in Full Duplex */
-
-/* PHY Interrupt/Status Mask Register */
-#define PHY_MASK_REG		0x13	/* Interrupt Mask */
-/* Uses the same bit definitions as PHY_INT_REG */
-
-
-/*-------------------------------------------------------------------------
- .  I define some macros to make it easier to do somewhat common
- . or slightly complicated, repeated tasks.
- --------------------------------------------------------------------------*/
-
-/* select a register bank, 0 to 3  */
-
-#define SMC_SELECT_BANK(x)  { SMC_outw( x, BANK_SELECT ); }
-
-/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) {\
-		unsigned char mask;\
-		SMC_SELECT_BANK(2);\
-		mask = SMC_inb( IM_REG );\
-		mask |= (x);\
-		SMC_outb( mask, IM_REG ); \
-}
-
-/* this disables an interrupt from the interrupt mask register */
-
-#define SMC_DISABLE_INT(x) {\
-		unsigned char mask;\
-		SMC_SELECT_BANK(2);\
-		mask = SMC_inb( IM_REG );\
-		mask &= ~(x);\
-		SMC_outb( mask, IM_REG ); \
-}
-
-/*----------------------------------------------------------------------
- . Define the interrupts that I want to receive from the card
- .
- . I want:
- .  IM_EPH_INT, for nasty errors
- .  IM_RCV_INT, for happy received packets
- .  IM_RX_OVRN_INT, because I have to kick the receiver
- .  IM_MDINT, for PHY Register 18 Status Changes
- --------------------------------------------------------------------------*/
-#define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
-	IM_MDINT)
-
-#endif  /* _SMC_91111_H_ */
diff --git a/drivers/serial/asc_serial.c b/drivers/serial/asc_serial.c
deleted file mode 100644
index d95ec3fd2f..0000000000
--- a/drivers/serial/asc_serial.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * (INCA) ASC UART support
- */
-
-#include <config.h>
-
-#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
-
-#ifdef CONFIG_PURPLE
-#define	serial_init	asc_serial_init
-#define	serial_putc	asc_serial_putc
-#define	serial_puts	asc_serial_puts
-#define	serial_getc	asc_serial_getc
-#define	serial_tstc	asc_serial_tstc
-#define	serial_setbrg	asc_serial_setbrg
-#endif
-
-#include <common.h>
-#include <asm/inca-ip.h>
-#include "asc_serial.h"
-
-#ifdef CONFIG_PURPLE
-
-#undef ASC_FIFO_PRESENT
-#define TOUT_LOOP	100000
-
-/* Set base address for second FPI interrupt control register bank */
-#define SFPI_INTCON_BASEADDR	0xBF0F0000
-
-/* Register offset from base address */
-#define FBS_ISR		0x00000000	/* Interrupt status register */
-#define FBS_IMR		0x00000008	/* Interrupt mask register */
-#define FBS_IDIS	0x00000010	/* Interrupt disable register */
-
-/* Interrupt status register bits */
-#define FBS_ISR_AT	0x00000040	/* ASC transmit interrupt */
-#define FBS_ISR_AR 	0x00000020	/* ASC receive interrupt */
-#define FBS_ISR_AE	0x00000010	/* ASC error interrupt */
-#define FBS_ISR_AB	0x00000008	/* ASC transmit buffer interrupt */
-#define FBS_ISR_AS      0x00000004 	/* ASC start of autobaud detection interrupt */
-#define FBS_ISR_AF	0x00000002	/* ASC end of autobaud detection interrupt */
-
-#else
-
-#define ASC_FIFO_PRESENT
-
-#endif
-
-
-#define SET_BIT(reg, mask)                  reg |= (mask)
-#define CLEAR_BIT(reg, mask)                reg &= (~mask)
-#define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
-
-extern uint incaip_get_fpiclk(void);
-
-static int serial_setopt (void);
-
-/* pointer to ASC register base address */
-static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
-
-/******************************************************************************
-*
-* serial_init - initialize a INCAASC channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-#ifdef CONFIG_INCA_IP
-    /* we have to set PMU.EN13 bit to enable an ASC device*/
-    INCAASC_PMU_ENABLE(13);
-#endif
-
-    /* and we have to set CLC register*/
-    CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
-    SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
-    /* initialy we are in async mode */
-    pAsc->asc_con = ASCCON_M_8ASYNC;
-
-    /* select input port */
-    pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
-
-#ifdef ASC_FIFO_PRESENT
-    /* TXFIFO's filling level */
-    SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
-		    ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
-    /* enable TXFIFO */
-    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
-
-    /* RXFIFO's filling level */
-    SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
-		    ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
-    /* enable RXFIFO */
-    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
-#endif
-
-    /* enable error signals */
-    SET_BIT(pAsc->asc_con, ASCCON_FEN);
-    SET_BIT(pAsc->asc_con, ASCCON_OEN);
-
-#ifdef CONFIG_INCA_IP
-    /* acknowledge ASC interrupts */
-    ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
-
-    /* disable ASC interrupts */
-    ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
-#endif
-
-#ifdef ASC_FIFO_PRESENT
-    /* set FIFOs into the transparent mode */
-    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
-    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
-#endif
-
-    /* set baud rate */
-    serial_setbrg();
-
-    /* set the options */
-    serial_setopt();
-
-    return 0;
-}
-
-void serial_setbrg (void)
-{
-    ulong      uiReloadValue, fdv;
-    ulong      f_ASC;
-
-#ifdef CONFIG_INCA_IP
-    f_ASC = incaip_get_fpiclk();
-#else
-    f_ASC = ASC_CLOCK_RATE;
-#endif
-
-#ifndef INCAASC_USE_FDV
-    fdv = 2;
-    uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
-    fdv = INCAASC_FDV_HIGH_BAUDRATE;
-    uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
-    if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
-    {
-#ifndef INCAASC_USE_FDV
-	fdv = 3;
-	uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
-	fdv = INCAASC_FDV_LOW_BAUDRATE;
-	uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
-	if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
-	{
-	    return;    /* can't impossibly generate that baud rate */
-	}
-    }
-
-    /* Disable Baud Rate Generator; BG should only be written when R=0 */
-    CLEAR_BIT(pAsc->asc_con, ASCCON_R);
-
-#ifndef INCAASC_USE_FDV
-    /*
-     * Disable Fractional Divider (FDE)
-     * Divide clock by reload-value + constant (BRS)
-     */
-    /* FDE = 0 */
-    CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
-
-    if ( fdv == 2 )
-	CLEAR_BIT(pAsc->asc_con, ASCCON_BRS);   /* BRS = 0 */
-    else
-	SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
-
-#else /* INCAASC_USE_FDV */
-
-    /* Enable Fractional Divider */
-    SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
-
-    /* Set fractional divider value */
-    pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
-
-#endif /* INCAASC_USE_FDV */
-
-    /* Set reload value in BG */
-    pAsc->asc_bg = uiReloadValue;
-
-    /* Enable Baud Rate Generator */
-    SET_BIT(pAsc->asc_con, ASCCON_R);           /* R = 1 */
-}
-
-/*******************************************************************************
-*
-* serial_setopt - set the serial options
-*
-* Set the channel operating mode to that specified. Following options
-* are supported: CREAD, CSIZE, PARENB, and PARODD.
-*
-* Note, this routine disables the transmitter.  The calling routine
-* may have to re-enable it.
-*
-* RETURNS:
-* Returns 0 to indicate success, otherwise -1 is returned
-*/
-
-static int serial_setopt (void)
-{
-    ulong  con;
-
-    switch ( ASC_OPTIONS & ASCOPT_CSIZE )
-    {
-    /* 7-bit-data */
-    case ASCOPT_CS7:
-	con = ASCCON_M_7ASYNCPAR;   /* 7-bit-data and parity bit */
-	break;
-
-    /* 8-bit-data */
-    case ASCOPT_CS8:
-	if ( ASC_OPTIONS & ASCOPT_PARENB )
-	    con = ASCCON_M_8ASYNCPAR;   /* 8-bit-data and parity bit */
-	else
-	    con = ASCCON_M_8ASYNC;      /* 8-bit-data no parity */
-	break;
-
-    /*
-     *  only 7 and 8-bit frames are supported
-     *  if we don't use IOCTL extensions
-     */
-    default:
-	return -1;
-    }
-
-    if ( ASC_OPTIONS & ASCOPT_STOPB )
-	SET_BIT(con, ASCCON_STP);       /* 2 stop bits */
-    else
-	CLEAR_BIT(con, ASCCON_STP);     /* 1 stop bit */
-
-    if ( ASC_OPTIONS & ASCOPT_PARENB )
-	SET_BIT(con, ASCCON_PEN);           /* enable parity checking */
-    else
-	CLEAR_BIT(con, ASCCON_PEN);         /* disable parity checking */
-
-    if ( ASC_OPTIONS & ASCOPT_PARODD )
-	SET_BIT(con, ASCCON_ODD);       /* odd parity */
-    else
-	CLEAR_BIT(con, ASCCON_ODD);     /* even parity */
-
-    if ( ASC_OPTIONS & ASCOPT_CREAD )
-	SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
-
-    pAsc->asc_con |= con;
-
-    return 0;
-}
-
-void serial_putc (const char c)
-{
-#ifdef ASC_FIFO_PRESENT
-    uint txFl = 0;
-#else
-    uint timeout = 0;
-#endif
-
-    if (c == '\n') serial_putc ('\r');
-
-#ifdef ASC_FIFO_PRESENT
-    /* check do we have a free space in the TX FIFO */
-    /* get current filling level */
-    do
-    {
-	txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
-    }
-    while ( txFl == INCAASC_TXFIFO_FULL );
-#else
-
-    while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
-			   FBS_ISR_AB))
-    {
-	    if (timeout++ > TOUT_LOOP)
-	    {
-		    break;
-	    }
-    }
-#endif
-
-    pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
-
-#ifndef ASC_FIFO_PRESENT
-    *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
-								 FBS_ISR_AT;
-#endif
-
-    /* check for errors */
-    if ( pAsc->asc_con & ASCCON_OE )
-    {
-	SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-	return;
-    }
-}
-
-void serial_puts (const char *s)
-{
-    while (*s)
-    {
-	serial_putc (*s++);
-    }
-}
-
-int serial_getc (void)
-{
-    ulong symbol_mask;
-    char c;
-
-    while (!serial_tstc());
-
-    symbol_mask =
-	((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-
-    c = (char)(pAsc->asc_rbuf & symbol_mask);
-
-#ifndef ASC_FIFO_PRESENT
-    *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
-#endif
-
-    return c;
-}
-
-int serial_tstc (void)
-{
-    int res = 1;
-
-#ifdef ASC_FIFO_PRESENT
-    if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
-    {
-	res = 0;
-    }
-#else
-    if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
-								FBS_ISR_AR))
-
-    {
-	res = 0;
-    }
-#endif
-    else if ( pAsc->asc_con & ASCCON_FE )
-    {
-	SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
-	res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_PE )
-    {
-	SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
-	res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_OE )
-    {
-	SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-	res = 0;
-    }
-
-    return res;
-}
-#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */
diff --git a/drivers/serial/asc_serial.h b/drivers/serial/asc_serial.h
deleted file mode 100644
index 7ffdcfaf8b..0000000000
--- a/drivers/serial/asc_serial.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* incaAscSio.h - (INCA) ASC UART tty driver header */
-
-#ifndef __INCincaAscSioh
-#define __INCincaAscSioh
-
-#include <asm/inca-ip.h>
-
-/* channel operating modes */
-#define	ASCOPT_CSIZE	0x00000003
-#define	ASCOPT_CS7	0x00000001
-#define	ASCOPT_CS8	0x00000002
-#define	ASCOPT_PARENB	0x00000004
-#define	ASCOPT_STOPB	0x00000008
-#define	ASCOPT_PARODD	0x00000010
-#define	ASCOPT_CREAD	0x00000020
-
-#define ASC_OPTIONS		(ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY	0
-
-/* use fractional divider for baudrate settings */
-#define INCAASC_USE_FDV
-
-#ifdef INCAASC_USE_FDV
-   #define INCAASC_FDV_LOW_BAUDRATE        71
-   #define INCAASC_FDV_HIGH_BAUDRATE       453
-#endif /*INCAASC_USE_FDV*/
-
-
-#define INCAASC_TXFIFO_FL       1
-#define INCAASC_RXFIFO_FL       1
-#define INCAASC_TXFIFO_FULL     16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define INCAASC_IRQ_LINE_ALL        0x000F0000  /* all IRQs */
-
-#define INCAASC_IRQ_LINE_TIR            0x00010000      /* TIR - Tx */
-#define INCAASC_IRQ_LINE_RIR            0x00020000      /* RIR - Rx */
-#define INCAASC_IRQ_LINE_EIR            0x00040000      /* EIR - Err */
-#define INCAASC_IRQ_LINE_TBIR           0x00080000      /* TBIR - Tx Buf*/
-
-/* interrupt controller access macros */
-#define ASC_INTERRUPTS_ENABLE(X)  \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
-#define ASC_INTERRUPTS_DISABLE(X) \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
-#define ASC_INTERRUPTS_CLEAR(X)   \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR        0x00000001
-#define ASCCLC_DISS        0x00000002
-#define ASCCLC_RMCMASK     0x0000FF00
-#define ASCCLC_RMCOFFSET   8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK 0x0007
-    #define ASCCON_M_8SYNC          0x0
-    #define ASCCON_M_8ASYNC         0x1
-    #define ASCCON_M_8IRDAASYNC     0x2
-    #define ASCCON_M_7ASYNCPAR      0x3
-    #define ASCCON_M_9ASYNC         0x4
-    #define ASCCON_M_8WAKEUPASYNC   0x5
-    #define ASCCON_M_8ASYNCPAR      0x7
-#define ASCCON_STP      0x0008
-#define ASCCON_REN      0x0010
-#define ASCCON_PEN      0x0020
-#define ASCCON_FEN      0x0040
-#define ASCCON_OEN      0x0080
-#define ASCCON_PE       0x0100
-#define ASCCON_FE       0x0200
-#define ASCCON_OE       0x0400
-#define ASCCON_FDE      0x0800
-#define ASCCON_ODD      0x1000
-#define ASCCON_BRS      0x2000
-#define ASCCON_LB       0x4000
-#define ASCCON_R        0x8000
-
-/* WHBCON register's bits and bitfields */
-#define ASCWHBCON_CLRREN    0x0010
-#define ASCWHBCON_SETREN    0x0020
-#define ASCWHBCON_CLRPE     0x0100
-#define ASCWHBCON_CLRFE     0x0200
-#define ASCWHBCON_CLROE     0x0400
-#define ASCWHBCON_SETPE     0x0800
-#define ASCWHBCON_SETFE     0x1000
-#define ASCWHBCON_SETOE     0x2000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN       0x0001
-#define ASCABCON_AUREN      0x0002
-#define ASCABCON_ABSTEN     0x0004
-#define ASCABCON_ABDETEN    0x0008
-#define ASCABCON_FCDETEN    0x0010
-#define ASCABCON_EMMASK     0x0300
-    #define ASCABCON_EMOFF          8
-	#define ASCABCON_EM_DISAB       0x0
-	#define ASCABCON_EM_DURAB       0x1
-	#define ASCABCON_EM_ALWAYS      0x2
-#define ASCABCON_TXINV      0x0400
-#define ASCABCON_RXINV      0x0800
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK     0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_SETABEN     0x0001
-#define ASCWHBABCON_CLRABEN     0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET    0x0001
-#define ASCABSTAT_FCCDET    0x0002
-#define ASCABSTAT_SCSDET    0x0004
-#define ASCABSTAT_SCCDET    0x0008
-#define ASCABSTAT_DETWAIT   0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET  0x0001
-#define ASCWHBABSTAT_SETFCSDET  0x0002
-#define ASCWHBABSTAT_CLRFCCDET  0x0004
-#define ASCWHBABSTAT_SETFCCDET  0x0008
-#define ASCWHBABSTAT_CLRSCSDET  0x0010
-#define ASCWHBABSTAT_SETSCSDET  0x0020
-#define ASCWHBABSTAT_SETSCCDET  0x0040
-#define ASCWHBABSTAT_CLRSCCDET  0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFEN         0x0001
-#define ASCTXFCON_TXFFLU        0x0002
-#define ASCTXFCON_TXTMEN        0x0004
-#define ASCTXFCON_TXFITLMASK    0x3F00
-#define ASCTXFCON_TXFITLOFF     8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFEN         0x0001
-#define ASCRXFCON_RXFFLU        0x0002
-#define ASCRXFCON_RXTMEN        0x0004
-#define ASCRXFCON_RXFITLMASK    0x3F00
-#define ASCRXFCON_RXFITLOFF     8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK      0x003F
-#define ASCFSTAT_TXFFLMASK      0x3F00
-#define ASCFSTAT_TXFFLOFF       8
-
-#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
-
-typedef  struct         /* incaAsc_t */
-{
-    volatile unsigned long  asc_clc;                            /*0x0000*/
-    volatile unsigned long  asc_pisel;                          /*0x0004*/
-    volatile unsigned long  asc_rsvd1[2];   /* for mapping */   /*0x0008*/
-    volatile unsigned long  asc_con;                            /*0x0010*/
-    volatile unsigned long  asc_bg;                             /*0x0014*/
-    volatile unsigned long  asc_fdv;                            /*0x0018*/
-    volatile unsigned long  asc_pmw;        /* not used */      /*0x001C*/
-    volatile unsigned long  asc_tbuf;                           /*0x0020*/
-    volatile unsigned long  asc_rbuf;                           /*0x0024*/
-    volatile unsigned long  asc_rsvd2[2];   /* for mapping */   /*0x0028*/
-    volatile unsigned long  asc_abcon;                          /*0x0030*/
-    volatile unsigned long  asc_abstat;     /* not used */      /*0x0034*/
-    volatile unsigned long  asc_rsvd3[2];   /* for mapping */   /*0x0038*/
-    volatile unsigned long  asc_rxfcon;                         /*0x0040*/
-    volatile unsigned long  asc_txfcon;                         /*0x0044*/
-    volatile unsigned long  asc_fstat;                          /*0x0048*/
-    volatile unsigned long  asc_rsvd4;      /* for mapping */   /*0x004C*/
-    volatile unsigned long  asc_whbcon;                         /*0x0050*/
-    volatile unsigned long  asc_whbabcon;                       /*0x0054*/
-    volatile unsigned long  asc_whbabstat;  /* not used */      /*0x0058*/
-
-} incaAsc_t;
-
-#endif /* __INCincaAscSioh */
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
deleted file mode 100644
index 41c37683d7..0000000000
--- a/drivers/serial/atmel_usart.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <common.h>
-
-#ifdef CONFIG_ATMEL_USART
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-#include "atmel_usart.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
-	unsigned long divisor;
-	unsigned long usart_hz;
-
-	/*
-	 *              Master Clock
-	 * Baud Rate = --------------
-	 *                16 * CD
-	 */
-	usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id);
-	divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
-	usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor));
-}
-
-int serial_init(void)
-{
-	usart3_writel(gd->console_uart, CR,
-		      USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
-
-	serial_setbrg();
-
-	usart3_writel(gd->console_uart, CR,
-		      USART3_BIT(RXEN) | USART3_BIT(TXEN));
-	usart3_writel(gd->console_uart, MR,
-		      USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
-		      | USART3_BF(USCLKS, USART3_USCLKS_MCK)
-		      | USART3_BF(CHRL, USART3_CHRL_8)
-		      | USART3_BF(PAR, USART3_PAR_NONE)
-		      | USART3_BF(NBSTOP, USART3_NBSTOP_1));
-
-	return 0;
-}
-
-void serial_putc(char c)
-{
-	if (c == '\n')
-		serial_putc('\r');
-
-	while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(TXRDY))) ;
-	usart3_writel(gd->console_uart, THR, c);
-}
-
-void serial_puts(const char *s)
-{
-	while (*s)
-		serial_putc(*s++);
-}
-
-int serial_getc(void)
-{
-	while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY))) ;
-	return usart3_readl(gd->console_uart, RHR);
-}
-
-int serial_tstc(void)
-{
-	return (usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY)) != 0;
-}
-
-#endif /* CONFIG_ATMEL_USART */
diff --git a/drivers/serial/ns9750_serial.c b/drivers/serial/ns9750_serial.c
deleted file mode 100644
index 02c0d39520..0000000000
--- a/drivers/serial/ns9750_serial.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Serial driver for the NS9750. Only one UART is supported yet.
- * @References: [1] NS9750 Hardware Reference/December 2003
- * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#ifdef CFG_NS9750_UART
-
-#include "ns9750_bbus.h"	/* for GPIOs */
-#include "ns9750_ser.h"		/* for serial configuration */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_CONS_INDEX)
-#error "No console index specified."
-#endif
-
-#define CONSOLE CONFIG_CONS_INDEX
-
-static unsigned int calcBitrateRegister( void );
-static unsigned int calcRxCharGapRegister( void );
-
-static char cCharsAvailable; /* Numbers of chars in unCharCache */
-static unsigned int unCharCache; /* unCharCache is only valid if
-				  * cCharsAvailable > 0 */
-
-/***********************************************************************
- * @Function: serial_init
- * @Return: 0
- * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off
- ***********************************************************************/
-
-int serial_init( void )
-{
-	unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
-	unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
-
-	cCharsAvailable = 0;
-
-	/* configure TxD and RxD pins for their special function */
-	set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ],
-			      NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT );
-	set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ],
-			      NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT );
-
-	/* configure serial engine */
-	*get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) =
-		NS9750_SER_CTRL_A_CE |
-		NS9750_SER_CTRL_A_STOP |
-		NS9750_SER_CTRL_A_WLS_8;
-
-	serial_setbrg();
-
-	*get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) =
-		NS9750_SER_CTRL_B_RCGT;
-
-	return 0;
-}
-
-/***********************************************************************
- * @Function: serial_putc
- * @Return: n/a
- * @Descr: writes one character to the FIFO. Blocks until FIFO is not full
- ***********************************************************************/
-
-void serial_putc( const char c )
-{
-	if (c == '\n')
-		serial_putc( '\r' );
-
-	while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) &
-		 NS9750_SER_STAT_A_TRDY ) ) {
-		/* do nothing, wait for characters in FIFO sent */
-	}
-
-	*(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO,
-						    CONSOLE) = c;
-}
-
-/***********************************************************************
- * @Function: serial_puts
- * @Return: n/a
- * @Descr: writes non-zero string to the FIFO.
- ***********************************************************************/
-
-void serial_puts( const char *s )
-{
-	while (*s) {
-		serial_putc( *s++ );
-	}
-}
-
-/***********************************************************************
- * @Function: serial_getc
- * @Return: the character read
- * @Descr: performs only 8bit accesses to the FIFO. No error handling
- ***********************************************************************/
-
-int serial_getc( void )
-{
-	int i;
-
-	while (!serial_tstc() ) {
-		/* do nothing, wait for incoming characters */
-	}
-
-	/*  at least one character in unCharCache */
-	i = (int) (unCharCache & 0xff);
-
-	unCharCache >>= 8;
-	cCharsAvailable--;
-
-	return i;
-}
-
-/***********************************************************************
- * @Function: serial_tstc
- * @Return: 0 if no input available, otherwise != 0
- * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in
- *	   unCharCache and the numbers of characters in cCharsAvailable
- ***********************************************************************/
-
-int serial_tstc( void )
-{
-	unsigned int unRegCache;
-
-	if ( cCharsAvailable )
-		return 1;
-
-	unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE );
-	if( unRegCache & NS9750_SER_STAT_A_RBC ) {
-		*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) =
-			NS9750_SER_STAT_A_RBC;
-		unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,
-							CONSOLE );
-	}
-
-	if ( unRegCache & NS9750_SER_STAT_A_RRDY ) {
-		cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20;
-		if ( !cCharsAvailable )
-			cCharsAvailable = 4;
-
-		unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO,
-							 CONSOLE );
-		return 1;
-	}
-
-	/* no chars available */
-	return 0;
-}
-
-void serial_setbrg( void )
-{
-	*get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) =
-		calcBitrateRegister();
-	*get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) =
-		calcRxCharGapRegister();
-}
-
-/***********************************************************************
- * @Function: calcBitrateRegister
- * @Return: value for the serial bitrate register
- * @Descr: register value depends on clock frequency and baudrate
- ***********************************************************************/
-
-static unsigned int calcBitrateRegister( void )
-{
-	return ( NS9750_SER_BITRATE_EBIT |
-		 NS9750_SER_BITRATE_CLKMUX_BCLK |
-		 NS9750_SER_BITRATE_TMODE |
-		 NS9750_SER_BITRATE_TCDR_16 |
-		 NS9750_SER_BITRATE_RCDR_16 |
-		 ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */
-		       ( gd->baudrate * 16 ) ) - 1 ) &
-		   NS9750_SER_BITRATE_N_MA ) );
-}
-
-/***********************************************************************
- * @Function: calcRxCharGapRegister
- * @Return: value for the character gap timer register
- * @Descr: register value depends on clock frequency and baudrate. Currently 0
- *	   is used as there is a bug with the gap timer in PLL bypass mode.
- ***********************************************************************/
-
-static unsigned int calcRxCharGapRegister( void )
-{
-	return NS9750_SER_RX_CHAR_TIMER_TRUN;
-}
-
-#endif /* CFG_NS9750_UART */
diff --git a/drivers/serial/s3c4510b_uart.c b/drivers/serial/s3c4510b_uart.c
deleted file mode 100644
index ddcd591f84..0000000000
--- a/drivers/serial/s3c4510b_uart.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * MODULE:        $Id:$
- * Description:   UART/Serial interface for Samsung S3C4510B SoC
- * Runtime Env:   ARM7TDMI
- * Change History:
- *     03-02-04    Create (Curt Brune) curt@cucy.com
- *
- */
-
-#include <common.h>
-
-#ifdef CONFIG_DRIVER_S3C4510_UART
-
-#include <asm/hardware.h>
-#include "s3c4510b_uart.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static UART    *uart;
-
-/* flush serial input queue. returns 0 on success or negative error
- * number otherwise
- */
-static int serial_flush_input(void)
-{
-	volatile u32 tmp;
-
-	/* keep on reading as long as the receiver is not empty */
-	while( uart->m_stat.bf.rxReady) {
-		tmp = uart->m_rx;
-	}
-
-	return 0;
-}
-
-
-/* flush output queue. returns 0 on success or negative error number
- * otherwise
- */
-static int serial_flush_output(void)
-{
-	/* wait until the transmitter is no longer busy */
-	while( !uart->m_stat.bf.txBufEmpty);
-
-	return 0;
-}
-
-
-void serial_setbrg (void)
-{
-	UART_LINE_CTRL ulctrl;
-	UART_CTRL      uctrl;
-	UART_BAUD_DIV  ubd;
-
-	serial_flush_output();
-	serial_flush_input();
-
-	/* control register */
-	uctrl.ui = 0x0;
-	uctrl.bf.rxMode = 0x1;
-	uctrl.bf.rxIrq = 0x0;
-	uctrl.bf.txMode = 0x1;
-	uctrl.bf.DSR = 0x0;
-	uctrl.bf.sendBreak = 0x0;
-	uctrl.bf.loopBack = 0x0;
-	uart->m_ctrl.ui = uctrl.ui;
-
-	/* line control register */
-	ulctrl.ui  = 0x0;
-	ulctrl.bf.wordLen   = 0x3; /* 8 bit data */
-	ulctrl.bf.nStop     = 0x0; /* 1 stop bit */
-	ulctrl.bf.parity    = 0x0; /* no parity */
-	ulctrl.bf.clk       = 0x0; /* internal clock */
-	ulctrl.bf.infra_red = 0x0; /* no infra_red */
-	uart->m_lineCtrl.ui = ulctrl.ui;
-
-	ubd.ui = 0x0;
-
-	/* see table on page 10-15 in SAMSUNG S3C4510B manual */
-	/* get correct divisor */
-	switch(gd->baudrate) {
-	case   1200:	ubd.bf.cnt0 = 1301;	break;
-	case   2400:	ubd.bf.cnt0 =  650;	break;
-	case   4800:	ubd.bf.cnt0 =  324;	break;
-	case   9600:	ubd.bf.cnt0 =  162;	break;
-	case  19200:	ubd.bf.cnt0 =   80;	break;
-	case  38400:	ubd.bf.cnt0 =   40;	break;
-	case  57600:	ubd.bf.cnt0 =   26;	break;
-	case 115200:	ubd.bf.cnt0 =   13;	break;
-	}
-
-	uart->m_baudDiv.ui = ubd.ui;
-	uart->m_baudCnt = 0x0;
-	uart->m_baudClk = 0x0;
-
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-
-#if   CONFIG_SERIAL1 == 1
-	uart = (UART *)UART0_BASE;
-#elif CONFIG_SERIAL1 == 2
-	uart = (UART *)UART1_BASE;
-#else
-#error CONFIG_SERIAL1 not equal to 1 or 2
-#endif
-
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	/* wait for room in the transmit FIFO */
-	while( !uart->m_stat.bf.txBufEmpty);
-
-	uart->m_tx = c;
-
-	/*
-		to be polite with serial console add a line feed
-		to the carriage return character
-	*/
-	if (c=='\n')
-		serial_putc('\r');
-}
-
-/*
- * Test if an input byte is ready from the serial port. Returns non-zero on
- * success, 0 otherwise.
- */
-int serial_tstc (void)
-{
-	return uart->m_stat.bf.rxReady;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	int rv;
-
-	for(;;) {
-		rv = serial_tstc();
-
-		if (rv) {
-			return uart->m_rx & 0xFF;
-		}
-	}
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-
-	/* busy wait for tx complete */
-	while ( !uart->m_stat.bf.txComplete);
-
-	/* clear break */
-	uart->m_ctrl.bf.sendBreak = 0;
-
-}
-
-#endif
diff --git a/drivers/serial/serial_au1x00.c b/drivers/serial/serial_au1x00.c
deleted file mode 100644
index 42c668ee3d..0000000000
--- a/drivers/serial/serial_au1x00.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * AU1X00 UART support
- *
- * Hardcoded to UART 0 for now
- * Speed and options also hardcoded to 115200 8N1
- *
- *  Copyright (c) 2003	Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#ifdef CONFIG_AU1X00
-
-#include <common.h>
-#include <asm/au1x00.h>
-
-/******************************************************************************
-*
-* serial_init - initialize a channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-	volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
-	volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
-
-	/* Enable clocks first */
-	*uart_enable = UART_EN_CE;
-
-	/* Then release reset */
-	/* Must release reset before setting other regs */
-	*uart_enable = UART_EN_CE|UART_EN_E;
-
-	/* Activate fifos, reset tx and rx */
-	/* Set tx trigger level to 12 */
-	*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
-		UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
-
-	serial_setbrg();
-
-	return 0;
-}
-
-
-void serial_setbrg (void)
-{
-	volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
-	volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
-	volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
-	int sd;
-	int divisorx2;
-
-	/* sd is system clock divisor			*/
-	/* see section 10.4.5 in au1550 datasheet	*/
-	sd = (*sys_powerctrl & 0x03) + 2;
-
-	/* calulate 2x baudrate and round */
-	divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE)));
-
-	if (divisorx2 & 0x01)
-		divisorx2 = divisorx2 + 1;
-
-	*uart_clk = divisorx2 / 2;
-
-	/* Set parity, stop bits and word length to 8N1 */
-	*uart_lcr = UART_LCR_WLEN8;
-}
-
-void serial_putc (const char c)
-{
-	volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-	volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
-
-	if (c == '\n') serial_putc ('\r');
-
-	/* Wait for fifo to shift out some bytes */
-	while((*uart_lsr&UART_LSR_THRE)==0);
-
-	*uart_tx = (u32)c;
-}
-
-void serial_puts (const char *s)
-{
-	while (*s)
-	{
-		serial_putc (*s++);
-	}
-}
-
-int serial_getc (void)
-{
-	volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
-	char c;
-
-	while (!serial_tstc());
-
-	c = (*uart_rx&0xFF);
-	return c;
-}
-
-int serial_tstc (void)
-{
-	volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-
-	if(*uart_lsr&UART_LSR_DR){
-		/* Data in rfifo */
-		return(1);
-	}
-	return 0;
-}
-#endif /* CONFIG_SERIAL_AU1X00 */
diff --git a/drivers/serial/serial_clps7111.c b/drivers/serial/serial_clps7111.c
deleted file mode 100644
index 054bab9811..0000000000
--- a/drivers/serial/serial_clps7111.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-
-#include <clps7111.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg (void)
-{
-	unsigned int reg = 0;
-
-	switch (gd->baudrate) {
-	case   1200:	reg = 191;	break;
-	case   9600:	reg =  23;	break;
-	case  19200:	reg =  11;	break;
-	case  38400:	reg =   5;	break;
-	case  57600:	reg =   3;	break;
-	case 115200:	reg =   1;	break;
-	default:	hang ();	break;
-	}
-
-	/* init serial serial 1,2 */
-	IO_SYSCON1 = SYSCON1_UART1EN;
-	IO_SYSCON2 = SYSCON2_UART2EN;
-
-	reg |= UBRLCR_WRDLEN8;
-
-	IO_UBRLCR1 = reg;
-	IO_UBRLCR2 = reg;
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	int tmo;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-
-	tmo = get_timer (0) + 1 * CFG_HZ;
-	while (IO_SYSFLG1 & SYSFLG1_UTXFF)
-		if (get_timer (0) > tmo)
-			break;
-
-	IO_UARTDR1 = c;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_tstc (void)
-{
-	return !(IO_SYSFLG1 & SYSFLG1_URXFE);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	while (IO_SYSFLG1 & SYSFLG1_URXFE);
-
-	return IO_UARTDR1 & 0xff;
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */
diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c
deleted file mode 100644
index 2015958571..0000000000
--- a/drivers/serial/serial_ixp.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg (void)
-{
-	unsigned int quot = 0;
-	int uart = CFG_IXP425_CONSOLE;
-
-	if (gd->baudrate == 1200)
-		quot = 192;
-	else if (gd->baudrate == 9600)
-		quot = 96;
-	else if (gd->baudrate == 19200)
-		quot = 48;
-	else if (gd->baudrate == 38400)
-		quot = 24;
-	else if (gd->baudrate == 57600)
-		quot = 16;
-	else if (gd->baudrate == 115200)
-		quot = 8;
-	else
-		hang ();
-
-	IER(uart) = 0;					/* Disable for now */
-	FCR(uart) = 0;					/* No fifos enabled */
-
-	/* set baud rate */
-	LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-	DLL(uart) = quot & 0xff;
-	DLH(uart) = quot >> 8;
-	LCR(uart) = LCR_WLS0 | LCR_WLS1;
-
-	IER(uart) = IER_UUE;
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	/* wait for room in the tx FIFO on UART */
-	while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0);
-
-	THR(CFG_IXP425_CONSOLE) = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_tstc (void)
-{
-	return LSR(CFG_IXP425_CONSOLE) & LSR_DR;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR));
-
-	return (char) RBR(CFG_IXP425_CONSOLE) & 0xff;
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
deleted file mode 100644
index aacd1be630..0000000000
--- a/drivers/serial/serial_ks8695.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * serial.c -- KS8695 serial driver
- *
- * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SERIAL1
-#error "Bad: you didn't configure serial ..."
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- *	Define the UART hardware register access structure.
- */
-struct ks8695uart {
-	unsigned int	RX;		/* 0x00	- Receive data (r) */
-	unsigned int	TX;		/* 0x04	- Transmit data (w) */
-	unsigned int	FCR;		/* 0x08	- Fifo Control (r/w) */
-	unsigned int	LCR;		/* 0x0c	- Line Control (r/w) */
-	unsigned int	MCR;		/* 0x10	- Modem Control (r/w) */
-	unsigned int	LSR;		/* 0x14	- Line Status (r/w) */
-	unsigned int	MSR;		/* 0x18	- Modem Status (r/w) */
-	unsigned int	BD;		/* 0x1c	- Baud Rate (r/w) */
-	unsigned int	SR;		/* 0x20	- Status (r/w) */
-};
-
-#define	KS8695_UART_ADDR	((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
-#define	KS8695_UART_CLK		25000000
-
-
-/*
- * Under some circumstances we want to be "quiet" and not issue any
- * serial output - though we want u-boot to otherwise work and behave
- * the same. By default be noisy.
- */
-int serial_console = 1;
-
-
-void serial_setbrg(void)
-{
-	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
-	/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
-	uartp->BD = KS8695_UART_CLK / gd->baudrate;
-	uartp->LCR = KS8695_UART_LINEC_WLEN8;
-}
-
-int serial_init(void)
-{
-	serial_console = 1;
-	serial_setbrg();
-	return 0;
-}
-
-void serial_raw_putc(const char c)
-{
-	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-	int i;
-
-	for (i = 0; (i < 0x100000); i++) {
-		if (uartp->LSR & KS8695_UART_LINES_TXFE)
-			break;
-	}
-
-	uartp->TX = c;
-}
-
-void serial_putc(const char c)
-{
-	if (serial_console) {
-		serial_raw_putc(c);
-		if (c == '\n')
-			serial_raw_putc('\r');
-	}
-}
-
-int serial_tstc(void)
-{
-	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-	if (serial_console)
-		return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
-	return 0;
-}
-
-void serial_puts(const char *s)
-{
-	char c;
-	while ((c = *s++) != 0)
-		serial_putc(c);
-}
-
-int serial_getc(void)
-{
-	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
-	while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
-		;
-	return (uartp->RX);
-}
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
deleted file mode 100644
index d727ccaa4f..0000000000
--- a/drivers/serial/serial_lh7a40x.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONSOLE_UART1)
-# define UART_CONSOLE 1
-#elif defined(CONFIG_CONSOLE_UART2)
-# define UART_CONSOLE 2
-#elif defined(CONFIG_CONSOLE_UART3)
-# define UART_CONSOLE 3
-#else
-# error "No console configured ... "
-#endif
-
-void serial_setbrg (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-	int i;
-	unsigned int reg = 0;
-
-	/*
-	 * userguide 15.1.2.4
-	 *
-	 * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
-	 *
-	 *   UART_REF_FREQ = external system clock input / 2 (Hz)
-	 *   BAUD is desired baudrate (bits/s)
-	 *
-	 *   NOTE: we add (divisor/2) to numerator to round for
-	 *         more precision
-	 */
-	reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
-	uart->brcon = reg;
-
-	for (i = 0; i < 100; i++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* UART must be enabled before writing to any config registers */
-	uart->con |= (UART_EN);
-
-#ifdef CONFIG_CONSOLE_UART1
-	/* infrared disabled */
-	uart->con |= UART_SIRD;
-#endif
-	/* loopback disabled */
-	uart->con &= ~(UART_LBE);
-
-	/* modem lines and tx/rx polarities */
-	uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
-
-	/* FIFO enable, N81 */
-	uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
-
-	/* set baudrate */
-	serial_setbrg ();
-
-	/* enable rx interrupt */
-	uart->inten |= UART_RI;
-
-	return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* wait for character to arrive */
-	while (uart->status & UART_RXFE);
-
-	return(uart->data & 0xff);
-}
-
-#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
-int hwflow_onoff(int on)
-{
-	switch(on) {
-	case 0:
-	default:
-		break; /* return current */
-	case 1:
-		hwflow = 1; /* turn on */
-		break;
-	case -1:
-		hwflow = 0; /* turn off */
-		break;
-	}
-	return hwflow;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* wait for room in the tx FIFO */
-	while (!(uart->status & UART_TXFE));
-
-#ifdef CONFIG_HWFLOW
-	/* Wait for CTS up */
-	while(hwflow && !(uart->status & UART_CTS));
-#endif
-
-	uart->data = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	return(!(uart->status & UART_RXFE));
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/drivers/serial/serial_max3100.c b/drivers/serial/serial_max3100.c
deleted file mode 100644
index 35c5596985..0000000000
--- a/drivers/serial/serial_max3100.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * (C) Copyright 2003
- *
- * Pantelis Antoniou <panto@intracom.gr>
- * Intracom S.A.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_MAX3100_SERIAL
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/**************************************************************/
-
-/* convienient macros */
-#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)
-
-#define MAX3100_SPI_TXD(x) \
-	do { \
-		if (x) \
-			MAX3100_SPI_TXD_PORT |=  MAX3100_SPI_TXD_BIT; \
-		else \
-			MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
-	} while(0)
-
-#define MAX3100_SPI_CLK(x) \
-	do { \
-		if (x) \
-			MAX3100_SPI_CLK_PORT |=  MAX3100_SPI_CLK_BIT; \
-		else \
-			MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
-	} while(0)
-
-#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)
-
-#define MAX3100_CS(x) \
-	do { \
-		if (x) \
-			MAX3100_CS_PORT |=  MAX3100_CS_BIT; \
-		else \
-			MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
-	} while(0)
-
-/**************************************************************/
-
-/* MAX3100 definitions */
-
-#define MAX3100_WC	(3 << 14)		/* write configuration */
-#define MAX3100_RC	(1 << 14)		/* read  configuration */
-#define MAX3100_WD	(2 << 14)		/* write data          */
-#define MAX3100_RD	(0 << 14)		/* read  data          */
-
-/* configuration register bits */
-#define MAX3100_FEN	(1 << 13)		/* FIFO enable           */
-#define MAX3100_SHDN    (1 << 12)		/* shutdown bit          */
-#define MAX3100_TM	(1 << 11)		/* T bit irq mask        */
-#define MAX3100_RM	(1 << 10)		/* R bit irq mask        */
-#define MAX3100_PM	(1 <<  9)		/* P bit irq mask        */
-#define MAX3100_RAM	(1 <<  8)		/* mask for RA/FE bit    */
-#define MAX3100_IR	(1 <<  7)		/* IRDA timing mode      */
-#define MAX3100_ST	(1 <<  6)		/* transmit stop bit     */
-#define MAX3100_PE	(1 <<  5)		/* parity enable bit     */
-#define MAX3100_L	(1 <<  4)		/* Length bit            */
-#define MAX3100_B_MASK	(0x000F)		/* baud rate bits mask   */
-#define MAX3100_B(x)	((x) & 0x000F)	/* baud rate select bits */
-
-/* data register bits (write) */
-#define MAX3100_TE	(1 << 10)		/* transmit enable bit (active low)        */
-#define MAX3100_RTS	(1 <<  9)		/* request-to-send bit (inverted ~RTS pin) */
-
-/* data register bits (read) */
-#define MAX3100_RA	(1 << 10)		/* receiver activity when in shutdown mode */
-#define MAX3100_FE	(1 << 10)		/* framing error when in normal mode       */
-#define MAX3100_CTS	(1 <<  9)		/* clear-to-send bit (inverted ~CTS pin)   */
-
-/* data register bits (both directions) */
-#define MAX3100_R 	(1 << 15)		/* receive bit    */
-#define MAX3100_T	(1 << 14)		/* transmit bit   */
-#define MAX3100_P	(1 <<  8)		/* parity bit     */
-#define MAX3100_D_MASK	0x00FF                  /* data bits mask */
-#define MAX3100_D(x)	((x) & 0x00FF)		/* data bits      */
-
-/* these definitions are valid only for fOSC = 3.6864MHz */
-#define MAX3100_B_230400        MAX3100_B(0)
-#define MAX3100_B_115200        MAX3100_B(1)
-#define MAX3100_B_57600         MAX3100_B(2)
-#define MAX3100_B_38400         MAX3100_B(9)
-#define MAX3100_B_19200         MAX3100_B(10)
-#define MAX3100_B_9600          MAX3100_B(11)
-#define MAX3100_B_4800          MAX3100_B(12)
-#define MAX3100_B_2400          MAX3100_B(13)
-#define MAX3100_B_1200          MAX3100_B(14)
-#define MAX3100_B_600           MAX3100_B(15)
-
-/**************************************************************/
-
-static inline unsigned int max3100_transfer(unsigned int val)
-{
-	unsigned int rx;
-	int b;
-
-	MAX3100_SPI_CLK(0);
-	MAX3100_CS(0);
-
-	rx = 0; b = 16;
-	while (--b >= 0) {
-		MAX3100_SPI_TXD(val & 0x8000);
-		val <<= 1;
-		MAX3100_SPI_CLK_TOGGLE();
-		udelay(1);
-		rx <<= 1;
-		if (MAX3100_SPI_RXD())
-			rx |= 1;
-		MAX3100_SPI_CLK_TOGGLE();
-		udelay(1);
-	}
-
-	MAX3100_SPI_CLK(1);
-	MAX3100_CS(1);
-
-	return rx;
-}
-
-/**************************************************************/
-
-/* must be power of 2 */
-#define RXFIFO_SZ	16
-
-static int rxfifo_cnt;
-static int rxfifo_in;
-static int rxfifo_out;
-static unsigned char rxfifo_buf[16];
-
-static void max3100_putc(int c)
-{
-	unsigned int rx;
-
-	while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0)
-		WATCHDOG_RESET();
-
-	rx = max3100_transfer(MAX3100_WD | (c & 0xff));
-	if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) {
-		rxfifo_cnt++;
-		rxfifo_buf[rxfifo_in++] = rx & 0xff;
-		rxfifo_in &= RXFIFO_SZ - 1;
-	}
-}
-
-static int max3100_getc(void)
-{
-	int c;
-	unsigned int rx;
-
-	while (rxfifo_cnt == 0) {
-		rx = max3100_transfer(MAX3100_RD);
-		if ((rx & MAX3100_R) != 0) {
-			do {
-				rxfifo_cnt++;
-				rxfifo_buf[rxfifo_in++] = rx & 0xff;
-				rxfifo_in &= RXFIFO_SZ - 1;
-
-				if (rxfifo_cnt >= RXFIFO_SZ)
-					break;
-			} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
-		}
-		WATCHDOG_RESET();
-	}
-
-	rxfifo_cnt--;
-	c = rxfifo_buf[rxfifo_out++];
-	rxfifo_out &= RXFIFO_SZ - 1;
-	return c;
-}
-
-static int max3100_tstc(void)
-{
-	unsigned int rx;
-
-	if (rxfifo_cnt > 0)
-		return 1;
-
-	rx = max3100_transfer(MAX3100_RD);
-	if ((rx & MAX3100_R) == 0)
-		return 0;
-
-	do {
-		rxfifo_cnt++;
-		rxfifo_buf[rxfifo_in++] = rx & 0xff;
-		rxfifo_in &= RXFIFO_SZ - 1;
-
-		if (rxfifo_cnt >= RXFIFO_SZ)
-			break;
-	} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
-
-	return 1;
-}
-
-int serial_init(void)
-{
-	unsigned int wconf, rconf;
-	int i;
-
-	wconf = 0;
-
-	/* Set baud rate */
-	switch (gd->baudrate) {
-		case 1200:
-			wconf = MAX3100_B_1200;
-			break;
-		case 2400:
-			wconf = MAX3100_B_2400;
-			break;
-		case 4800:
-			wconf = MAX3100_B_4800;
-			break;
-		case 9600:
-			wconf = MAX3100_B_9600;
-			break;
-		case 19200:
-			wconf = MAX3100_B_19200;
-			break;
-		case 38400:
-			wconf = MAX3100_B_38400;
-			break;
-		case 57600:
-			wconf = MAX3100_B_57600;
-			break;
-		default:
-		case 115200:
-			wconf = MAX3100_B_115200;
-			break;
-		case 230400:
-			wconf = MAX3100_B_230400;
-			break;
-	}
-
-	/* try for 10ms, with a 100us gap */
-	for (i = 0; i < 10000; i += 100) {
-
-		max3100_transfer(MAX3100_WC | wconf);
-		rconf = max3100_transfer(MAX3100_RC) & 0x3fff;
-
-		if (rconf == wconf)
-			break;
-		udelay(100);
-	}
-
-	rxfifo_in = rxfifo_out = rxfifo_cnt = 0;
-
-	return (0);
-}
-
-void serial_putc(const char c)
-{
-	if (c == '\n')
-		max3100_putc('\r');
-
-	max3100_putc(c);
-}
-
-void serial_puts(const char *s)
-{
-	while (*s)
-		serial_putc (*s++);
-}
-
-int serial_getc(void)
-{
-	return max3100_getc();
-}
-
-int serial_tstc(void)
-{
-	return max3100_tstc();
-}
-
-/* XXX WTF? */
-void serial_setbrg(void)
-{
-}
-
-#endif
diff --git a/drivers/serial/serial_mcf52x2.c b/drivers/serial/serial_mcf52x2.c
deleted file mode 100644
index 8be09e34fe..0000000000
--- a/drivers/serial/serial_mcf52x2.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <watchdog.h>
-
-#include <asm/mcfuart.h>
-
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#endif
-
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#endif
-
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#endif
-
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5271)
-#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a))
-#else
-#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a))
-#endif
-
-void rs_serial_setbaudrate(int port,int baudrate)
-{
-#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
-	volatile unsigned char	*uartp;
-# ifndef CONFIG_M5271
-	double fraction;
-# endif
-	double clock;
-
-	if (port == 0)
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-	else
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
-
-	clock = DoubleClock(baudrate);	/* Set baud above */
-
-	uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff);	/* set msb baud */
-	uartp[MCFUART_UBG2] = ((int)clock & 0xff);		/* set lsb baud */
-
-# ifndef CONFIG_M5271
-	fraction = ((clock - (int)clock) * 16.0) + 0.5;
-	uartp[MCFUART_UFPD] = ((int)fraction & 0xf);	/* set baud fraction adjust */
-# endif
-#endif
-
-#if  defined(CONFIG_M5282)
-	volatile unsigned char	*uartp;
-	long clock;
-
-	switch (port) {
-	case 1:
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
-		break;
-	case 2:
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
-		break;
-	default:
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-	}
-
-	clock = (long) CFG_CLK / ((long) 32 * baudrate);	/* Set baud above */
-
-	uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff);	/* set msb baud */
-	uartp[MCFUART_UBG2] = ((int) clock & 0xff);		/* set lsb baud */
-
-#endif
-};
-
-void rs_serial_init (int port, int baudrate)
-{
-	volatile unsigned char *uartp;
-
-	/*
-	 *      Reset UART, get it into known state...
-	 */
-	switch (port) {
-	case 1:
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
-		break;
-#if  defined(CONFIG_M5282)
-	case 2:
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
-		break;
-#endif
-	default:
-		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-	}
-
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX;	/* reset TX */
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX;	/* reset RX */
-
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR;	/* reset MR pointer */
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR;	/* reset Error pointer */
-
-	/*
-	 * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
-	 */
-	uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8;
-	uartp[MCFUART_UMR] = MCFUART_MR2_STOP1;
-
-	/* Mask UART interrupts */
-	uartp[MCFUART_UIMR] = 0;
-
-	/* Set clock Select Register: Tx/Rx clock is timer */
-	uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
-
-	rs_serial_setbaudrate (port, baudrate);
-
-	/* Enable Tx/Rx */
-	uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
-
-	return;
-}
-
-/****************************************************************************/
-/*
- *	Output a single character, using UART polled mode.
- *	This is used for console output.
- */
-
-void rs_put_char(char ch)
-{
-	volatile unsigned char	*uartp;
-	int			i;
-
-	uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-
-	for (i = 0; (i < 0x10000); i++) {
-		if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY)
-			break;
-	}
-	uartp[MCFUART_UTB] = ch;
-	return;
-}
-
-int rs_is_char(void)
-{
-	volatile unsigned char	*uartp;
-
-	uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-	return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0);
-}
-
-int rs_get_char(void)
-{
-	volatile unsigned char	*uartp;
-
-	uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-	return(uartp[MCFUART_URB]);
-}
-
-void serial_setbrg(void) {
-	rs_serial_setbaudrate(0,gd->bd->bi_baudrate);
-}
-
-int serial_init(void) {
-	rs_serial_init(0,gd->baudrate);
-	return 0;
-}
-
-
-void serial_putc(const char c) {
-	if (c == '\n')
-		serial_putc ('\r');
-	rs_put_char(c);
-}
-
-void serial_puts (const char *s) {
-	while (*s)
-		serial_putc(*s++);
-}
-
-int serial_getc(void) {
-	while(!rs_is_char())
-		WATCHDOG_RESET();
-
-	return rs_get_char();
-}
-
-int serial_tstc() {
-	return rs_is_char();
-}
diff --git a/drivers/serial/serial_mpc5xx.c b/drivers/serial/serial_mpc5xx.c
deleted file mode 100644
index ac5556f05c..0000000000
--- a/drivers/serial/serial_mpc5xx.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation,
- */
-
-/*
- * File:		serial.c
- *
- * Discription:		Serial interface driver for SCI1 and SCI2.
- *     			Since this code will be called from ROM use
- * 			only non-static local variables.
- *
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <mpc5xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Local function prototypes
- */
-
-static int ready_to_send(void);
-
-/*
- * Minimal global serial functions needed to use one of the SCI modules.
- */
-
-int serial_init (void)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
-	serial_setbrg();
-
-#if defined(CONFIG_5xx_CONS_SCI1)
-	/* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */
-	immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10;
-	immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE;
-#else
-	immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10;
-	immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE;
-#endif
-	return 0;
-}
-
-void serial_putc(const char c)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
-	/* Test for completition */
-	if(ready_to_send()) {
-#if defined(CONFIG_5xx_CONS_SCI1)
-		immr->im_qsmcm.qsmcm_sc1dr = (short)c;
-#else
-		immr->im_qsmcm.qsmcm_sc2dr = (short)c;
-#endif
-		if(c == '\n') {
-			if(ready_to_send());
-#if defined(CONFIG_5xx_CONS_SCI1)
-			immr->im_qsmcm.qsmcm_sc1dr = (short)'\r';
-#else
-			immr->im_qsmcm.qsmcm_sc2dr = (short)'\r';
-#endif
-		}
-	}
-}
-
-int serial_getc(void)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile short status;
-	unsigned char tmp;
-
-	/* New data ? */
-	do {
-#if defined(CONFIG_5xx_CONS_SCI1)
-		status = immr->im_qsmcm.qsmcm_sc1sr;
-#else
-		status = immr->im_qsmcm.qsmcm_sc2sr;
-#endif
-
-#if defined(CONFIG_WATCHDOG)
-		reset_5xx_watchdog (immr);
-#endif
-	} while ((status & SCI_RDRF) == 0);
-
-	/* Read data */
-#if defined(CONFIG_5xx_CONS_SCI1)
-	tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK);
-#else
-	tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK);
-#endif
-	return	tmp;
-}
-
-int serial_tstc()
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	short status;
-
-	/* New data character ? */
-#if defined(CONFIG_5xx_CONS_SCI1)
-	status = immr->im_qsmcm.qsmcm_sc1sr;
-#else
-	status = immr->im_qsmcm.qsmcm_sc2sr;
-#endif
-	return (status & SCI_RDRF);
-}
-
-void serial_setbrg (void)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	short scxbr;
-
-	/* Set baudrate */
-	scxbr = (gd->cpu_clk / (32 * gd->baudrate));
-#if defined(CONFIG_5xx_CONS_SCI1)
-	immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK);
-#else
-	immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK);
-#endif
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc(*s);
-		++s;
-	}
-}
-
-int ready_to_send(void)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile short status;
-
-	do {
-#if defined(CONFIG_5xx_CONS_SCI1)
-		status = immr->im_qsmcm.qsmcm_sc1sr;
-#else
-		status = immr->im_qsmcm.qsmcm_sc2sr;
-#endif
-
-#if defined(CONFIG_WATCHDOG)
-		reset_5xx_watchdog (immr);
-#endif
-	} while ((status & SCI_TDRE) == 0);
-	return 1;
-
-}
diff --git a/drivers/serial/serial_mpc8260_scc.c b/drivers/serial/serial_mpc8260_scc.c
deleted file mode 100644
index 3a6eaf0a67..0000000000
--- a/drivers/serial/serial_mpc8260_scc.c
+++ /dev/null
@@ -1,498 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
- */
-
-/*
- * Minimal serial functions needed to use one of the SCC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <asm/cpm_8260.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONS_ON_SCC)
-
-#if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
-
-#define SCC_INDEX		0
-#define PROFF_SCC		PROFF_SCC1
-#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
-					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */
-
-#define SCC_INDEX		1
-#define PROFF_SCC		PROFF_SCC2
-#define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
-					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */
-
-#define SCC_INDEX		2
-#define PROFF_SCC		PROFF_SCC3
-#define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
-					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */
-
-#define SCC_INDEX		3
-#define PROFF_SCC		PROFF_SCC4
-#define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
-					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
-
-#else
-
-#error "console not correctly defined"
-
-#endif
-
-int serial_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile scc_t *sp;
-	volatile scc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile cpm8260_t *cp = &(im->im_cpm);
-	uint	dpaddr;
-
-	/* initialize pointers to SCC */
-
-	sp = (scc_t *) &(im->im_scc[SCC_INDEX]);
-	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-	/* put the SCC channel into NMSI (non multiplexd serial interface)
-	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
-	 */
-	im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE;
-
-	/* Set up the baud rate generator.
-	*/
-	serial_setbrg ();
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = BD_SC_WRAP;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->scc_genscc.scc_rbase = dpaddr;
-	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
-	up->scc_genscc.scc_rfcr = CPMFCR_EB;
-	up->scc_genscc.scc_tfcr = CPMFCR_EB;
-	up->scc_genscc.scc_mrblr = 1;
-	up->scc_maxidl = 0;
-	up->scc_brkcr = 1;
-	up->scc_parec = 0;
-	up->scc_frmec = 0;
-	up->scc_nosec = 0;
-	up->scc_brkec = 0;
-	up->scc_uaddr1 = 0;
-	up->scc_uaddr2 = 0;
-	up->scc_toseq = 0;
-	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
-	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
-	up->scc_rccm = 0xc0ff;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->scc_sccm = 0;
-	sp->scc_scce = 0xffff;
-
-	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
-	*/
-	sp->scc_gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
-	sp->scc_gsmrl = \
-		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
-
-	/* Set CTS flow control, 1 stop bit, 8 bit character length,
-	 * normal async UART mode, no parity
-	 */
-	sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
-
-	/* execute the "Init Rx and Tx params" CP command.
-	*/
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
-					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
-
-	return (0);
-}
-
-void
-serial_setbrg (void)
-{
-#if defined(CONFIG_CONS_USE_EXTC)
-	m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
-		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
-#else
-	m8260_cpm_setbrg(SCC_INDEX, gd->baudrate);
-#endif
-}
-
-void
-serial_putc(const char c)
-{
-	volatile scc_uart_t	*up;
-	volatile cbd_t		*tbdf;
-	volatile immap_t	*im;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
-	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
-
-	/* Wait for last character to go.
-	 */
-	while (tbdf->cbd_sc & BD_SC_READY)
-		;
-
-	/* Load the character into the transmit buffer.
-	 */
-	*(volatile char *)tbdf->cbd_bufaddr = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int
-serial_getc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
-	unsigned char		c;
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
-	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
-
-	/* Wait for character to show up.
-	 */
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		;
-
-	/* Grab the char and clear the buffer again.
-	 */
-	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return (c);
-}
-
-int
-serial_tstc()
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
-	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
-
-	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
-}
-
-#endif	/* CONFIG_CONS_ON_SCC */
-
-#if defined(CONFIG_KGDB_ON_SCC)
-
-#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
-#error Whoops! serial console and kgdb are on the same scc serial port
-#endif
-
-#if CONFIG_KGDB_INDEX == 1	/* KGDB Port on SCC1 */
-
-#define KGDB_SCC_INDEX		0
-#define KGDB_PROFF_SCC		PROFF_SCC1
-#define KGDB_CMXSCR_MASK	(CMXSCR_GR1|CMXSCR_SC1|\
-					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
-#define KGDB_CMXSCR_VALUE	(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
-#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC1_PAGE
-#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
-
-#elif CONFIG_KGDB_INDEX == 2	/* KGDB Port on SCC2 */
-
-#define KGDB_SCC_INDEX		1
-#define KGDB_PROFF_SCC		PROFF_SCC2
-#define KGDB_CMXSCR_MASK	(CMXSCR_GR2|CMXSCR_SC2|\
-					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
-#define KGDB_CMXSCR_VALUE	(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
-#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC2_PAGE
-#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
-
-#elif CONFIG_KGDB_INDEX == 3	/* KGDB Port on SCC3 */
-
-#define KGDB_SCC_INDEX		2
-#define KGDB_PROFF_SCC		PROFF_SCC3
-#define KGDB_CMXSCR_MASK	(CMXSCR_GR3|CMXSCR_SC3|\
-					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
-#define KGDB_CMXSCR_VALUE	(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
-#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC3_PAGE
-#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
-
-#elif CONFIG_KGDB_INDEX == 4	/* KGDB Port on SCC4 */
-
-#define KGDB_SCC_INDEX		3
-#define KGDB_PROFF_SCC		PROFF_SCC4
-#define KGDB_CMXSCR_MASK	(CMXSCR_GR4|CMXSCR_SC4|\
-					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
-#define KGDB_CMXSCR_VALUE	(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
-#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC4_PAGE
-#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
-
-#else
-
-#error "kgdb serial port not correctly defined"
-
-#endif
-
-void
-kgdb_serial_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile scc_t *sp;
-	volatile scc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile cpm8260_t *cp = &(im->im_cpm);
-	uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
-	char *s, *e;
-
-	if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
-		ulong rate = simple_strtoul(s, &e, 10);
-		if (e > s && *e == '\0')
-			speed = rate;
-	}
-
-	/* initialize pointers to SCC */
-
-	sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]);
-	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-	/* put the SCC channel into NMSI (non multiplexd serial interface)
-	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
-	 */
-	im->im_cpmux.cmx_scr = \
-		(im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE;
-
-	/* Set up the baud rate generator.
-	*/
-#if defined(CONFIG_KGDB_USE_EXTC)
-	m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
-		CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
-#else
-	m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
-#endif
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = BD_SC_WRAP;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->scc_genscc.scc_rbase = dpaddr;
-	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
-	up->scc_genscc.scc_rfcr = CPMFCR_EB;
-	up->scc_genscc.scc_tfcr = CPMFCR_EB;
-	up->scc_genscc.scc_mrblr = 1;
-	up->scc_maxidl = 0;
-	up->scc_brkcr = 1;
-	up->scc_parec = 0;
-	up->scc_frmec = 0;
-	up->scc_nosec = 0;
-	up->scc_brkec = 0;
-	up->scc_uaddr1 = 0;
-	up->scc_uaddr2 = 0;
-	up->scc_toseq = 0;
-	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
-	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
-	up->scc_rccm = 0xc0ff;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->scc_sccm = 0;
-	sp->scc_scce = 0xffff;
-
-	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
-	*/
-	sp->scc_gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
-	sp->scc_gsmrl = \
-		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
-
-	/* Set CTS flow control, 1 stop bit, 8 bit character length,
-	 * normal async UART mode, no parity
-	 */
-	sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
-
-	/* execute the "Init Rx and Tx params" CP command.
-	*/
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK,
-					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
-
-	printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
-}
-
-void
-putDebugChar(const char c)
-{
-	volatile scc_uart_t	*up;
-	volatile cbd_t		*tbdf;
-	volatile immap_t	*im;
-
-	if (c == '\n')
-		putDebugChar ('\r');
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
-	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
-
-	/* Wait for last character to go.
-	 */
-	while (tbdf->cbd_sc & BD_SC_READY)
-		;
-
-	/* Load the character into the transmit buffer.
-	 */
-	*(volatile char *)tbdf->cbd_bufaddr = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-}
-
-void
-putDebugStr (const char *s)
-{
-	while (*s) {
-		putDebugChar (*s++);
-	}
-}
-
-int
-getDebugChar(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
-	unsigned char		c;
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
-	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
-
-	/* Wait for character to show up.
-	 */
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		;
-
-	/* Grab the char and clear the buffer again.
-	 */
-	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return (c);
-}
-
-void
-kgdb_interruptible(int yes)
-{
-	return;
-}
-
-#endif	/* CONFIG_KGDB_ON_SCC */
diff --git a/drivers/serial/serial_mpc8260_smc.c b/drivers/serial/serial_mpc8260_smc.c
deleted file mode 100644
index f3dffeb119..0000000000
--- a/drivers/serial/serial_mpc8260_smc.c
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
- * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the
- * Linux/PPC sources (m8260_tty.c had no copyright info in it).
- */
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <asm/cpm_8260.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONS_ON_SMC)
-
-#if CONFIG_CONS_INDEX == 1	/* Console on SMC1 */
-
-#define SMC_INDEX		0
-#define PROFF_SMC_BASE		PROFF_SMC1_BASE
-#define PROFF_SMC		PROFF_SMC1
-#define CPM_CR_SMC_PAGE		CPM_CR_SMC1_PAGE
-#define CPM_CR_SMC_SBLOCK	CPM_CR_SMC1_SBLOCK
-#define CMXSMR_MASK		(CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
-#define CMXSMR_VALUE		CMXSMR_SMC1CS_BRG7
-
-#elif CONFIG_CONS_INDEX == 2	/* Console on SMC2 */
-
-#define SMC_INDEX		1
-#define PROFF_SMC_BASE		PROFF_SMC2_BASE
-#define PROFF_SMC		PROFF_SMC2
-#define CPM_CR_SMC_PAGE		CPM_CR_SMC2_PAGE
-#define CPM_CR_SMC_SBLOCK	CPM_CR_SMC2_SBLOCK
-#define CMXSMR_MASK		(CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
-#define CMXSMR_VALUE		CMXSMR_SMC2CS_BRG8
-
-#else
-
-#error "console not correctly defined"
-
-#endif
-
-/* map rs_table index to baud rate generator index */
-static unsigned char brg_map[] = {
-	6,	/* BRG7 for SMC1 */
-	7,	/* BRG8 for SMC2 */
-	0,	/* BRG1 for SCC1 */
-	1,	/* BRG1 for SCC2 */
-	2,	/* BRG1 for SCC3 */
-	3,	/* BRG1 for SCC4 */
-};
-
-int serial_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile smc_t *sp;
-	volatile smc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile cpm8260_t *cp = &(im->im_cpm);
-	uint	dpaddr;
-
-	/* initialize pointers to SMC */
-
-	sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
-	*(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
-	up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
-
-	/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = 0;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = 0;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->smc_rbase = dpaddr;
-	up->smc_tbase = dpaddr+sizeof(cbd_t);
-	up->smc_rfcr = CPMFCR_EB;
-	up->smc_tfcr = CPMFCR_EB;
-	up->smc_brklen = 0;
-	up->smc_brkec = 0;
-	up->smc_brkcr = 0;
-
-	/* Set UART mode, 8 bit, no parity, one stop.
-	 * Enable receive and transmit.
-	 */
-	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->smc_smcm = 0;
-	sp->smc_smce = 0xff;
-
-	/* put the SMC channel into NMSI (non multiplexd serial interface)
-	 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
-	 */
-	im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
-
-	/* Set up the baud rate generator.
-	*/
-	serial_setbrg ();
-
-	/* Make the first buffer the only buffer.
-	*/
-	tbdf->cbd_sc |= BD_SC_WRAP;
-	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
-
-	/* Single character receive.
-	*/
-	up->smc_mrblr = 1;
-	up->smc_maxidl = 0;
-
-	/* Initialize Tx/Rx parameters.
-	*/
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
-					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
-
-	return (0);
-}
-
-void
-serial_setbrg (void)
-{
-#if defined(CONFIG_CONS_USE_EXTC)
-	m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
-		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
-#else
-	m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
-#endif
-}
-
-void
-serial_putc(const char c)
-{
-	volatile cbd_t		*tbdf;
-	volatile char		*buf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
-
-	tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
-
-	/* Wait for last character to go.
-	*/
-	buf = (char *)tbdf->cbd_bufaddr;
-	while (tbdf->cbd_sc & BD_SC_READY)
-		;
-
-	*buf = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int
-serial_getc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile unsigned char	*buf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	unsigned char		c;
-
-	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
-
-	rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
-
-	/* Wait for character to show up.
-	*/
-	buf = (unsigned char *)rbdf->cbd_bufaddr;
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		;
-	c = *buf;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return(c);
-}
-
-int
-serial_tstc()
-{
-	volatile cbd_t		*rbdf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-
-	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
-
-	rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
-
-	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
-}
-
-#endif	/* CONFIG_CONS_ON_SMC */
-
-#if defined(CONFIG_KGDB_ON_SMC)
-
-#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
-#error Whoops! serial console and kgdb are on the same smc serial port
-#endif
-
-#if CONFIG_KGDB_INDEX == 1	/* KGDB Port on SMC1 */
-
-#define KGDB_SMC_INDEX		0
-#define KGDB_PROFF_SMC_BASE	PROFF_SMC1_BASE
-#define KGDB_PROFF_SMC		PROFF_SMC1
-#define KGDB_CPM_CR_SMC_PAGE	CPM_CR_SMC1_PAGE
-#define KGDB_CPM_CR_SMC_SBLOCK	CPM_CR_SMC1_SBLOCK
-#define KGDB_CMXSMR_MASK	(CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
-#define KGDB_CMXSMR_VALUE	CMXSMR_SMC1CS_BRG7
-
-#elif CONFIG_KGDB_INDEX == 2	/* KGDB Port on SMC2 */
-
-#define KGDB_SMC_INDEX		1
-#define KGDB_PROFF_SMC_BASE	PROFF_SMC2_BASE
-#define KGDB_PROFF_SMC		PROFF_SMC2
-#define KGDB_CPM_CR_SMC_PAGE	CPM_CR_SMC2_PAGE
-#define KGDB_CPM_CR_SMC_SBLOCK	CPM_CR_SMC2_SBLOCK
-#define KGDB_CMXSMR_MASK	(CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
-#define KGDB_CMXSMR_VALUE	CMXSMR_SMC2CS_BRG8
-
-#else
-
-#error "console not correctly defined"
-
-#endif
-
-void
-kgdb_serial_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile smc_t *sp;
-	volatile smc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile cpm8260_t *cp = &(im->im_cpm);
-	uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
-	char *s, *e;
-
-	if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
-		ulong rate = simple_strtoul(s, &e, 10);
-		if (e > s && *e == '\0')
-			speed = rate;
-	}
-
-	/* initialize pointers to SMC */
-
-	sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
-	*(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
-	up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
-
-	/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = 0;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = 0;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->smc_rbase = dpaddr;
-	up->smc_tbase = dpaddr+sizeof(cbd_t);
-	up->smc_rfcr = CPMFCR_EB;
-	up->smc_tfcr = CPMFCR_EB;
-	up->smc_brklen = 0;
-	up->smc_brkec = 0;
-	up->smc_brkcr = 0;
-
-	/* Set UART mode, 8 bit, no parity, one stop.
-	 * Enable receive and transmit.
-	 */
-	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->smc_smcm = 0;
-	sp->smc_smce = 0xff;
-
-	/* put the SMC channel into NMSI (non multiplexd serial interface)
-	 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
-	 */
-	im->im_cpmux.cmx_smr =
-		(im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
-
-	/* Set up the baud rate generator.
-	*/
-#if defined(CONFIG_KGDB_USE_EXTC)
-	m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
-		CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
-#else
-	m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
-#endif
-
-	/* Make the first buffer the only buffer.
-	*/
-	tbdf->cbd_sc |= BD_SC_WRAP;
-	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
-
-	/* Single character receive.
-	*/
-	up->smc_mrblr = 1;
-	up->smc_maxidl = 0;
-
-	/* Initialize Tx/Rx parameters.
-	*/
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
-					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
-
-	printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
-}
-
-void
-putDebugChar(const char c)
-{
-	volatile cbd_t		*tbdf;
-	volatile char		*buf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-
-	if (c == '\n')
-		putDebugChar ('\r');
-
-	up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
-
-	tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
-
-	/* Wait for last character to go.
-	*/
-	buf = (char *)tbdf->cbd_bufaddr;
-	while (tbdf->cbd_sc & BD_SC_READY)
-		;
-
-	*buf = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-}
-
-void
-putDebugStr (const char *s)
-{
-	while (*s) {
-		putDebugChar (*s++);
-	}
-}
-
-int
-getDebugChar(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile unsigned char	*buf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	unsigned char		c;
-
-	up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
-
-	rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
-
-	/* Wait for character to show up.
-	*/
-	buf = (unsigned char *)rbdf->cbd_bufaddr;
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		;
-	c = *buf;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return(c);
-}
-
-void
-kgdb_interruptible(int yes)
-{
-	return;
-}
-
-#endif	/* CONFIG_KGDB_ON_SMC */
diff --git a/drivers/serial/serial_mpc85xx_scc.c b/drivers/serial/serial_mpc85xx_scc.c
deleted file mode 100644
index 4e925f8bea..0000000000
--- a/drivers/serial/serial_mpc85xx_scc.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao (X.Xiao@motorola.com)
- * Modified based on 8260 for 8560.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
- */
-
-/*
- * Minimal serial functions needed to use one of the SCC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <asm/cpm_85xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CPM2)
-#if defined(CONFIG_CONS_ON_SCC)
-
-#if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
-
-#define SCC_INDEX		0
-#define PROFF_SCC		PROFF_SCC1
-#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
-					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */
-
-#define SCC_INDEX		1
-#define PROFF_SCC		PROFF_SCC2
-#define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
-					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */
-
-#define SCC_INDEX		2
-#define PROFF_SCC		PROFF_SCC3
-#define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
-					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */
-
-#define SCC_INDEX		3
-#define PROFF_SCC		PROFF_SCC4
-#define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
-					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
-
-#else
-
-#error "console not correctly defined"
-
-#endif
-
-int serial_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile ccsr_cpm_scc_t *sp;
-	volatile scc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
-	uint	dpaddr;
-
-	/* initialize pointers to SCC */
-
-	sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-	/* put the SCC channel into NMSI (non multiplexd serial interface)
-	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
-	 */
-	im->im_cpm.im_cpm_mux.cmxscr = \
-		(im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
-
-	/* Set up the baud rate generator.
-	*/
-	serial_setbrg ();
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-	rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = BD_SC_WRAP;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->scc_genscc.scc_rbase = dpaddr;
-	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
-	up->scc_genscc.scc_rfcr = CPMFCR_EB;
-	up->scc_genscc.scc_tfcr = CPMFCR_EB;
-	up->scc_genscc.scc_mrblr = 1;
-	up->scc_maxidl = 0;
-	up->scc_brkcr = 1;
-	up->scc_parec = 0;
-	up->scc_frmec = 0;
-	up->scc_nosec = 0;
-	up->scc_brkec = 0;
-	up->scc_uaddr1 = 0;
-	up->scc_uaddr2 = 0;
-	up->scc_toseq = 0;
-	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
-	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
-	up->scc_rccm = 0xc0ff;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->sccm = 0;
-	sp->scce = 0xffff;
-
-	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
-	*/
-	sp->gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
-	sp->gsmrl = \
-		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
-
-	/* Set CTS no flow control, 1 stop bit, 8 bit character length,
-	 * normal async UART mode, no parity
-	 */
-	sp->psmr = SCU_PSMR_CL;
-
-	/* execute the "Init Rx and Tx params" CP command.
-	*/
-
-	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
-					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
-
-	return (0);
-}
-
-void
-serial_setbrg (void)
-{
-#if defined(CONFIG_CONS_USE_EXTC)
-	m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
-		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
-#else
-	m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
-#endif
-}
-
-void
-serial_putc(const char c)
-{
-	volatile scc_uart_t	*up;
-	volatile cbd_t		*tbdf;
-	volatile immap_t	*im;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-	tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
-
-	/* Wait for last character to go.
-	 */
-	while (tbdf->cbd_sc & BD_SC_READY)
-		;
-
-	/* Load the character into the transmit buffer.
-	 */
-	*(volatile char *)tbdf->cbd_bufaddr = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int
-serial_getc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
-	unsigned char		c;
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-	rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
-
-	/* Wait for character to show up.
-	 */
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		;
-
-	/* Grab the char and clear the buffer again.
-	 */
-	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return (c);
-}
-
-int
-serial_tstc()
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
-
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-	rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
-
-	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
-}
-
-#endif	/* CONFIG_CONS_ON_SCC */
-
-#endif /* CONFIG_CPM2 */
diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c
deleted file mode 100644
index af5f4cf201..0000000000
--- a/drivers/serial/serial_mpc8xx.c
+++ /dev/null
@@ -1,704 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <command.h>
-#include <serial.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_8xx_CONS_NONE)	/* No Console at all */
-
-#if defined(CONFIG_8xx_CONS_SMC1)	/* Console on SMC1 */
-#define	SMC_INDEX	0
-#define PROFF_SMC	PROFF_SMC1
-#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
-
-#elif defined(CONFIG_8xx_CONS_SMC2)	/* Console on SMC2 */
-#define SMC_INDEX	1
-#define PROFF_SMC	PROFF_SMC2
-#define CPM_CR_CH_SMC	CPM_CR_CH_SMC2
-
-#endif /* CONFIG_8xx_CONS_SMCx */
-
-#if defined(CONFIG_8xx_CONS_SCC1)	/* Console on SCC1 */
-#define SCC_INDEX	0
-#define PROFF_SCC	PROFF_SCC1
-#define CPM_CR_CH_SCC	CPM_CR_CH_SCC1
-
-#elif defined(CONFIG_8xx_CONS_SCC2)	/* Console on SCC2 */
-#define SCC_INDEX	1
-#define PROFF_SCC	PROFF_SCC2
-#define CPM_CR_CH_SCC	CPM_CR_CH_SCC2
-
-#elif defined(CONFIG_8xx_CONS_SCC3)	/* Console on SCC3 */
-#define SCC_INDEX	2
-#define PROFF_SCC	PROFF_SCC3
-#define CPM_CR_CH_SCC	CPM_CR_CH_SCC3
-
-#elif defined(CONFIG_8xx_CONS_SCC4)	/* Console on SCC4 */
-#define SCC_INDEX	3
-#define PROFF_SCC	PROFF_SCC4
-#define CPM_CR_CH_SCC	CPM_CR_CH_SCC4
-
-#endif /* CONFIG_8xx_CONS_SCCx */
-
-static void serial_setdivisor(volatile cpm8xx_t *cp)
-{
-	int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
-
-	if(divisor/16>0x1000) {
-		/* bad divisor, assume 50Mhz clock and 9600 baud */
-		divisor=(50*1000*1000 + 8*9600)/16/9600;
-	}
-
-#ifdef CFG_BRGCLK_PRESCALE
-	divisor /= CFG_BRGCLK_PRESCALE;
-#endif
-
-	if(divisor<=0x1000) {
-		cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
-	} else {
-		cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
-	}
-}
-
-#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-static void smc_setbrg (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t *cp = &(im->im_cpm);
-
-	/* Set up the baud rate generator.
-	 * See 8xx_io/commproc.c for details.
-	 *
-	 * Wire BRG1 to SMCx
-	 */
-
-	cp->cp_simode = 0x00000000;
-
-	serial_setdivisor(cp);
-}
-
-static int smc_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile smc_t *sp;
-	volatile smc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile cpm8xx_t *cp = &(im->im_cpm);
-#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
-	volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
-#endif
-	uint	dpaddr;
-
-	/* initialize pointers to SMC */
-
-	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
-	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
-
-	/* Enable SDMA.
-	*/
-	im->im_siu_conf.sc_sdcr = 1;
-
-	/* clear error conditions */
-#ifdef	CFG_SDSR
-	im->im_sdma.sdma_sdsr = CFG_SDSR;
-#else
-	im->im_sdma.sdma_sdsr = 0x83;
-#endif
-
-	/* clear SDMA interrupt mask */
-#ifdef	CFG_SDMR
-	im->im_sdma.sdma_sdmr = CFG_SDMR;
-#else
-	im->im_sdma.sdma_sdmr = 0x00;
-#endif
-
-#if defined(CONFIG_8xx_CONS_SMC1)
-	/* Use Port B for SMC1 instead of other functions.
-	*/
-	cp->cp_pbpar |=  0x000000c0;
-	cp->cp_pbdir &= ~0x000000c0;
-	cp->cp_pbodr &= ~0x000000c0;
-#else	/* CONFIG_8xx_CONS_SMC2 */
-# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
-	/* Use Port A for SMC2 instead of other functions.
-	*/
-	ip->iop_papar |=  0x00c0;
-	ip->iop_padir &= ~0x00c0;
-	ip->iop_paodr &= ~0x00c0;
-# else	/* must be a 860 then */
-	/* Use Port B for SMC2 instead of other functions.
-	*/
-	cp->cp_pbpar |=  0x00000c00;
-	cp->cp_pbdir &= ~0x00000c00;
-	cp->cp_pbodr &= ~0x00000c00;
-# endif
-#endif
-
-#if defined(CONFIG_FADS) || defined(CONFIG_ADS)
-	/* Enable RS232 */
-#if defined(CONFIG_8xx_CONS_SMC1)
-	*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
-#else
-	*((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
-#endif
-#endif	/* CONFIG_FADS */
-
-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
-	/* Enable Monitor Port Transceiver */
-	*((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
-#endif /* CONFIG_RPXLITE */
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-
-#ifdef CFG_ALLOC_DPRAM
-	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
-#else
-	dpaddr = CPM_SERIAL_BASE ;
-#endif
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * For now, this address seems OK, but it may have to
-	 * change with newer versions of the firmware.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = 0;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = 0;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->smc_rbase = dpaddr;
-	up->smc_tbase = dpaddr+sizeof(cbd_t);
-	up->smc_rfcr = SMC_EB;
-	up->smc_tfcr = SMC_EB;
-
-#if defined(CONFIG_MBX)
-	board_serial_init();
-#endif	/* CONFIG_MBX */
-
-	/* Set UART mode, 8 bit, no parity, one stop.
-	 * Enable receive and transmit.
-	 */
-	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->smc_smcm = 0;
-	sp->smc_smce = 0xff;
-
-#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
-	*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
-#else
-	/* Set up the baud rate generator */
-	smc_setbrg ();
-#endif
-
-	/* Make the first buffer the only buffer.
-	*/
-	tbdf->cbd_sc |= BD_SC_WRAP;
-	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
-
-	/* Single character receive.
-	*/
-	up->smc_mrblr = 1;
-	up->smc_maxidl = 0;
-
-	/* Initialize Tx/Rx parameters.
-	*/
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
-
-	return (0);
-}
-
-static void
-smc_putc(const char c)
-{
-	volatile cbd_t		*tbdf;
-	volatile char		*buf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
-
-	if (c == '\n')
-		smc_putc ('\r');
-
-	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
-	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
-
-	/* Wait for last character to go.
-	*/
-
-	buf = (char *)tbdf->cbd_bufaddr;
-
-	*buf = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-	__asm__("eieio");
-
-	while (tbdf->cbd_sc & BD_SC_READY) {
-		WATCHDOG_RESET ();
-		__asm__("eieio");
-	}
-}
-
-static void
-smc_puts (const char *s)
-{
-	while (*s) {
-		smc_putc (*s++);
-	}
-}
-
-static int
-smc_getc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile unsigned char	*buf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
-	unsigned char		c;
-
-	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
-	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
-
-	/* Wait for character to show up.
-	*/
-	buf = (unsigned char *)rbdf->cbd_bufaddr;
-
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		WATCHDOG_RESET ();
-
-	c = *buf;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return(c);
-}
-
-static int
-smc_tstc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
-
-	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
-	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
-
-	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
-}
-
-struct serial_device serial_smc_device =
-{
-	"serial_smc",
-	"SMC",
-	smc_init,
-	smc_setbrg,
-	smc_getc,
-	smc_tstc,
-	smc_putc,
-	smc_puts,
-};
-
-#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
-
-#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
-    defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
-
-static void
-scc_setbrg (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t *cp = &(im->im_cpm);
-
-	/* Set up the baud rate generator.
-	 * See 8xx_io/commproc.c for details.
-	 *
-	 * Wire BRG1 to SCCx
-	 */
-
-	cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
-
-	serial_setdivisor(cp);
-}
-
-static int scc_init (void)
-{
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
-	volatile scc_t *sp;
-	volatile scc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile cpm8xx_t *cp = &(im->im_cpm);
-	uint	 dpaddr;
-#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
-	volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
-#endif
-
-	/* initialize pointers to SCC */
-
-	sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
-	up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
-
-#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
-    {	/* Disable Ethernet, enable Serial */
-	uchar c;
-
-	c = pic_read  (0x61);
-	c &= ~0x40;	/* enable COM3 */
-	c |=  0x80;	/* disable Ethernet */
-	pic_write (0x61, c);
-
-	/* enable RTS2 */
-	cp->cp_pbpar |=  0x2000;
-	cp->cp_pbdat |=  0x2000;
-	cp->cp_pbdir |=  0x2000;
-    }
-#endif	/* CONFIG_LWMON */
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
-	/*
-	 * The MPC850 has SCC3 on Port B
-	 */
-	cp->cp_pbpar |=  0x06;
-	cp->cp_pbdir &= ~0x06;
-	cp->cp_pbodr &= ~0x06;
-
-#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
-	/*
-	 * Standard configuration for SCC's is on Part A
-	 */
-	ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
-	ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
-	ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
-#else
-	/*
-	 * The IP860 has SCC3 and SCC4 on Port D
-	 */
-	ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
-#endif
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 */
-
-#ifdef CFG_ALLOC_DPRAM
-	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
-#else
-	dpaddr = CPM_SERIAL2_BASE ;
-#endif
-
-	/* Enable SDMA.
-	*/
-	im->im_siu_conf.sc_sdcr = 0x0001;
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-
-	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = 0;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = 0;
-
-	/* Set up the baud rate generator.
-	*/
-	scc_setbrg ();
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->scc_genscc.scc_rbase = dpaddr;
-	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
-
-	/* Initialize Tx/Rx parameters.
-	*/
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-		;
-	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-		;
-
-	up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
-	up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
-
-	up->scc_genscc.scc_mrblr = 1;	/* Single character receive */
-	up->scc_maxidl = 0;		/* disable max idle */
-	up->scc_brkcr  = 1;		/* send one break character on stop TX */
-	up->scc_parec  = 0;
-	up->scc_frmec  = 0;
-	up->scc_nosec  = 0;
-	up->scc_brkec  = 0;
-	up->scc_uaddr1 = 0;
-	up->scc_uaddr2 = 0;
-	up->scc_toseq  = 0;
-	up->scc_char1  = 0x8000;
-	up->scc_char2  = 0x8000;
-	up->scc_char3  = 0x8000;
-	up->scc_char4  = 0x8000;
-	up->scc_char5  = 0x8000;
-	up->scc_char6  = 0x8000;
-	up->scc_char7  = 0x8000;
-	up->scc_char8  = 0x8000;
-	up->scc_rccm   = 0xc0ff;
-
-	/* Set low latency / small fifo.
-	 */
-	sp->scc_gsmrh = SCC_GSMRH_RFW;
-
-	/* Set SCC(x) clock mode to 16x
-	 * See 8xx_io/commproc.c for details.
-	 *
-	 * Wire BRG1 to SCCn
-	 */
-
-	/* Set UART mode, clock divider 16 on Tx and Rx
-	 */
-	sp->scc_gsmrl &= ~0xF;
-	sp->scc_gsmrl |=
-		(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
-
-	sp->scc_psmr  = 0;
-	sp->scc_psmr  |= SCU_PSMR_CL;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->scc_sccm = 0;
-	sp->scc_scce = 0xffff;
-	sp->scc_dsr  = 0x7e7e;
-	sp->scc_psmr = 0x3000;
-
-	/* Make the first buffer the only buffer.
-	*/
-	tbdf->cbd_sc |= BD_SC_WRAP;
-	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-	return (0);
-}
-
-static void
-scc_putc(const char c)
-{
-	volatile cbd_t		*tbdf;
-	volatile char		*buf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
-
-	if (c == '\n')
-		scc_putc ('\r');
-
-	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
-
-	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
-
-	/* Wait for last character to go.
-	*/
-
-	buf = (char *)tbdf->cbd_bufaddr;
-
-	*buf = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-	__asm__("eieio");
-
-	while (tbdf->cbd_sc & BD_SC_READY) {
-		__asm__("eieio");
-		WATCHDOG_RESET ();
-	}
-}
-
-static void
-scc_puts (const char *s)
-{
-	while (*s) {
-		scc_putc (*s++);
-	}
-}
-
-static int
-scc_getc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile unsigned char	*buf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
-	unsigned char		c;
-
-	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
-
-	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
-
-	/* Wait for character to show up.
-	*/
-	buf = (unsigned char *)rbdf->cbd_bufaddr;
-
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		WATCHDOG_RESET ();
-
-	c = *buf;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return(c);
-}
-
-static int
-scc_tstc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
-	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
-
-	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
-
-	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
-
-	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
-}
-
-struct serial_device serial_scc_device =
-{
-	"serial_scc",
-	"SCC",
-	scc_init,
-	scc_setbrg,
-	scc_getc,
-	scc_tstc,
-	scc_putc,
-	scc_puts,
-};
-
-#endif	/* CONFIG_8xx_CONS_SCCx */
-
-void enable_putc(void)
-{
-	gd->be_quiet = 0;
-}
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-
-void
-kgdb_serial_init(void)
-{
-	int i = -1;
-
-	if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
-	{
-#if defined(CONFIG_8xx_CONS_SMC1)
-		i = 1;
-#elif defined(CONFIG_8xx_CONS_SMC2)
-		i = 2;
-#endif
-	}
-	else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
-	{
-#if defined(CONFIG_8xx_CONS_SCC1)
-		i = 1;
-#elif defined(CONFIG_8xx_CONS_SCC2)
-		i = 2;
-#elif defined(CONFIG_8xx_CONS_SCC3)
-		i = 3;
-#elif defined(CONFIG_8xx_CONS_SCC4)
-		i = 4;
-#endif
-	}
-
-	if (i >= 0)
-	{
-		serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
-	}
-}
-
-void
-putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void
-putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int
-getDebugChar (void)
-{
-	return serial_getc();
-}
-
-void
-kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif	/* CFG_CMD_KGDB	*/
-
-#endif	/* CONFIG_8xx_CONS_NONE */
diff --git a/drivers/serial/serial_netarm.c b/drivers/serial/serial_netarm.c
deleted file mode 100644
index bc6bf30b69..0000000000
--- a/drivers/serial/serial_netarm.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Serial Port stuff - taken from Linux
- *
- * (C) Copyright 2002
- * MAZeT GmbH <www.mazet.de>
- * Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
- *
- * (c) 2004
- * IMMS gGmbH <www.imms.de>
- * Thomas Elste <info@elste.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-
-#ifdef CONFIG_NETARM
-
-#include <asm/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PORTA	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
-#if !defined(CONFIG_NETARM_NS7520)
-#define PORTB	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
-#else
-#define PORTC	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC))
-#endif
-
-/* wait until transmitter is ready for another character */
-#define TXWAITRDY(registers) 							\
-{										\
-	ulong tmo = get_timer(0) + 1 * CFG_HZ;					\
-	while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 )	{	\
-		if (get_timer(0) > tmo)						\
-			break;							\
-	}									\
-}
-
-
-#ifndef CONFIG_UART1_CONSOLE
-volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0);
-volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1);
-#else
-volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1);
-volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0);
-#endif
-
-extern void _netarm_led_FAIL1(void);
-
-/*
- * Setup both serial i/f with given baudrate
- */
-void serial_setbrg (void)
-{
-	/* set 0 ... make sure pins are configured for serial */
-#if !defined(CONFIG_NETARM_NS7520)
-	PORTA = PORTB =
-		NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
-#else
-	PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
-	PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
-#endif
-
-	/* first turn em off */
-	serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0;
-
-	/* clear match register, we don't need it */
-	serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0;
-
-	/* setup bit rate generator and rx buffer gap timer (1 byte only) */
-	if ((gd->baudrate >= MIN_BAUD_RATE)
-	    && (gd->baudrate <= MAX_BAUD_RATE)) {
-		serial_reg_ch1->bitrate = serial_reg_ch2->bitrate =
-			NETARM_SER_BR_X16 (gd->baudrate);
-		serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer =
-			0;
-		serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer =
-			NETARM_SER_RXGAP (gd->baudrate);
-	} else {
-		hang ();
-	}
-
-	/* setup port mode */
-	serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b =
-		( NETARM_SER_CTLB_RCGT_EN |
-		  NETARM_SER_CTLB_UART_MODE);
-	serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a =
-		( NETARM_SER_CTLA_ENABLE |
-		  NETARM_SER_CTLA_P_NONE |
-		  /* see errata */
-		  NETARM_SER_CTLA_2STOP |
-		  NETARM_SER_CTLA_8BITS |
-		  NETARM_SER_CTLA_DTR_EN |
-		  NETARM_SER_CTLA_RTS_EN);
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-	return 0;
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	volatile unsigned char *fifo;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-
-	fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo);
-	TXWAITRDY (serial_reg_ch1);
-	*fifo = c;
-}
-
-/*
- * Test of a single byte from the serial port. Returns 1 on success, 0
- * otherwise.
- */
-int serial_tstc(void)
-{
-	return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise.
- */
-int serial_getc (void)
-{
-	unsigned int ch_uint;
-	volatile unsigned int *fifo;
-	volatile unsigned char *fifo_char = NULL;
-	int buf_count = 0;
-
-	while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY))
-		/* NOP */ ;
-
-	fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo);
-	fifo_char = (unsigned char *) &ch_uint;
-	ch_uint = *fifo;
-
-	buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a);
-	switch (buf_count) {
-	case NETARM_SER_STATA_RXFDB_4BYTES:
-		buf_count = 4;
-		break;
-	case NETARM_SER_STATA_RXFDB_3BYTES:
-		buf_count = 3;
-		break;
-	case NETARM_SER_STATA_RXFDB_2BYTES:
-		buf_count = 2;
-		break;
-	case NETARM_SER_STATA_RXFDB_1BYTES:
-		buf_count = 1;
-		break;
-	default:
-		/* panic, be never here */
-		break;
-	}
-
-	serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED;
-
-	return ch_uint & 0xff;
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-#endif /* CONFIG_NETARM */
diff --git a/drivers/serial/serial_nios.c b/drivers/serial/serial_nios.c
deleted file mode 100644
index 5ecdc6d7ea..0000000000
--- a/drivers/serial/serial_nios.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <watchdog.h>
-#include <nios-io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*------------------------------------------------------------------
- * JTAG acts as the serial port
- *-----------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
-
-static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
-
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
-
-void serial_putc (char c)
-{
-	while ((jtag->txcntl & NIOS_JTAG_TRDY) != 0)
-		WATCHDOG_RESET ();
-	jtag->txcntl = NIOS_JTAG_TRDY | (unsigned char)c;
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0)
-		serial_putc (*s++);
-}
-
-int serial_tstc (void)
-{
-	return (jtag->rxcntl & NIOS_JTAG_RRDY);
-}
-
-int serial_getc (void)
-{
-	int c;
-	while (serial_tstc() == 0)
-		WATCHDOG_RESET ();
-	c = jtag->rxcntl & 0x0ff;
-	jtag->rxcntl = 0;
-	return (c);
-}
-
-/*------------------------------------------------------------------
- * UART the serial port
- *-----------------------------------------------------------------*/
-#else
-
-static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE;
-
-#if defined(CFG_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF
- * assignment
- */
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
-
-#else
-
-void serial_setbrg (void)
-{
-	unsigned div;
-
-	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
-	uart->divisor = div;
-	return;
-}
-
-int serial_init (void)
-{
-	serial_setbrg ();
-	return (0);
-}
-
-#endif /* CFG_NIOS_FIXEDBAUD */
-
-
-/*-----------------------------------------------------------------------
- * UART CONSOLE
- *---------------------------------------------------------------------*/
-void serial_putc (char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-	while ((uart->status & NIOS_UART_TRDY) == 0)
-		WATCHDOG_RESET ();
-	uart->txdata = (unsigned char)c;
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_tstc (void)
-{
-	return (uart->status & NIOS_UART_RRDY);
-}
-
-int serial_getc (void)
-{
-	while (serial_tstc () == 0)
-		WATCHDOG_RESET ();
-	return( uart->rxdata & 0x00ff );
-}
-
-#endif /* CONFIG_JTAG_CONSOLE */
diff --git a/drivers/serial/serial_nios2.c b/drivers/serial/serial_nios2.c
deleted file mode 100644
index 0bd3821e39..0000000000
--- a/drivers/serial/serial_nios2.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/io.h>
-#include <nios2-io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*------------------------------------------------------------------
- * JTAG acts as the serial port
- *-----------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
-
-static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
-
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
-
-void serial_putc (char c)
-{
-	unsigned val;
-
-	while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
-		WATCHDOG_RESET ();
-	writel (&jtag->data, (unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0)
-		serial_putc (*s++);
-}
-
-int serial_tstc (void)
-{
-	return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
-}
-
-int serial_getc (void)
-{
-	int c;
-	unsigned val;
-
-	while (1) {
-		WATCHDOG_RESET ();
-		val = readl (&jtag->data);
-		if (val & NIOS_JTAG_RVALID)
-			break;
-	}
-	c = val & 0x0ff;
-	return (c);
-}
-
-/*------------------------------------------------------------------
- * UART the serial port
- *-----------------------------------------------------------------*/
-#else
-
-static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE;
-
-#if defined(CFG_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF
- * assignment
- */
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
-
-#else
-
-void serial_setbrg (void)
-{
-	unsigned div;
-
-	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
-	writel (&uart->divisor,div);
-	return;
-}
-
-int serial_init (void)
-{
-	serial_setbrg ();
-	return (0);
-}
-
-#endif /* CFG_NIOS_FIXEDBAUD */
-
-
-/*-----------------------------------------------------------------------
- * UART CONSOLE
- *---------------------------------------------------------------------*/
-void serial_putc (char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-	while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
-		WATCHDOG_RESET ();
-	writel (&uart->txdata,(unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_tstc (void)
-{
-	return (readl (&uart->status) & NIOS_UART_RRDY);
-}
-
-int serial_getc (void)
-{
-	while (serial_tstc () == 0)
-		WATCHDOG_RESET ();
-	return (readl (&uart->rxdata) & 0x00ff );
-}
-
-#endif /* CONFIG_JTAG_CONSOLE */
diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c
deleted file mode 100644
index 417b6aeda6..0000000000
--- a/drivers/serial/serial_pl010.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
-/* Should be fairly simple to make it work with the PL010 as well */
-
-#include <common.h>
-
-#ifdef CFG_PL010_SERIAL
-
-#include "serial_pl011.h"
-
-#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
-#define IO_READ(addr) (*(volatile unsigned int *)(addr))
-
-/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */
-#define CONSOLE_PORT CONFIG_CONS_INDEX
-#define baudRate CONFIG_BAUDRATE
-static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
-#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
-
-
-static void pl010_putc (int portnum, char c);
-static int pl010_getc (int portnum);
-static int pl010_tstc (int portnum);
-
-
-int serial_init (void)
-{
-	unsigned int divisor;
-
-	/*
-	 ** First, disable everything.
-	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
-
-	/*
-	 ** Set baud rate
-	 **
-	 */
-	switch (baudRate) {
-	case 9600:
-		divisor = UART_PL010_BAUD_9600;
-		break;
-
-	case 19200:
-		divisor = UART_PL010_BAUD_9600;
-		break;
-
-	case 38400:
-		divisor = UART_PL010_BAUD_38400;
-		break;
-
-	case 57600:
-		divisor = UART_PL010_BAUD_57600;
-		break;
-
-	case 115200:
-		divisor = UART_PL010_BAUD_115200;
-		break;
-
-	default:
-		divisor = UART_PL010_BAUD_38400;
-	}
-
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
-		  ((divisor & 0xf00) >> 8));
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
-
-	/*
-	 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
-	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
-		  (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
-
-	/*
-	 ** Finally, enable the UART
-	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
-
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	if (c == '\n')
-		pl010_putc (CONSOLE_PORT, '\r');
-
-	pl010_putc (CONSOLE_PORT, c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_getc (void)
-{
-	return pl010_getc (CONSOLE_PORT);
-}
-
-int serial_tstc (void)
-{
-	return pl010_tstc (CONSOLE_PORT);
-}
-
-void serial_setbrg (void)
-{
-}
-
-static void pl010_putc (int portnum, char c)
-{
-	/* Wait until there is space in the FIFO */
-	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
-
-	/* Send the character */
-	IO_WRITE (port[portnum] + UART_PL01x_DR, c);
-}
-
-static int pl010_getc (int portnum)
-{
-	unsigned int data;
-
-	/* Wait until there is data in the FIFO */
-	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
-
-	data = IO_READ (port[portnum] + UART_PL01x_DR);
-
-	/* Check for an error flag */
-	if (data & 0xFFFFFF00) {
-		/* Clear the error */
-		IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
-		return -1;
-	}
-
-	return (int) data;
-}
-
-static int pl010_tstc (int portnum)
-{
-	return !(IO_READ (port[portnum] + UART_PL01x_FR) &
-		 UART_PL01x_FR_RXFE);
-}
-
-#endif
diff --git a/drivers/serial/serial_pl011.c b/drivers/serial/serial_pl011.c
deleted file mode 100644
index 4d35fe5e9e..0000000000
--- a/drivers/serial/serial_pl011.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
-/* Should be fairly simple to make it work with the PL010 as well */
-
-#include <common.h>
-
-#ifdef CFG_PL011_SERIAL
-
-#include "serial_pl011.h"
-
-#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
-#define IO_READ(addr) (*(volatile unsigned int *)(addr))
-
-/*
- * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1
- * Versatile PB has four UARTs.
- */
-
-#define CONSOLE_PORT CONFIG_CONS_INDEX
-#define baudRate CONFIG_BAUDRATE
-static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
-#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
-
-static void pl011_putc (int portnum, char c);
-static int pl011_getc (int portnum);
-static int pl011_tstc (int portnum);
-
-
-int serial_init (void)
-{
-	unsigned int temp;
-	unsigned int divider;
-	unsigned int remainder;
-	unsigned int fraction;
-
-	/*
-	 ** First, disable everything.
-	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
-
-	/*
-	 ** Set baud rate
-	 **
-	 ** IBRD = UART_CLK / (16 * BAUD_RATE)
-	 ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
-	 */
-	temp = 16 * baudRate;
-	divider = CONFIG_PL011_CLOCK / temp;
-	remainder = CONFIG_PL011_CLOCK % temp;
-	temp = (8 * remainder) / baudRate;
-	fraction = (temp >> 1) + (temp & 1);
-
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
-
-	/*
-	 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
-	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
-		  (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
-
-	/*
-	 ** Finally, enable the UART
-	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
-		  (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
-		   UART_PL011_CR_RXE));
-
-	return 0;
-}
-
-void serial_putc (const char c)
-{
-	if (c == '\n')
-		pl011_putc (CONSOLE_PORT, '\r');
-
-	pl011_putc (CONSOLE_PORT, c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_getc (void)
-{
-	return pl011_getc (CONSOLE_PORT);
-}
-
-int serial_tstc (void)
-{
-	return pl011_tstc (CONSOLE_PORT);
-}
-
-void serial_setbrg (void)
-{
-}
-
-static void pl011_putc (int portnum, char c)
-{
-	/* Wait until there is space in the FIFO */
-	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
-
-	/* Send the character */
-	IO_WRITE (port[portnum] + UART_PL01x_DR, c);
-}
-
-static int pl011_getc (int portnum)
-{
-	unsigned int data;
-
-	/* Wait until there is data in the FIFO */
-	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
-
-	data = IO_READ (port[portnum] + UART_PL01x_DR);
-
-	/* Check for an error flag */
-	if (data & 0xFFFFFF00) {
-		/* Clear the error */
-		IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
-		return -1;
-	}
-
-	return (int) data;
-}
-
-static int pl011_tstc (int portnum)
-{
-	return !(IO_READ (port[portnum] + UART_PL01x_FR) &
-		 UART_PL01x_FR_RXFE);
-}
-
-#endif
diff --git a/drivers/serial/serial_pl011.h b/drivers/serial/serial_pl011.h
deleted file mode 100644
index 5f20fdd108..0000000000
--- a/drivers/serial/serial_pl011.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * (C) Copyright 2003, 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * ARM PrimeCell UART's (PL010 & PL011)
- * ------------------------------------
- *
- *  Definitions common to both PL010 & PL011
- *
- */
-#define UART_PL01x_DR                   0x00	 /*  Data read or written from the interface. */
-#define UART_PL01x_RSR                  0x04	 /*  Receive status register (Read). */
-#define UART_PL01x_ECR                  0x04	 /*  Error clear register (Write). */
-#define UART_PL01x_FR                   0x18	 /*  Flag register (Read only). */
-
-#define UART_PL01x_RSR_OE               0x08
-#define UART_PL01x_RSR_BE               0x04
-#define UART_PL01x_RSR_PE               0x02
-#define UART_PL01x_RSR_FE               0x01
-
-#define UART_PL01x_FR_TXFE              0x80
-#define UART_PL01x_FR_RXFF              0x40
-#define UART_PL01x_FR_TXFF              0x20
-#define UART_PL01x_FR_RXFE              0x10
-#define UART_PL01x_FR_BUSY              0x08
-#define UART_PL01x_FR_TMSK              (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
-
-/*
- *  PL010 definitions
- *
- */
-#define UART_PL010_LCRH                 0x08	 /*  Line control register, high byte. */
-#define UART_PL010_LCRM                 0x0C	 /*  Line control register, middle byte. */
-#define UART_PL010_LCRL                 0x10	 /*  Line control register, low byte. */
-#define UART_PL010_CR                   0x14	 /*  Control register. */
-#define UART_PL010_IIR                  0x1C	 /*  Interrupt indentification register (Read). */
-#define UART_PL010_ICR                  0x1C	 /*  Interrupt clear register (Write). */
-#define UART_PL010_ILPR                 0x20	 /*  IrDA low power counter register. */
-
-#define UART_PL010_CR_LPE               (1 << 7)
-#define UART_PL010_CR_RTIE              (1 << 6)
-#define UART_PL010_CR_TIE               (1 << 5)
-#define UART_PL010_CR_RIE               (1 << 4)
-#define UART_PL010_CR_MSIE              (1 << 3)
-#define UART_PL010_CR_IIRLP             (1 << 2)
-#define UART_PL010_CR_SIREN             (1 << 1)
-#define UART_PL010_CR_UARTEN            (1 << 0)
-
-#define UART_PL010_LCRH_WLEN_8          (3 << 5)
-#define UART_PL010_LCRH_WLEN_7          (2 << 5)
-#define UART_PL010_LCRH_WLEN_6          (1 << 5)
-#define UART_PL010_LCRH_WLEN_5          (0 << 5)
-#define UART_PL010_LCRH_FEN             (1 << 4)
-#define UART_PL010_LCRH_STP2            (1 << 3)
-#define UART_PL010_LCRH_EPS             (1 << 2)
-#define UART_PL010_LCRH_PEN             (1 << 1)
-#define UART_PL010_LCRH_BRK             (1 << 0)
-
-
-#define UART_PL010_BAUD_460800            1
-#define UART_PL010_BAUD_230400            3
-#define UART_PL010_BAUD_115200            7
-#define UART_PL010_BAUD_57600             15
-#define UART_PL010_BAUD_38400             23
-#define UART_PL010_BAUD_19200             47
-#define UART_PL010_BAUD_14400             63
-#define UART_PL010_BAUD_9600              95
-#define UART_PL010_BAUD_4800              191
-#define UART_PL010_BAUD_2400              383
-#define UART_PL010_BAUD_1200              767
-/*
- *  PL011 definitions
- *
- */
-#define UART_PL011_IBRD                 0x24
-#define UART_PL011_FBRD                 0x28
-#define UART_PL011_LCRH                 0x2C
-#define UART_PL011_CR                   0x30
-#define UART_PL011_IMSC                 0x38
-#define UART_PL011_PERIPH_ID0           0xFE0
-
-#define UART_PL011_LCRH_SPS             (1 << 7)
-#define UART_PL011_LCRH_WLEN_8          (3 << 5)
-#define UART_PL011_LCRH_WLEN_7          (2 << 5)
-#define UART_PL011_LCRH_WLEN_6          (1 << 5)
-#define UART_PL011_LCRH_WLEN_5          (0 << 5)
-#define UART_PL011_LCRH_FEN             (1 << 4)
-#define UART_PL011_LCRH_STP2            (1 << 3)
-#define UART_PL011_LCRH_EPS             (1 << 2)
-#define UART_PL011_LCRH_PEN             (1 << 1)
-#define UART_PL011_LCRH_BRK             (1 << 0)
-
-#define UART_PL011_CR_CTSEN             (1 << 15)
-#define UART_PL011_CR_RTSEN             (1 << 14)
-#define UART_PL011_CR_OUT2              (1 << 13)
-#define UART_PL011_CR_OUT1              (1 << 12)
-#define UART_PL011_CR_RTS               (1 << 11)
-#define UART_PL011_CR_DTR               (1 << 10)
-#define UART_PL011_CR_RXE               (1 << 9)
-#define UART_PL011_CR_TXE               (1 << 8)
-#define UART_PL011_CR_LPE               (1 << 7)
-#define UART_PL011_CR_IIRLP             (1 << 2)
-#define UART_PL011_CR_SIREN             (1 << 1)
-#define UART_PL011_CR_UARTEN            (1 << 0)
-
-#define UART_PL011_IMSC_OEIM            (1 << 10)
-#define UART_PL011_IMSC_BEIM            (1 << 9)
-#define UART_PL011_IMSC_PEIM            (1 << 8)
-#define UART_PL011_IMSC_FEIM            (1 << 7)
-#define UART_PL011_IMSC_RTIM            (1 << 6)
-#define UART_PL011_IMSC_TXIM            (1 << 5)
-#define UART_PL011_IMSC_RXIM            (1 << 4)
-#define UART_PL011_IMSC_DSRMIM          (1 << 3)
-#define UART_PL011_IMSC_DCDMIM          (1 << 2)
-#define UART_PL011_IMSC_CTSMIM          (1 << 1)
-#define UART_PL011_IMSC_RIMIM           (1 << 0)
diff --git a/drivers/serial/serial_ppc4xx.c b/drivers/serial/serial_ppc4xx.c
deleted file mode 100644
index fab0d95006..0000000000
--- a/drivers/serial/serial_ppc4xx.c
+++ /dev/null
@@ -1,984 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/*------------------------------------------------------------------------------+ */
-/*
- * This source code has been made available to you by IBM on an AS-IS
- * basis.  Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications.  No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT   I B M   CORPORATION 1995
- * LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
- */
-/*------------------------------------------------------------------------------- */
-/*
- * Travis Sawyer 15 September 2004
- *    Added CONFIG_SERIAL_MULTI support
- */
-#include <common.h>
-#include <commproc.h>
-#include <asm/processor.h>
-#include <watchdog.h>
-#include "vecnum.h"
-
-#ifdef CONFIG_SERIAL_MULTI
-#include <serial.h>
-#endif
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-#include <malloc.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*****************************************************************************/
-#ifdef CONFIG_IOP480
-
-#define SPU_BASE         0x40000000
-
-#define spu_LineStat_rc  0x00	/* Line Status Register (Read/Clear) */
-#define spu_LineStat_w   0x04	/* Line Status Register (Set) */
-#define spu_Handshk_rc   0x08	/* Handshake Status Register (Read/Clear) */
-#define spu_Handshk_w    0x0c	/* Handshake Status Register (Set) */
-#define spu_BRateDivh    0x10	/* Baud rate divisor high */
-#define spu_BRateDivl    0x14	/* Baud rate divisor low */
-#define spu_CtlReg       0x18	/* Control Register */
-#define spu_RxCmd        0x1c	/* Rx Command Register */
-#define spu_TxCmd        0x20	/* Tx Command Register */
-#define spu_RxBuff       0x24	/* Rx data buffer */
-#define spu_TxBuff       0x24	/* Tx data buffer */
-
-/*-----------------------------------------------------------------------------+
-  | Line Status Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncLSRport1           0x40000000
-#define asyncLSRport1set        0x40000004
-#define asyncLSRDataReady             0x80
-#define asyncLSRFramingError          0x40
-#define asyncLSROverrunError          0x20
-#define asyncLSRParityError           0x10
-#define asyncLSRBreakInterrupt        0x08
-#define asyncLSRTxHoldEmpty           0x04
-#define asyncLSRTxShiftEmpty          0x02
-
-/*-----------------------------------------------------------------------------+
-  | Handshake Status Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncHSRport1           0x40000008
-#define asyncHSRport1set        0x4000000c
-#define asyncHSRDsr                   0x80
-#define asyncLSRCts                   0x40
-
-/*-----------------------------------------------------------------------------+
-  | Control Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncCRport1            0x40000018
-#define asyncCRNormal                 0x00
-#define asyncCRLoopback               0x40
-#define asyncCRAutoEcho               0x80
-#define asyncCRDtr                    0x20
-#define asyncCRRts                    0x10
-#define asyncCRWordLength7            0x00
-#define asyncCRWordLength8            0x08
-#define asyncCRParityDisable          0x00
-#define asyncCRParityEnable           0x04
-#define asyncCREvenParity             0x00
-#define asyncCROddParity              0x02
-#define asyncCRStopBitsOne            0x00
-#define asyncCRStopBitsTwo            0x01
-#define asyncCRDisableDtrRts          0x00
-
-/*-----------------------------------------------------------------------------+
-  | Receiver Command Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncRCRport1           0x4000001c
-#define asyncRCRDisable               0x00
-#define asyncRCREnable                0x80
-#define asyncRCRIntDisable            0x00
-#define asyncRCRIntEnabled            0x20
-#define asyncRCRDMACh2                0x40
-#define asyncRCRDMACh3                0x60
-#define asyncRCRErrorInt              0x10
-#define asyncRCRPauseEnable           0x08
-
-/*-----------------------------------------------------------------------------+
-  | Transmitter Command Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncTCRport1           0x40000020
-#define asyncTCRDisable               0x00
-#define asyncTCREnable                0x80
-#define asyncTCRIntDisable            0x00
-#define asyncTCRIntEnabled            0x20
-#define asyncTCRDMACh2                0x40
-#define asyncTCRDMACh3                0x60
-#define asyncTCRTxEmpty               0x10
-#define asyncTCRErrorInt              0x08
-#define asyncTCRStopPause             0x04
-#define asyncTCRBreakGen              0x02
-
-/*-----------------------------------------------------------------------------+
-  | Miscellanies defines.
-  +-----------------------------------------------------------------------------*/
-#define asyncTxBufferport1      0x40000024
-#define asyncRxBufferport1      0x40000024
-#define asyncDLABLsbport1       0x40000014
-#define asyncDLABMsbport1       0x40000010
-#define asyncXOFFchar                 0x13
-#define asyncXONchar                  0x11
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-int serial_init (void)
-{
-	volatile char val;
-	unsigned short br_reg;
-
-	br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
-	/*
-	 * Init onboard UART
-	 */
-	out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
-	out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
-	out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
-	out8 (SPU_BASE + spu_CtlReg, 0x08);	/* Set 8 bits, no parity and 1 stop bit */
-	out8 (SPU_BASE + spu_RxCmd, 0xb0);	/* Enable Rx */
-	out8 (SPU_BASE + spu_TxCmd, 0x9c);	/* Enable Tx */
-	out8 (SPU_BASE + spu_Handshk_rc, 0xff);	/* Clear Handshake */
-	val = in8 (SPU_BASE + spu_RxBuff);	/* Dummy read, to clear receiver */
-
-	return (0);
-}
-
-void serial_setbrg (void)
-{
-	unsigned short br_reg;
-
-	br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
-	out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
-	out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
-}
-
-void serial_putc (const char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-
-	/* load status from handshake register */
-	if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
-		out8 (SPU_BASE + spu_Handshk_rc, 0xff);	/* Clear Handshake */
-
-	out8 (SPU_BASE + spu_TxBuff, c);	/* Put char */
-
-	while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
-		if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
-			out8 (SPU_BASE + spu_Handshk_rc, 0xff);	/* Clear Handshake */
-	}
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_getc ()
-{
-	unsigned char status = 0;
-
-	while (1) {
-		status = in8 (asyncLSRport1);
-		if ((status & asyncLSRDataReady) != 0x0) {
-			break;
-		}
-		if ((status & ( asyncLSRFramingError |
-				asyncLSROverrunError |
-				asyncLSRParityError  |
-				asyncLSRBreakInterrupt )) != 0) {
-			(void) out8 (asyncLSRport1,
-				     asyncLSRFramingError |
-				     asyncLSROverrunError |
-				     asyncLSRParityError  |
-				     asyncLSRBreakInterrupt );
-		}
-	}
-	return (0x000000ff & (int) in8 (asyncRxBufferport1));
-}
-
-int serial_tstc ()
-{
-	unsigned char status;
-
-	status = in8 (asyncLSRport1);
-	if ((status & asyncLSRDataReady) != 0x0) {
-		return (1);
-	}
-	if ((status & ( asyncLSRFramingError |
-			asyncLSROverrunError |
-			asyncLSRParityError  |
-			asyncLSRBreakInterrupt )) != 0) {
-		(void) out8 (asyncLSRport1,
-			     asyncLSRFramingError |
-			     asyncLSROverrunError |
-			     asyncLSRParityError  |
-			     asyncLSRBreakInterrupt);
-	}
-	return 0;
-}
-
-#endif	/* CONFIG_IOP480 */
-
-/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
-    defined(CONFIG_440)
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
-#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
-#else
-#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
-#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
-#endif
-
-#if defined(CONFIG_440GP)
-#define CR0_MASK        0x3fff0000
-#define CR0_EXTCLK_ENA  0x00600000
-#define CR0_UDIV_POS    16
-#define UDIV_SUBTRACT	1
-#define UART0_SDR	cntrl0
-#define MFREG(a, d)	d = mfdcr(a)
-#define MTREG(a, d)	mtdcr(a, d)
-#else /* #if defined(CONFIG_440GP) */
-/* all other 440 PPC's access clock divider via sdr register */
-#define CR0_MASK        0xdfffffff
-#define CR0_EXTCLK_ENA  0x00800000
-#define CR0_UDIV_POS    0
-#define UDIV_SUBTRACT	0
-#define UART0_SDR	sdr_uart0
-#define UART1_SDR	sdr_uart1
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
-    defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPe)
-#define UART2_SDR	sdr_uart2
-#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
-    defined(CONFIG_440GR) || defined(CONFIG_440GRx)
-#define UART3_SDR	sdr_uart3
-#endif
-#define MFREG(a, d)	mfsdr(a, d)
-#define MTREG(a, d)	mtsdr(a, d)
-#endif /* #if defined(CONFIG_440GP) */
-#elif defined(CONFIG_405EP)
-#define UART0_BASE      0xef600300
-#define UART1_BASE      0xef600400
-#define UCR0_MASK       0x0000007f
-#define UCR1_MASK       0x00007f00
-#define UCR0_UDIV_POS   0
-#define UCR1_UDIV_POS   8
-#define UDIV_MAX        127
-#else /* CONFIG_405GP || CONFIG_405CR */
-#define UART0_BASE      0xef600300
-#define UART1_BASE      0xef600400
-#define CR0_MASK        0x00001fff
-#define CR0_EXTCLK_ENA  0x000000c0
-#define CR0_UDIV_POS    1
-#define UDIV_MAX        32
-#endif
-
-/* using serial port 0 or 1 as U-Boot console ? */
-#if defined(CONFIG_UART1_CONSOLE)
-#define ACTING_UART0_BASE	UART1_BASE
-#define ACTING_UART1_BASE	UART0_BASE
-#else
-#define ACTING_UART0_BASE	UART0_BASE
-#define ACTING_UART1_BASE	UART1_BASE
-#endif
-
-#if defined(CONFIG_SERIAL_MULTI)
-#define UART_BASE	dev_base
-#else
-#define UART_BASE	ACTING_UART0_BASE
-#endif
-
-#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on AMCC PPC405EP!"
-#endif
-
-#define UART_RBR    0x00
-#define UART_THR    0x00
-#define UART_IER    0x01
-#define UART_IIR    0x02
-#define UART_FCR    0x02
-#define UART_LCR    0x03
-#define UART_MCR    0x04
-#define UART_LSR    0x05
-#define UART_MSR    0x06
-#define UART_SCR    0x07
-#define UART_DLL    0x00
-#define UART_DLM    0x01
-
-/*-----------------------------------------------------------------------------+
-  | Line Status Register.
-  +-----------------------------------------------------------------------------*/
-/*#define asyncLSRport1           ACTING_UART0_BASE+0x05 */
-#define asyncLSRDataReady1            0x01
-#define asyncLSROverrunError1         0x02
-#define asyncLSRParityError1          0x04
-#define asyncLSRFramingError1         0x08
-#define asyncLSRBreakInterrupt1       0x10
-#define asyncLSRTxHoldEmpty1          0x20
-#define asyncLSRTxShiftEmpty1         0x40
-#define asyncLSRRxFifoError1          0x80
-
-/*-----------------------------------------------------------------------------+
-  | Miscellanies defines.
-  +-----------------------------------------------------------------------------*/
-/*#define asyncTxBufferport1      ACTING_UART0_BASE+0x00 */
-/*#define asyncRxBufferport1      ACTING_UART0_BASE+0x00 */
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-/*-----------------------------------------------------------------------------+
-  | Fifo
-  +-----------------------------------------------------------------------------*/
-typedef struct {
-	char *rx_buffer;
-	ulong rx_put;
-	ulong rx_get;
-} serial_buffer_t;
-
-volatile static serial_buffer_t buf_info;
-#endif
-
-#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
-static void serial_divs (int baudrate, unsigned long *pudiv,
-			 unsigned short *pbdiv )
-{
-	sys_info_t	sysinfo;
-	unsigned long div;		/* total divisor udiv * bdiv */
-	unsigned long umin;		/* minimum udiv	*/
-	unsigned short diff;    /* smallest diff */
-	unsigned long udiv;     /* best udiv */
-
-	unsigned short idiff;   /* current diff */
-	unsigned short ibdiv;   /* current bdiv */
-	unsigned long i;
-	unsigned long est;      /* current estimate */
-
-	get_sys_info( &sysinfo );
-
-	udiv = 32;     /* Assume lowest possible serial clk */
-	div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
-	umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
-	diff = 32;      /* highest possible */
-
-	/* i is the test udiv value -- start with the largest
-	 * possible (32) to minimize serial clock and constrain
-	 * search to umin.
-	 */
-	for( i = 32; i > umin; i-- ){
-		ibdiv = div/i;
-		est = i * ibdiv;
-		idiff = (est > div) ? (est-div) : (div-est);
-		if( idiff == 0 ){
-			udiv = i;
-			break;      /* can't do better */
-		}
-		else if( idiff < diff ){
-			udiv = i;       /* best so far */
-			diff = idiff;   /* update lowest diff*/
-		}
-	}
-
-	*pudiv = udiv;
-	*pbdiv = div/udiv;
-
-}
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_init_dev (unsigned long dev_base)
-#else
-int serial_init(void)
-#endif
-{
-	unsigned long reg;
-	unsigned long udiv;
-	unsigned short bdiv;
-	volatile char val;
-#ifdef CFG_EXT_SERIAL_CLOCK
-	unsigned long tmp;
-#endif
-
-	MFREG(UART0_SDR, reg);
-	reg &= ~CR0_MASK;
-
-#ifdef CFG_EXT_SERIAL_CLOCK
-	reg |= CR0_EXTCLK_ENA;
-	udiv = 1;
-	tmp  = gd->baudrate * 16;
-	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
-#else
-	/* For 440, the cpu clock is on divider chain A, UART on divider
-	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
-	 * values that are subject to the 1/2 opb clock constraint
-	 */
-	serial_divs (gd->baudrate, &udiv, &bdiv);
-#endif
-
-	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
-
-	/*
-	 * Configure input clock to baudrate generator for all
-	 * available serial ports here
-	 */
-	MTREG(UART0_SDR, reg);
-#if defined(UART1_SDR)
-	MTREG(UART1_SDR, reg);
-#endif
-#if defined(UART2_SDR)
-	MTREG(UART2_SDR, reg);
-#endif
-#if defined(UART3_SDR)
-	MTREG(UART3_SDR, reg);
-#endif
-
-	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8(UART_BASE + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
-	out8(UART_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8(UART_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8(UART_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8(UART_BASE + UART_LSR);	/* clear line status */
-	val = in8(UART_BASE + UART_RBR);	/* read receive buffer */
-	out8(UART_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8(UART_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-
-	return (0);
-}
-
-#else /* !defined(CONFIG_440) */
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_init_dev (unsigned long dev_base)
-#else
-int serial_init (void)
-#endif
-{
-	unsigned long reg;
-	unsigned long tmp;
-	unsigned long clk;
-	unsigned long udiv;
-	unsigned short bdiv;
-	volatile char val;
-
-#ifdef CONFIG_405EP
-	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
-	clk = gd->cpu_clk;
-	tmp = CFG_BASE_BAUD * 16;
-	udiv = (clk + tmp / 2) / tmp;
-	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
-		udiv = UDIV_MAX;
-	reg |= (udiv) << UCR0_UDIV_POS;	        /* set the UART divisor */
-	reg |= (udiv) << UCR1_UDIV_POS;	        /* set the UART divisor */
-	mtdcr (cpc0_ucr, reg);
-#else /* CONFIG_405EP */
-	reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
-	clk = CFG_EXT_SERIAL_CLOCK;
-	udiv = 1;
-	reg |= CR0_EXTCLK_ENA;
-#else
-	clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
-	udiv = 31;			/* Errata 59: stuck at 31 */
-#else
-	tmp = CFG_BASE_BAUD * 16;
-	udiv = (clk + tmp / 2) / tmp;
-	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
-		udiv = UDIV_MAX;
-#endif
-#endif
-	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
-	mtdcr (cntrl0, reg);
-#endif /* CONFIG_405EP */
-
-	tmp = gd->baudrate * udiv * 16;
-	bdiv = (clk + tmp / 2) / tmp;
-
-	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8(UART_BASE + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
-	out8(UART_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8(UART_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8(UART_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8(UART_BASE + UART_LSR);	/* clear line status */
-	val = in8(UART_BASE + UART_RBR);	/* read receive buffer */
-	out8(UART_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8(UART_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-
-	return (0);
-}
-
-#endif /* if defined(CONFIG_440) */
-
-#if defined(CONFIG_SERIAL_MULTI)
-void serial_setbrg_dev (unsigned long dev_base)
-#else
-void serial_setbrg (void)
-#endif
-{
-#if defined(CONFIG_SERIAL_MULTI)
-	serial_init_dev(dev_base);
-#else
-	serial_init();
-#endif
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-void serial_putc_dev (unsigned long dev_base, const char c)
-#else
-void serial_putc (const char c)
-#endif
-{
-	int i;
-
-	if (c == '\n')
-#if defined(CONFIG_SERIAL_MULTI)
-		serial_putc_dev (dev_base, '\r');
-#else
-		serial_putc ('\r');
-#endif
-
-	/* check THRE bit, wait for transmiter available */
-	for (i = 1; i < 3500; i++) {
-		if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
-			break;
-		udelay (100);
-	}
-	out8 (UART_BASE + UART_THR, c);	/* put character out */
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-void serial_puts_dev (unsigned long dev_base, const char *s)
-#else
-void serial_puts (const char *s)
-#endif
-{
-	while (*s) {
-#if defined(CONFIG_SERIAL_MULTI)
-		serial_putc_dev (dev_base, *s++);
-#else
-		serial_putc (*s++);
-#endif
-	}
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_getc_dev (unsigned long dev_base)
-#else
-int serial_getc (void)
-#endif
-{
-	unsigned char status = 0;
-
-	while (1) {
-#if defined(CONFIG_HW_WATCHDOG)
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-#endif	/* CONFIG_HW_WATCHDOG */
-		status = in8 (UART_BASE + UART_LSR);
-		if ((status & asyncLSRDataReady1) != 0x0) {
-			break;
-		}
-		if ((status & ( asyncLSRFramingError1 |
-				asyncLSROverrunError1 |
-				asyncLSRParityError1  |
-				asyncLSRBreakInterrupt1 )) != 0) {
-			out8 (UART_BASE + UART_LSR,
-			      asyncLSRFramingError1 |
-			      asyncLSROverrunError1 |
-			      asyncLSRParityError1  |
-			      asyncLSRBreakInterrupt1);
-		}
-	}
-	return (0x000000ff & (int) in8 (UART_BASE));
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_tstc_dev (unsigned long dev_base)
-#else
-int serial_tstc (void)
-#endif
-{
-	unsigned char status;
-
-	status = in8 (UART_BASE + UART_LSR);
-	if ((status & asyncLSRDataReady1) != 0x0) {
-		return (1);
-	}
-	if ((status & ( asyncLSRFramingError1 |
-			asyncLSROverrunError1 |
-			asyncLSRParityError1  |
-			asyncLSRBreakInterrupt1 )) != 0) {
-		out8 (UART_BASE + UART_LSR,
-		      asyncLSRFramingError1 |
-		      asyncLSROverrunError1 |
-		      asyncLSRParityError1  |
-		      asyncLSRBreakInterrupt1);
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-
-void serial_isr (void *arg)
-{
-	int space;
-	int c;
-	const int rx_get = buf_info.rx_get;
-	int rx_put = buf_info.rx_put;
-
-	if (rx_get <= rx_put) {
-		space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
-	} else {
-		space = rx_get - rx_put;
-	}
-	while (serial_tstc_dev (ACTING_UART0_BASE)) {
-		c = serial_getc_dev (ACTING_UART0_BASE);
-		if (space) {
-			buf_info.rx_buffer[rx_put++] = c;
-			space--;
-		}
-		if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
-			rx_put = 0;
-		if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
-			/* Stop flow by setting RTS inactive */
-			out8 (ACTING_UART0_BASE + UART_MCR,
-			      in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
-		}
-	}
-	buf_info.rx_put = rx_put;
-}
-
-void serial_buffered_init (void)
-{
-	serial_puts ("Switching to interrupt driven serial input mode.\n");
-	buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
-	buf_info.rx_put = 0;
-	buf_info.rx_get = 0;
-
-	if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
-		serial_puts ("Check CTS signal present on serial port: OK.\n");
-	} else {
-		serial_puts ("WARNING: CTS signal not present on serial port.\n");
-	}
-
-	irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
-			      serial_isr /*interrupt_handler_t *handler */ ,
-			      (void *) &buf_info /*void *arg */ );
-
-	/* Enable "RX Data Available" Interrupt on UART */
-	/* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
-	out8 (ACTING_UART0_BASE + UART_IER, 0x01);
-	/* Set DTR active */
-	out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
-	/* Start flow by setting RTS active */
-	out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
-	/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
-	out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
-}
-
-void serial_buffered_putc (const char c)
-{
-	/* Wait for CTS */
-#if defined(CONFIG_HW_WATCHDOG)
-	while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
-		WATCHDOG_RESET ();
-#else
-	while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
-#endif
-	serial_putc (c);
-}
-
-void serial_buffered_puts (const char *s)
-{
-	serial_puts (s);
-}
-
-int serial_buffered_getc (void)
-{
-	int space;
-	int c;
-	int rx_get = buf_info.rx_get;
-	int rx_put;
-
-#if defined(CONFIG_HW_WATCHDOG)
-	while (rx_get == buf_info.rx_put)
-		WATCHDOG_RESET ();
-#else
-	while (rx_get == buf_info.rx_put);
-#endif
-	c = buf_info.rx_buffer[rx_get++];
-	if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
-		rx_get = 0;
-	buf_info.rx_get = rx_get;
-
-	rx_put = buf_info.rx_put;
-	if (rx_get <= rx_put) {
-		space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
-	} else {
-		space = rx_get - rx_put;
-	}
-	if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
-		/* Start flow by setting RTS active */
-		out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
-	}
-
-	return c;
-}
-
-int serial_buffered_tstc (void)
-{
-	return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
-}
-
-#endif	/* CONFIG_SERIAL_SOFTWARE_FIFO */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-/*
-  AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
-  number 0 or number 1
-  - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
-  configuration has been already done
-  - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
-  configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
-*/
-#if (CONFIG_KGDB_SER_INDEX & 2)
-void kgdb_serial_init (void)
-{
-	volatile char val;
-	unsigned short br_reg;
-
-	get_clocks ();
-	br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
-		  5) / 10;
-	/*
-	 * Init onboard 16550 UART
-	 */
-	out8 (ACTING_UART1_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff));	/* set divisor for 9600 baud */
-	out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8));	/* set divisor for 9600 baud */
-	out8 (ACTING_UART1_BASE + UART_LCR, 0x03);	/* line control 8 bits no parity */
-	out8 (ACTING_UART1_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (ACTING_UART1_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (ACTING_UART1_BASE + UART_LSR);	/* clear line status */
-	val = in8 (ACTING_UART1_BASE + UART_RBR);	/* read receive buffer */
-	out8 (ACTING_UART1_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (ACTING_UART1_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-}
-
-void putDebugChar (const char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-
-	out8 (ACTING_UART1_BASE + UART_THR, c);	/* put character out */
-
-	/* check THRE bit, wait for transfer done */
-	while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
-}
-
-void putDebugStr (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int getDebugChar (void)
-{
-	unsigned char status = 0;
-
-	while (1) {
-		status = in8 (ACTING_UART1_BASE + UART_LSR);
-		if ((status & asyncLSRDataReady1) != 0x0) {
-			break;
-		}
-		if ((status & ( asyncLSRFramingError1 |
-				asyncLSROverrunError1 |
-				asyncLSRParityError1  |
-				asyncLSRBreakInterrupt1 )) != 0) {
-			out8 (ACTING_UART1_BASE + UART_LSR,
-			      asyncLSRFramingError1 |
-			      asyncLSROverrunError1 |
-			      asyncLSRParityError1  |
-			      asyncLSRBreakInterrupt1);
-		}
-	}
-	return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-
-#else	/* ! (CONFIG_KGDB_SER_INDEX & 2) */
-
-void kgdb_serial_init (void)
-{
-	serial_printf ("[on serial] ");
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif	/* (CONFIG_KGDB_SER_INDEX & 2) */
-#endif	/* CFG_CMD_KGDB */
-
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial0_init(void)
-{
-	return (serial_init_dev(UART0_BASE));
-}
-
-int serial1_init(void)
-{
-	return (serial_init_dev(UART1_BASE));
-}
-void serial0_setbrg (void)
-{
-	serial_setbrg_dev(UART0_BASE);
-}
-void serial1_setbrg (void)
-{
-	serial_setbrg_dev(UART1_BASE);
-}
-
-void serial0_putc(const char c)
-{
-	serial_putc_dev(UART0_BASE,c);
-}
-
-void serial1_putc(const char c)
-{
-	serial_putc_dev(UART1_BASE, c);
-}
-void serial0_puts(const char *s)
-{
-	serial_puts_dev(UART0_BASE, s);
-}
-
-void serial1_puts(const char *s)
-{
-	serial_puts_dev(UART1_BASE, s);
-}
-
-int serial0_getc(void)
-{
-	return(serial_getc_dev(UART0_BASE));
-}
-
-int serial1_getc(void)
-{
-	return(serial_getc_dev(UART1_BASE));
-}
-int serial0_tstc(void)
-{
-	return (serial_tstc_dev(UART0_BASE));
-}
-
-int serial1_tstc(void)
-{
-	return (serial_tstc_dev(UART1_BASE));
-}
-
-struct serial_device serial0_device =
-{
-	"serial0",
-	"UART0",
-	serial0_init,
-	serial0_setbrg,
-	serial0_getc,
-	serial0_tstc,
-	serial0_putc,
-	serial0_puts,
-};
-
-struct serial_device serial1_device =
-{
-	"serial1",
-	"UART1",
-	serial1_init,
-	serial1_setbrg,
-	serial1_getc,
-	serial1_tstc,
-	serial1_putc,
-	serial1_puts,
-};
-#endif /* CONFIG_SERIAL_MULTI */
-
-#endif	/* CONFIG_405GP || CONFIG_405CR */
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
deleted file mode 100644
index 09e036db40..0000000000
--- a/drivers/serial/serial_pxa.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/arch/pxa-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg (void)
-{
-	unsigned int quot = 0;
-
-	if (gd->baudrate == 1200)
-		quot = 768;
-	else if (gd->baudrate == 9600)
-		quot = 96;
-	else if (gd->baudrate == 19200)
-		quot = 48;
-	else if (gd->baudrate == 38400)
-		quot = 24;
-	else if (gd->baudrate == 57600)
-		quot = 16;
-	else if (gd->baudrate == 115200)
-		quot = 8;
-	else
-		hang ();
-
-#ifdef CONFIG_FFUART
-#ifdef CONFIG_CPU_MONAHANS
-	CKENA |= CKENA_22_FFUART;
-#else
-	CKEN |= CKEN6_FFUART;
-#endif /* CONFIG_CPU_MONAHANS */
-
-	FFIER = 0;					/* Disable for now */
-	FFFCR = FCR_TRFIFOE;				/* Fifos enabled */
-
-	/* set baud rate */
-	FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-	FFDLL = quot & 0xff;
-	FFDLH = quot >> 8;
-	FFLCR = LCR_WLS0 | LCR_WLS1;
-
-	FFIER = IER_UUE;			/* Enable FFUART */
-
-#elif defined(CONFIG_BTUART)
-#ifdef CONFIG_CPU_MONAHANS
-	CKENA |= CKENA_21_BTUART;
-#else
-	CKEN |= CKEN7_BTUART;
-#endif /*  CONFIG_CPU_MONAHANS */
-
-	BTIER = 0;
-	BTFCR = FCR_TRFIFOE;				/* Fifos enabled */
-
-	/* set baud rate */
-	BTLCR = LCR_DLAB;
-	BTDLL = quot & 0xff;
-	BTDLH = quot >> 8;
-	BTLCR = LCR_WLS0 | LCR_WLS1;
-
-	BTIER = IER_UUE;			/* Enable BFUART */
-
-#elif defined(CONFIG_STUART)
-#ifdef CONFIG_CPU_MONAHANS
-	CKENA |= CKENA_23_STUART;
-#else
-	CKEN |= CKEN5_STUART;
-#endif /* CONFIG_CPU_MONAHANS */
-
-	STIER = 0;
-	STFCR = 0;
-
-	/* set baud rate */
-	STLCR = LCR_DLAB;
-	STDLL = quot & 0xff;
-	STDLH = quot >> 8;
-	STLCR = LCR_WLS0 | LCR_WLS1;
-
-	STIER = IER_UUE;			/* Enable STUART */
-
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-#ifdef CONFIG_FFUART
-	/* wait for room in the tx FIFO on FFUART */
-	while ((FFLSR & LSR_TEMT) == 0)
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-	FFTHR = c;
-#elif defined(CONFIG_BTUART)
-	while ((BTLSR & LSR_TEMT ) == 0 )
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-	BTTHR = c;
-#elif defined(CONFIG_STUART)
-	while ((STLSR & LSR_TEMT ) == 0 )
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-	STTHR = c;
-#endif
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_tstc (void)
-{
-#ifdef CONFIG_FFUART
-	return FFLSR & LSR_DR;
-#elif defined(CONFIG_BTUART)
-	return BTLSR & LSR_DR;
-#elif defined(CONFIG_STUART)
-	return STLSR & LSR_DR;
-#endif
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-#ifdef CONFIG_FFUART
-	while (!(FFLSR & LSR_DR))
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-	return (char) FFRBR & 0xff;
-#elif defined(CONFIG_BTUART)
-	while (!(BTLSR & LSR_DR))
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-	return (char) BTRBR & 0xff;
-#elif defined(CONFIG_STUART)
-	while (!(STLSR & LSR_DR))
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-	return (char) STRBR & 0xff;
-#endif
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
deleted file mode 100644
index 52b07ad286..0000000000
--- a/drivers/serial/serial_s3c24x0.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
-
-#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SERIAL1
-#define UART_NR	S3C24X0_UART0
-
-#elif defined(CONFIG_SERIAL2)
-# if defined(CONFIG_TRAB)
-#  error "TRAB supports only CONFIG_SERIAL1"
-# endif
-#define UART_NR	S3C24X0_UART1
-
-#elif defined(CONFIG_SERIAL3)
-# if defined(CONFIG_TRAB)
-#  #error "TRAB supports only CONFIG_SERIAL1"
-# endif
-#define UART_NR	S3C24X0_UART2
-
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-
-void serial_setbrg (void)
-{
-	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
-	int i;
-	unsigned int reg = 0;
-
-	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
-	reg = get_PCLK() / (16 * gd->baudrate) - 1;
-
-	/* FIFO enable, Tx/Rx FIFO clear */
-	uart->UFCON = 0x07;
-	uart->UMCON = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	uart->ULCON = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	uart->UCON = 0x245;
-	uart->UBRDIV = reg;
-
-#ifdef CONFIG_HWFLOW
-	uart->UMCON = 0x1; /* RTS up */
-#endif
-	for (i = 0; i < 100; i++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
-
-	/* wait for character to arrive */
-	while (!(uart->UTRSTAT & 0x1));
-
-	return uart->URXH & 0xff;
-}
-
-#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
-int hwflow_onoff(int on)
-{
-	switch(on) {
-	case 0:
-	default:
-		break; /* return current */
-	case 1:
-		hwflow = 1; /* turn on */
-		break;
-	case -1:
-		hwflow = 0; /* turn off */
-		break;
-	}
-	return hwflow;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
-
-	/* wait for room in the tx FIFO */
-	while (!(uart->UTRSTAT & 0x2));
-
-#ifdef CONFIG_HWFLOW
-	/* Wait for CTS up */
-	while(hwflow && !(uart->UMSTAT & 0x1))
-		;
-#endif
-
-	uart->UTXH = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc (void)
-{
-	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
-
-	return uart->UTRSTAT & 0x1;
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c
deleted file mode 100644
index 95d0266c6c..0000000000
--- a/drivers/serial/serial_s3c44b0.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* flush serial input queue. returns 0 on success or negative error
- * number otherwise
- */
-static int serial_flush_input(void)
-{
-	volatile u32 tmp;
-
-	/* keep on reading as long as the receiver is not empty */
-	while(UTRSTAT0&0x01) {
-		tmp = REGB(URXH0);
-	}
-
-	return 0;
-}
-
-
-/* flush output queue. returns 0 on success or negative error number
- * otherwise
- */
-static int serial_flush_output(void)
-{
-	/* wait until the transmitter is no longer busy */
-	while(!(UTRSTAT0 & 0x02)) {
-	}
-
-	return 0;
-}
-
-
-void serial_setbrg (void)
-{
-	u32 divisor = 0;
-
-	/* get correct divisor */
-	switch(gd->baudrate) {
-
-	case 1200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-		divisor = 3124;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-		divisor = 3905;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-		break;
-
-	case 9600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-		divisor = 390;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-		divisor = 487;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-		break;
-
-	case 19200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-		divisor = 194;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-		divisor = 243;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-		break;
-
-	case 38400:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-		divisor = 97;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-		divisor = 121;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif	/* break; */
-
-	case 57600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-		divisor = 64;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-		divisor = 80;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif	/* break; */
-
-	case 115200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-		divisor = 32;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-		divisor = 40;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif	/* break; */
-	}
-
-	serial_flush_output();
-	serial_flush_input();
-	UFCON0 = 0x0;
-	ULCON0 = 0x03;
-	UCON0 = 0x05;
-	UBRDIV0 = divisor;
-
-	UFCON1 = 0x0;
-	ULCON1 = 0x03;
-	UCON1 = 0x05;
-	UBRDIV1 = divisor;
-
-	for(divisor=0; divisor<100; divisor++) {
-		/* NOP */
-	}
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	/* wait for room in the transmit FIFO */
-	while(!(UTRSTAT0 & 0x02));
-
-	UTXH0 = (unsigned char)c;
-
-	/*
-		to be polite with serial console add a line feed
-		to the carriage return character
-	*/
-	if (c=='\n')
-		serial_putc('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_tstc (void)
-{
-	return (UTRSTAT0 & 0x01);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	int rv;
-
-	for(;;) {
-		rv = serial_tstc();
-
-		if(rv > 0)
-			return URXH0;
-	}
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/drivers/serial/serial_sa1100.c b/drivers/serial/serial_sa1100.c
deleted file mode 100644
index 5d1887580d..0000000000
--- a/drivers/serial/serial_sa1100.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <SA-1100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg (void)
-{
-	unsigned int reg = 0;
-
-	if (gd->baudrate == 1200)
-		reg = 191;
-	else if (gd->baudrate == 9600)
-		reg = 23;
-	else if (gd->baudrate == 19200)
-		reg = 11;
-	else if (gd->baudrate == 38400)
-		reg = 5;
-	else if (gd->baudrate == 57600)
-		reg = 3;
-	else if (gd->baudrate == 115200)
-		reg = 1;
-	else
-		hang ();
-
-#ifdef CONFIG_SERIAL1
-	/* SA1110 uart function */
-	Ser1SDCR0 |= SDCR0_SUS;
-
-	/* Wait until port is ready ... */
-	while(Ser1UTSR1 & UTSR1_TBY) {}
-
-	/* init serial serial 1 */
-	Ser1UTCR3 = 0x00;
-	Ser1UTSR0 = 0xff;
-	Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData );
-	Ser1UTCR1 = 0;
-	Ser1UTCR2 = (u32)reg;
-	Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE );
-#elif defined(CONFIG_SERIAL3)
-	/* Wait until port is ready ... */
-	while (Ser3UTSR1 & UTSR1_TBY) {
-	}
-
-	/* init serial serial 3 */
-	Ser3UTCR3 = 0x00;
-	Ser3UTSR0 = 0xff;
-	Ser3UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData);
-	Ser3UTCR1 = 0;
-	Ser3UTCR2 = (u32) reg;
-	Ser3UTCR3 = (UTCR3_RXE | UTCR3_TXE);
-#else
-#error "Bad: you didn't configured serial ..."
-#endif
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-#ifdef CONFIG_SERIAL1
-	/* wait for room in the tx FIFO on SERIAL1 */
-	while ((Ser1UTSR0 & UTSR0_TFS) == 0);
-
-	Ser1UTDR = c;
-#elif defined(CONFIG_SERIAL3)
-	/* wait for room in the tx FIFO on SERIAL3 */
-	while ((Ser3UTSR0 & UTSR0_TFS) == 0);
-
-	Ser3UTDR = c;
-#endif
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_tstc (void)
-{
-#ifdef CONFIG_SERIAL1
-	return Ser1UTSR1 & UTSR1_RNE;
-#elif defined(CONFIG_SERIAL3)
-	return Ser3UTSR1 & UTSR1_RNE;
-#endif
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-#ifdef CONFIG_SERIAL1
-	while (!(Ser1UTSR1 & UTSR1_RNE));
-
-	return (char) Ser1UTDR & 0xff;
-#elif defined(CONFIG_SERIAL3)
-	while (!(Ser3UTSR1 & UTSR1_RNE));
-
-	return (char) Ser3UTDR & 0xff;
-#endif
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
deleted file mode 100644
index ed59abea86..0000000000
--- a/drivers/serial/serial_xuartlite.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#ifdef	CONFIG_MICROBLAZE
-
-#include <asm/serial_xuartlite.h>
-
-/* FIXME: we should convert these to in32 and out32 */
-#define IO_WORD(offset)	     (*(volatile unsigned long *)(offset))
-#define IO_SERIAL(offset)    IO_WORD(CONFIG_SERIAL_BASE + (offset))
-
-#define IO_SERIAL_RX_FIFO   IO_SERIAL(XUL_RX_FIFO_OFFSET)
-#define IO_SERIAL_TX_FIFO   IO_SERIAL(XUL_TX_FIFO_OFFSET)
-#define IO_SERIAL_STATUS    IO_SERIAL(XUL_STATUS_REG_OFFSET)
-#define IO_SERIAL_CONTROL   IO_SERIAL(XUL_CONTROL_REG_OFFSET)
-
-int serial_init(void)
-{
-	/* FIXME: Nothing for now. We should initialize fifo, etc */
-	return 0;
-}
-
-void serial_setbrg(void)
-{
-	/* FIXME: what's this for? */
-}
-
-void serial_putc(const char c)
-{
-	if (c == '\n') serial_putc('\r');
-	while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL);
-	IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff);
-}
-
-void serial_puts(const char * s)
-{
-	while (*s) {
-		serial_putc(*s++);
-	}
-}
-
-int serial_getc(void)
-{
-	while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA));
-	return IO_SERIAL_RX_FIFO & 0xff;
-}
-
-int serial_tstc(void)
-{
-	return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA);
-}
-
-#endif	/* CONFIG_MICROBLZE */