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| author | Juergen Beisert <jbe@pengutronix.de> | 2010-10-14 21:38:45 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-10-21 22:15:36 +0200 |
| commit | 32fc00e72f698866d3bdbfa28ffef23de23178e1 (patch) | |
| tree | e745da795b4202fe4fd939ead7a78286594384a0 /drivers | |
| parent | b6a68cf1b5b4447a098690fbbe9c2b3165f0c834 (diff) | |
| download | barebox-32fc00e72f698866d3bdbfa28ffef23de23178e1.tar.gz barebox-32fc00e72f698866d3bdbfa28ffef23de23178e1.tar.xz | |
Make the clock calculation easier to read and correct
Due to a wrong rounding while calculating the clock divider the requested clock
of 25 MHz resulted into a 48 MHz clock. With this patch a clock frequency
below or equal the requested one will be set.
By using 'div' and 'rate' as vars, its also easier to check against the data
sheet.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mci/stm378x.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/mci/stm378x.c b/drivers/mci/stm378x.c index fbb9994b6e..13e8006855 100644 --- a/drivers/mci/stm378x.c +++ b/drivers/mci/stm378x.c @@ -474,7 +474,7 @@ static int stm_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd, */ static unsigned setup_clock_speed(struct device_d *hw_dev, unsigned nc) { - unsigned ssp, div1, div2, reg; + unsigned ssp, div, rate, reg; if (nc == 0U) { /* TODO stop the clock */ @@ -483,21 +483,21 @@ static unsigned setup_clock_speed(struct device_d *hw_dev, unsigned nc) ssp = imx_get_sspclk() * 1000; - for (div1 = 2; div1 < 255; div1 += 2) { - div2 = ssp / nc / div1; - if (div2 <= 0x100) + for (div = 2; div < 255; div += 2) { + rate = (((ssp + (nc >> 1) ) / nc) + (div >> 1)) / div; + if (rate <= 0x100) break; } - if (div1 >= 255) { + if (div >= 255) { pr_warning("Cannot set clock to %d Hz\n", nc); return 0; } reg = readl(hw_dev->map_base + HW_SSP_TIMING) & SSP_TIMING_TIMEOUT_MASK; - reg |= SSP_TIMING_CLOCK_DIVIDE(div1) | SSP_TIMING_CLOCK_RATE(div2 - 1); + reg |= SSP_TIMING_CLOCK_DIVIDE(div) | SSP_TIMING_CLOCK_RATE(rate - 1); writel(reg, hw_dev->map_base + HW_SSP_TIMING); - return ssp / div1 / div2; + return ssp / div / rate; } /** |