diff options
| author | Michael Grzeschik <m.grzeschik@pengutronix.de> | 2010-08-06 14:36:08 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-08-06 19:18:59 +0200 |
| commit | 6937c9193518581d32ea79823a67b1bfb2d35ae1 (patch) | |
| tree | 9586caf4ce1f3a27fe87218cb49a74ed0f492991 /drivers | |
| parent | 877c9335d79d228f2cce42c44aa46b50f00f3372 (diff) | |
| download | barebox-6937c9193518581d32ea79823a67b1bfb2d35ae1.tar.gz barebox-6937c9193518581d32ea79823a67b1bfb2d35ae1.tar.xz | |
omap nand: bugfix configure ecc order
This repairs a bug which came with patch "0cb00c1 omap nand: cleanup"
We first have to set ecc.layout before we can use it and should
do the nand_scan_tail after we set the ecc.mode.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/nand_omap_gpmc.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c index 1363808ce0..aef682043d 100644 --- a/drivers/mtd/nand/nand_omap_gpmc.c +++ b/drivers/mtd/nand/nand_omap_gpmc.c @@ -498,24 +498,6 @@ static int gpmc_nand_probe(struct device_d *pdev) /* State my controller */ nand->controller = &oinfo->controller; - if (pdata->plat_options & NAND_HWECC_ENABLE) { - /* Program how many columns we expect+ - * enable the cs we want and enable the engine - */ - oinfo->ecc_config = (pdata->cs << 1) | - ((nand->options & NAND_BUSWIDTH_16) ? - (0x1 << 7) : 0x0) | 0x1; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.calculate = omap_calculate_ecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.steps = nand->ecc.layout->eccbytes / nand->ecc.bytes; - oinfo->ecc_parity_pairs = 12; - } else - nand->ecc.mode = NAND_ECC_SOFT; - /* All information is ready.. now lets call setup, if present */ if (pdata->nand_setup) { err = pdata->nand_setup(pdata); @@ -566,15 +548,33 @@ static int gpmc_nand_probe(struct device_d *pdev) goto out_release_mem; } + if (pdata->plat_options & NAND_HWECC_ENABLE) + nand->ecc.layout = layout; + + if (pdata->plat_options & NAND_HWECC_ENABLE) { + /* Program how many columns we expect+ + * enable the cs we want and enable the engine + */ + oinfo->ecc_config = (pdata->cs << 1) | + ((nand->options & NAND_BUSWIDTH_16) ? + (0x1 << 7) : 0x0) | 0x1; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = nand->ecc.layout->eccbytes / nand->ecc.bytes; + oinfo->ecc_parity_pairs = 12; + } else + nand->ecc.mode = NAND_ECC_SOFT; + /* second phase scan */ if (nand_scan_tail(minfo)) { err = -ENXIO; goto out_release_mem; } - if (pdata->plat_options & NAND_HWECC_ENABLE) - nand->ecc.layout = layout; - /* We are all set to register with the system now! */ err = add_mtd_device(minfo); if (err) { |