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author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2017-06-19 07:40:38 -0700 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-21 08:33:28 +0200 |
commit | cbff8031b491bf61673966e12f632300a17da470 (patch) | |
tree | 6febe9217676b3642c3e7890f4b3f03344afbff9 /drivers | |
parent | 5804dbe1599d8897d09703755b9bfa5bf779464a (diff) | |
download | barebox-cbff8031b491bf61673966e12f632300a17da470.tar.gz barebox-cbff8031b491bf61673966e12f632300a17da470.tar.xz |
i.MX: clk-pllv3: Do not touch PLL_BYPASS bit
Do not touch PLL_BYPASS bit as a part of clk_pll3_enable/disable
execution. For a number of platforms (e.g. Vybrid, i.MX6SL) PLL_BYPASS
is specified as a bit controlling a clock MUX represented by a
dedicated 'struct clk'. Altering that bit as a part of
clk_pll3_enable/disable is equivalent to calling clk_set_parent() and
it makes in the following code:
clk_enable(clk_disable(<some pll>))
change clock chain instead of being a no-op.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/imx/clk-pllv3.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 6d4399b9b3..a14d36e565 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -56,7 +56,6 @@ static int clk_pllv3_enable(struct clk *clk) int timeout = 10000; val = readl(pll->base); - val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= pll->power_bit; else @@ -88,7 +87,6 @@ static void clk_pllv3_disable(struct clk *clk) val &= ~BM_PLL_ENABLE; writel(val, pll->base); - val |= BM_PLL_BYPASS; if (pll->powerup_set) val &= ~pll->power_bit; else |