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author | Lucas Stach <l.stach@pengutronix.de> | 2020-11-05 15:10:14 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-09 08:44:55 +0100 |
commit | 61682b59363fca0fbf51d37ece46ec6d47ea35d4 (patch) | |
tree | a6c7caa2bee20a60072e50a6bd99e7ca743b393c /drivers | |
parent | 33f25eb1908b8b3e3c56a0bb2a24376a2735833a (diff) | |
download | barebox-61682b59363fca0fbf51d37ece46ec6d47ea35d4.tar.gz barebox-61682b59363fca0fbf51d37ece46ec6d47ea35d4.tar.xz |
ddr: imx8m: clean up entry points
The DDRC address in the memory map and the TF-A parameter store address
is the same for all i.MX8M* SoCs. The only difference (for now) is in the
power up sequence. Add a enum for the DDRC type, so we can take different
code paths in imx8m_ddr_init() depending on the SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/ddr/imx8m/ddr_init.c | 82 |
1 files changed, 37 insertions, 45 deletions
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index bc64e7c17e..230fa7ef42 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -13,8 +13,6 @@ #include <mach/imx8m-regs.h> #include <mach/imx8m-ccm-regs.h> -#define SRC_DDRC_RCR_ADDR MX8MQ_SRC_DDRC_RCR_ADDR - static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) { int i = 0; @@ -25,14 +23,37 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) } } -static int imx8m_ddr_init(unsigned long src_ddrc_rcr, - struct dram_timing_info *dram_timing) +/* + * We store the timing parameters here. the TF-A will pick these up. + * Note that the timing used we leave the driver with is a PLL bypass 25MHz + * mode. So if your board runs horribly slow you'll likely have to provide a + * TF-A binary. + */ +#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 + +static int imx8m_ddr_init(struct dram_timing_info *dram_timing, + enum ddrc_type type) { + unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; unsigned int tmp, initial_drate, target_freq; int ret; pr_debug("start DRAM init\n"); + /* Step1: Follow the power up procedure */ + switch (type) { + case DDRC_TYPE_MQ: + reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); + reg32_write(src_ddrc_rcr, 0x8f00000f); + reg32_write(src_ddrc_rcr + 0x04, 0x8f000000); + break; + case DDRC_TYPE_MM: + case DDRC_TYPE_MP: + reg32_write(src_ddrc_rcr, 0x8f00001f); + reg32_write(src_ddrc_rcr, 0x8f00000f); + break; + } + pr_debug("cfg clk\n"); /* disable iso */ @@ -44,7 +65,7 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr, ddrphy_init_set_dfi_clk(initial_drate); /* D-aasert the presetn */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + reg32_write(src_ddrc_rcr, 0x8F000006); /* Step2: Program the dwc_ddr_umctl2 registers */ pr_debug("ddrc config start\n"); @@ -52,8 +73,8 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr, pr_debug("ddrc config done\n"); /* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + reg32_write(src_ddrc_rcr, 0x8F000004); + reg32_write(src_ddrc_rcr, 0x8F000000); /* * Step4: Disable auto-refreshes, self-refresh, powerdown, and @@ -162,52 +183,23 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr, reg32_write(DDRC_PCTRL_0(0), 0x00000001); pr_debug(" ddrmix config done\n"); + /* save the dram timing config into memory */ + dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); + return 0; } -/* - * We store the timing parameters here. the TF-A will pick these up. - * Note that the timing used we leave the driver with is a PLL bypass 25MHz - * mode. So if your board runs horribly slow you'll likely have to provide a - * TF-A binary. - */ -#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 - int imx8mm_ddr_init(struct dram_timing_info *dram_timing) { - unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; - int ret; - - /* Step1: Follow the power up procedure */ - reg32_write(src_ddrc_rcr, 0x8f00001f); - reg32_write(src_ddrc_rcr, 0x8f00000f); - - ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing); - if (ret) - return ret; - - /* save the dram timing config into memory */ - dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); - - return 0; + return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM); } int imx8mq_ddr_init(struct dram_timing_info *dram_timing) { - unsigned long src_ddrc_rcr = MX8MQ_SRC_DDRC_RCR_ADDR; - int ret; - - /* Step1: Follow the power up procedure */ - reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); - reg32_write(src_ddrc_rcr, 0x8f00000f); - reg32_write(src_ddrc_rcr + 0x04, 0x8f000000); - - ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing); - if (ret) - return ret; - - /* save the dram timing config into memory */ - dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); + return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ); +} - return 0; +int imx8mp_ddr_init(struct dram_timing_info *dram_timing) +{ + return imx8m_ddr_init(dram_timing, DDRC_TYPE_MP); } |