clk: gate: add CLK_GATE_HIWORD_MASK flag

Clock gates having the CLK_GATE_HIWORD_MASK flag set use the upper 16
bits of the register as a "write enable" mask for the value in the
lower 16 bits.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 12 insertions, 5 deletions

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 54489c4214..85eba3d23a 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -37,12 +37,19 @@ static void clk_gate_endisable(struct clk *clk, int enable)
 	u32 val;
 
 	set ^= enable;
-	val = readl(gate->reg);
 
-	if (set)
-		val |= BIT(gate->shift);
-	else
-		val &= ~BIT(gate->shift);
+	if (gate->flags & CLK_GATE_HIWORD_MASK) {
+		val = BIT(gate->shift + 16);
+		if (set)
+			val |= BIT(gate->shift);
+	} else {
+		val = readl(gate->reg);
+
+		if (set)
+			val |= BIT(gate->shift);
+		else
+			val &= ~BIT(gate->shift);
+	}
 
 	writel(val, gate->reg);
 }