diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-07-18 07:13:57 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-07-18 07:13:57 +0200 |
commit | 62c40ea9da3d03b960951d61e670ba60326536ef (patch) | |
tree | 2803a806ba6af52379ae7d107afe68c8439cd9f4 /drivers | |
parent | 33f8f53317659cd2c61dd118bfa7150f33aa30fb (diff) | |
parent | d30ef4e4bf8ebd6d8e857747647283acc0010153 (diff) | |
download | barebox-62c40ea9da3d03b960951d61e670ba60326536ef.tar.gz barebox-62c40ea9da3d03b960951d61e670ba60326536ef.tar.xz |
Merge branch 'for-next/rockchip'
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/aiodev/Kconfig | 8 | ||||
-rw-r--r-- | drivers/aiodev/Makefile | 1 | ||||
-rw-r--r-- | drivers/aiodev/rockchip_saradc.c | 197 | ||||
-rw-r--r-- | drivers/clk/clk.c | 22 | ||||
-rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 34 | ||||
-rw-r--r-- | drivers/phy/Kconfig | 1 | ||||
-rw-r--r-- | drivers/phy/Makefile | 1 | ||||
-rw-r--r-- | drivers/phy/rockchip/Kconfig | 14 | ||||
-rw-r--r-- | drivers/phy/rockchip/Makefile | 2 | ||||
-rw-r--r-- | drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 981 | ||||
-rw-r--r-- | drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 607 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-rockchip.c | 104 | ||||
-rw-r--r-- | drivers/usb/dwc3/gadget.c | 8 | ||||
-rw-r--r-- | drivers/usb/host/ehci-hcd.c | 26 |
14 files changed, 1952 insertions, 54 deletions
diff --git a/drivers/aiodev/Kconfig b/drivers/aiodev/Kconfig index 88d013aad0..03c688ae61 100644 --- a/drivers/aiodev/Kconfig +++ b/drivers/aiodev/Kconfig @@ -50,4 +50,12 @@ config STM32_ADC Support for ADC on STM32. Supports simple one-shot readings rather than continuous sampling with DMA, etc. ADC channels should be configured via device tree, using the kernel bindings. + +config ROCKCHIP_SARADC + tristate "Rockchip SARADC driver" + depends on ARCH_RK3568 || COMPILE_TEST + depends on OFDEVICE + help + Support for Successive Approximation Register (SAR) ADC in Rockchip + SoCs. endif diff --git a/drivers/aiodev/Makefile b/drivers/aiodev/Makefile index 52652f67b7..1b480f6fa3 100644 --- a/drivers/aiodev/Makefile +++ b/drivers/aiodev/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_MC13XXX_ADC) += mc13xxx_adc.o obj-$(CONFIG_QORIQ_THERMAL) += qoriq_thermal.o obj-$(CONFIG_AM335X_ADC) += am335x_adc.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o +obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o diff --git a/drivers/aiodev/rockchip_saradc.c b/drivers/aiodev/rockchip_saradc.c new file mode 100644 index 0000000000..302f73c2c3 --- /dev/null +++ b/drivers/aiodev/rockchip_saradc.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch <michael.riesch@wolfvision.net> + * + * Originally based on the Linux kernel v5.12 drivers/iio/adc/rockchip-saradc.c. + */ + +#include <common.h> +#include <aiodev.h> +#include <linux/clk.h> +#include <regulator.h> + +#define SARADC_DATA 0x00 + +#define SARADC_CTRL 0x08 +#define SARADC_CTRL_IRQ_STATUS (1 << 6) +#define SARADC_CTRL_IRQ_ENABLE (1 << 5) +#define SARADC_CTRL_POWER_CTRL (1 << 3) +#define SARADC_CTRL_CHN_MASK 0x07 + +#define SARADC_DLY_PU_SOC 0x0c + +#define SARADC_TIMEOUT_NS (100 * MSECOND) + +struct rockchip_saradc_cfg { + unsigned int num_bits; + unsigned int num_channels; +}; + +struct rockchip_saradc_data { + const struct rockchip_saradc_cfg *config; + void __iomem *base; + struct regulator *vref; + unsigned int ref_voltage_mv; + struct clk *cclk; + struct clk *pclk; + struct aiodevice aiodev; + struct aiochannel *channels; +}; + +static inline void rockchip_saradc_reg_wr(struct rockchip_saradc_data *data, + u32 value, u32 reg) +{ + writel(value, data->base + reg); +} + +static inline u32 rockchip_saradc_reg_rd(struct rockchip_saradc_data *data, + u32 reg) +{ + return readl(data->base + reg); +} + +static int rockchip_saradc_read(struct aiochannel *chan, int *val) +{ + struct rockchip_saradc_data *data; + u32 value = 0; + u32 control = 0; + u32 mask; + u64 start; + + data = container_of(chan->aiodev, struct rockchip_saradc_data, aiodev); + + rockchip_saradc_reg_wr(data, 8, SARADC_DLY_PU_SOC); + rockchip_saradc_reg_wr(data, + (chan->index & SARADC_CTRL_CHN_MASK) | + SARADC_CTRL_IRQ_ENABLE | + SARADC_CTRL_POWER_CTRL, + SARADC_CTRL); + + start = get_time_ns(); + do { + control = rockchip_saradc_reg_rd(data, SARADC_CTRL); + + if (is_timeout(start, SARADC_TIMEOUT_NS)) + return -ETIMEDOUT; + } while (!(control & SARADC_CTRL_IRQ_STATUS)); + + mask = (1 << data->config->num_bits) - 1; + value = rockchip_saradc_reg_rd(data, SARADC_DATA) & mask; + rockchip_saradc_reg_wr(data, 0, SARADC_CTRL); + + *val = (value * data->ref_voltage_mv) / mask; + + return 0; +} + +static int rockchip_saradc_probe(struct device_d *dev) +{ + struct rockchip_saradc_data *data; + int i, ret; + + data = xzalloc(sizeof(struct rockchip_saradc_data)); + + data->config = device_get_match_data(dev); + data->aiodev.hwdev = dev; + data->aiodev.read = rockchip_saradc_read; + + data->base = dev_request_mem_region(dev, 0); + if (IS_ERR(data->base)) { + ret = PTR_ERR(data->base); + goto fail_data; + } + + data->vref = regulator_get(dev, "vref"); + if (IS_ERR(data->vref)) { + dev_err(dev, "can't get vref-supply: %pe\n", data->vref); + ret = PTR_ERR(data->vref); + goto fail_data; + } + + ret = regulator_enable(data->vref); + if (ret < 0) { + dev_err(dev, "can't enable vref-supply value: %d\n", ret); + goto fail_data; + } + + ret = regulator_get_voltage(data->vref); + if (ret < 0) { + dev_warn(dev, "can't get vref-supply value: %d\n", ret); + /* use default value as fallback */ + ret = 1800000; + } + data->ref_voltage_mv = ret / 1000; + + data->cclk = clk_get(dev, "saradc"); + if (IS_ERR(data->cclk)) { + dev_err(dev, "can't get converter clock: %pe\n", data->cclk); + ret = PTR_ERR(data->cclk); + goto fail_data; + } + + ret = clk_enable(data->cclk); + if (ret < 0) { + dev_err(dev, "can't enable converter clock: %pe\n", + ERR_PTR(ret)); + goto fail_data; + } + + data->pclk = clk_get(dev, "apb_pclk"); + if (IS_ERR(data->pclk)) { + dev_err(dev, "can't get peripheral clock: %pe\n", data->pclk); + ret = PTR_ERR(data->pclk); + goto fail_data; + } + + ret = clk_enable(data->pclk); + if (ret < 0) { + dev_err(dev, "can't enable peripheral clk: %pe\n", + ERR_PTR(ret)); + goto fail_data; + } + + data->aiodev.num_channels = data->config->num_channels; + data->channels = + xzalloc(sizeof(*data->channels) * data->aiodev.num_channels); + data->aiodev.channels = xmalloc(sizeof(*data->aiodev.channels) * + data->aiodev.num_channels); + for (i = 0; i < data->aiodev.num_channels; i++) { + data->aiodev.channels[i] = &data->channels[i]; + data->channels[i].unit = "mV"; + } + + rockchip_saradc_reg_wr(data, 0, SARADC_CTRL); + + ret = aiodevice_register(&data->aiodev); + if (ret) + goto fail_channels; + + dev_info(dev, "registered as %s\n", dev_name(&data->aiodev.dev)); + return 0; + +fail_channels: + kfree(data->channels); + kfree(data->aiodev.channels); + +fail_data: + kfree(data); + return ret; +} + +static const struct rockchip_saradc_cfg rk3568_saradc_cfg = { + .num_bits = 10, + .num_channels = 8, +}; + +static const struct of_device_id of_rockchip_saradc_match[] = { + { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_cfg }, + { /* end */ } +}; + +static struct driver_d rockchip_saradc_driver = { + .name = "rockchip_saradc", + .probe = rockchip_saradc_probe, + .of_compatible = DRV_OF_COMPAT(of_rockchip_saradc_match), +}; +device_platform_driver(rockchip_saradc_driver); diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index f9e771e5ea..fff1e21144 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -525,6 +525,28 @@ int clk_parent_set_rate(struct clk_hw *hw, unsigned long rate, return clk_set_rate(clk_get_parent(clk), rate); } +int clk_name_set_parent(const char *clkname, const char *clkparentname) +{ + struct clk *clk = clk_lookup(clkname); + struct clk *parent = clk_lookup(clkparentname); + + if (IS_ERR(clk)) + return -ENOENT; + if (IS_ERR(parent)) + return -ENOENT; + return clk_set_parent(clk, parent); +} + +int clk_name_set_rate(const char *clkname, unsigned long rate) +{ + struct clk *clk = clk_lookup(clkname); + + if (IS_ERR(clk)) + return -ENOENT; + + return clk_set_rate(clk, rate); +} + #if defined(CONFIG_COMMON_CLK_OF_PROVIDER) /** * struct of_clk_provider - Clock provider registration structure diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 4605158500..40ab7ee3d7 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1619,10 +1619,19 @@ static void __init rk3568_pmu_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, ARRAY_SIZE(rk3568_clk_pmu_branches)); + rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, ARRAY_SIZE(rk3568_pmucru_critical_clocks)); rockchip_clk_of_add_provider(np, ctx); + + clk_name_set_parent("ppll", "pll_ppll"); + clk_name_set_parent("clk_rtc_32k", "clk_rtc32k_frac"); + clk_name_set_rate("clk_rtc_32k", 32768); + clk_name_set_rate("pclk_pmu", 100000000); + clk_name_set_rate("pll_ppll", 200000000); } static void __init rk3568_clk_init(struct device_node *np) @@ -1654,12 +1663,37 @@ static void __init rk3568_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3568_clk_branches, ARRAY_SIZE(rk3568_clk_branches)); + rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST); rockchip_clk_protect_critical(rk3568_cru_critical_clocks, ARRAY_SIZE(rk3568_cru_critical_clocks)); rockchip_clk_of_add_provider(np, ctx); + + clk_name_set_parent("npll", "pll_npll"); + clk_name_set_parent("vpll", "pll_vpll"); + clk_name_set_parent("pclk_bus", "gpll_100m"); + clk_name_set_parent("clk_sdmmc0", "cpll_50m"); + clk_name_set_parent("cclk_emmc", "gpll_200m"); + + clk_name_set_rate("pll_cpll", 1000000000); + clk_name_set_rate("pll_gpll", 1188000000); + clk_name_set_rate("armclk", 600000000); + clk_name_set_rate("aclk_bus", 150000000); + clk_name_set_rate("pclk_bus", 100000000); + clk_name_set_rate("aclk_top_high", 300000000); + clk_name_set_rate("aclk_top_low", 200000000); + clk_name_set_rate("hclk_top", 150000000); + clk_name_set_rate("pclk_top", 100000000); + clk_name_set_rate("aclk_perimid", 300000000); + clk_name_set_rate("hclk_perimid", 150000000); + clk_name_set_rate("pll_npll", 1200000000); + clk_name_set_rate("pll_apll", 816000000); + + clk_name_set_parent("pclk_top", "gpll_100m"); } struct clk_rk3568_inits { diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0b513b68d0..684876e260 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -23,6 +23,7 @@ config USB_NOP_XCEIV phy programming such as ISP1x04 etc. source "drivers/phy/freescale/Kconfig" +source "drivers/phy/rockchip/Kconfig" config PHY_STM32_USBPHYC tristate "STM32 USB HS PHY Controller" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 684aaed75a..f06a9df92e 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o obj-$(CONFIG_USB_NOP_XCEIV) += usb-nop-xceiv.o obj-y += freescale/ obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o +obj-y += rockchip/ diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig new file mode 100644 index 0000000000..37a514059e --- /dev/null +++ b/drivers/phy/rockchip/Kconfig @@ -0,0 +1,14 @@ +config PHY_ROCKCHIP_INNO_USB2 + bool "Rockchip INNO USB2PHY Driver" + depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OFDEVICE + depends on COMMON_CLK + help + Support for Rockchip USB2.0 PHY with Innosilicon IP block. + +config PHY_ROCKCHIP_NANENG_COMBO_PHY + bool "Rockchip NANENG COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OFDEVICE + help + Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII + combo PHY with NaNeng IP block. + diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile new file mode 100644 index 0000000000..4d75d610ef --- /dev/null +++ b/drivers/phy/rockchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c new file mode 100644 index 0000000000..bb1a5c747e --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -0,0 +1,981 @@ +/* + * Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <errno.h> +#include <driver.h> +#include <malloc.h> +#include <usb/phy.h> +#include <linux/phy/phy.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <mfd/syscon.h> +#include <regulator.h> + +#define U2PHY_BIT_WRITEABLE_SHIFT 16 +#define CHG_DCD_MAX_RETRIES 6 +#define CHG_PRI_MAX_RETRIES 2 +#define CHG_DCD_POLL_TIME 100 /* millisecond */ +#define CHG_PRIMARY_DET_TIME 40 /* millisecond */ +#define CHG_SECONDARY_DET_TIME 40 /* millisecond */ + +struct rockchip_usb2phy; + +enum power_supply_type { + POWER_SUPPLY_TYPE_UNKNOWN = 0, + POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ + POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ + POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ + POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ +}; + +enum rockchip_usb2phy_port_id { + USB2PHY_PORT_OTG, + USB2PHY_PORT_HOST, + USB2PHY_NUM_PORTS, +}; + +struct usb2phy_reg { + u32 offset; + u32 bitend; + u32 bitstart; + u32 disable; + u32 enable; +}; + +/** + * struct rockchip_chg_det_reg: usb charger detect registers + * @cp_det: charging port detected successfully. + * @dcp_det: dedicated charging port detected successfully. + * @dp_det: assert data pin connect successfully. + * @idm_sink_en: open dm sink curren. + * @idp_sink_en: open dp sink current. + * @idp_src_en: open dm source current. + * @rdm_pdwn_en: open dm pull down resistor. + * @vdm_src_en: open dm voltage source. + * @vdp_src_en: open dp voltage source. + * @opmode: utmi operational mode. + */ +struct rockchip_chg_det_reg { + struct usb2phy_reg cp_det; + struct usb2phy_reg dcp_det; + struct usb2phy_reg dp_det; + struct usb2phy_reg idm_sink_en; + struct usb2phy_reg idp_sink_en; + struct usb2phy_reg idp_src_en; + struct usb2phy_reg rdm_pdwn_en; + struct usb2phy_reg vdm_src_en; + struct usb2phy_reg vdp_src_en; + struct usb2phy_reg opmode; +}; + +/** + * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. + * @phy_sus: phy suspend register. + * @bvalid_det_en: vbus valid rise detection enable register. + * @bvalid_det_st: vbus valid rise detection status register. + * @bvalid_det_clr: vbus valid rise detection clear register. + * @ls_det_en: linestate detection enable register. + * @ls_det_st: linestate detection state register. + * @ls_det_clr: linestate detection clear register. + * @iddig_output: iddig output from grf. + * @iddig_en: utmi iddig select between grf and phy, + * 0: from phy; 1: from grf + * @idfall_det_en: id fall detection enable register. + * @idfall_det_st: id fall detection state register. + * @idfall_det_clr: id fall detection clear register. + * @idrise_det_en: id rise detection enable register. + * @idrise_det_st: id rise detection state register. + * @idrise_det_clr: id rise detection clear register. + * @utmi_avalid: utmi vbus avalid status register. + * @utmi_bvalid: utmi vbus bvalid status register. + * @utmi_iddig: otg port id pin status register. + * @utmi_ls: utmi linestate state register. + * @utmi_hstdet: utmi host disconnect register. + * @vbus_det_en: vbus detect function power down register. + */ +struct rockchip_usb2phy_port_cfg { + struct usb2phy_reg phy_sus; + struct usb2phy_reg bvalid_det_en; + struct usb2phy_reg bvalid_det_st; + struct usb2phy_reg bvalid_det_clr; + struct usb2phy_reg ls_det_en; + struct usb2phy_reg ls_det_st; + struct usb2phy_reg ls_det_clr; + struct usb2phy_reg iddig_output; + struct usb2phy_reg iddig_en; + struct usb2phy_reg idfall_det_en; + struct usb2phy_reg idfall_det_st; + struct usb2phy_reg idfall_det_clr; + struct usb2phy_reg idrise_det_en; + struct usb2phy_reg idrise_det_st; + struct usb2phy_reg idrise_det_clr; + struct usb2phy_reg utmi_avalid; + struct usb2phy_reg utmi_bvalid; + struct usb2phy_reg utmi_iddig; + struct usb2phy_reg utmi_ls; + struct usb2phy_reg utmi_hstdet; + struct usb2phy_reg vbus_det_en; +}; + +/** + * struct rockchip_usb2phy_cfg: usb-phy configuration. + * @reg: the address offset of grf for usb-phy config. + * @num_ports: specify how many ports that the phy has. + * @phy_tuning: phy default parameters tunning. + * @clkout_ctl: keep on/turn off output clk of phy. + * @chg_det: charger detection registers. + */ +struct rockchip_usb2phy_cfg { + u32 reg; + u32 num_ports; + int (*phy_tuning)(struct rockchip_usb2phy *); + struct usb2phy_reg clkout_ctl; + const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; + const struct rockchip_chg_det_reg chg_det; +}; + +struct rockchip_usb2phy_phy { + struct phy *phy; + struct regulator *vbus; + struct rockchip_usb2phy *usb2phy; + const struct rockchip_usb2phy_port_cfg *port_cfg; +}; + +/** + * @dcd_retries: The retry count used to track Data contact + * detection process. + * @primary_retries: The retry count used to do usb bc detection + * primary stage. + * @grf: General Register Files register base. + * @usbgrf_base : USB General Register Files register base. + * @phy_cfg: phy register configuration, assigned by driver data. + */ +struct rockchip_usb2phy { + u8 dcd_retries; + u8 primary_retries; + struct regmap *grf_base; + const struct rockchip_usb2phy_cfg *phy_cfg; + struct rockchip_usb2phy_phy phys[2]; + struct phy_provider *provider; + struct clk *clk480m; + struct clk_hw clk480m_hw; + struct device_d *dev; + struct clk *clk; +}; + +static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) +{ + return rphy->grf_base; +} + +static inline int property_enable(struct regmap *base, + const struct usb2phy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static inline bool property_enabled(struct regmap *base, + const struct usb2phy_reg *reg) +{ + u32 tmp, orig; + u32 mask = GENMASK(reg->bitend, reg->bitstart); + + regmap_read(base, reg->offset, &orig); + + tmp = (orig & mask) >> reg->bitstart; + + return tmp == reg->enable; +} + +static int rockchip_usb2phy_init(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + struct rockchip_usb2phy *rphy = p->usb2phy; + struct regmap *base = get_reg_base(rphy); + + p->vbus = regulator_get(&phy->dev, "vbus"); + + property_enable(base, &p->port_cfg->phy_sus, false); + + /* waiting for the utmi_clk to become stable */ + udelay(2000); + + return 0; +} + +static int rockchip_usb2phy_exit(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + struct rockchip_usb2phy *rphy = p->usb2phy; + struct regmap *base = get_reg_base(rphy); + + property_enable(base, &p->port_cfg->phy_sus, true); + + return 0; +} + +static int rockchip_usb2phy_power_on(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + int ret; + + ret = regulator_enable(p->vbus); + if (ret) { + dev_err(&phy->dev, "Failed to enable VBus supply\n"); + return ret; + } + + return 0; +} + +static int rockchip_usb2phy_power_off(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + int ret; + + ret = regulator_disable(p->vbus); + if (ret) { + dev_err(&phy->dev, "Failed to disable VBus supply\n"); + return ret; + } + + return 0; +} + +static struct phy *rockchip_usb2phy_of_xlate(struct device_d *dev, + struct of_phandle_args *args) +{ + struct rockchip_usb2phy *rphy = dev->priv; + struct device_node *phynode = args->np; + struct rockchip_usb2phy_phy *p; + int port; + + for (port = 0; port < 2; port++) { + if (phynode == rphy->phys[port].phy->dev.device_node) { + p = &rphy->phys[port]; + return p->phy; + } + } + + return NULL; +} + +static struct phy_ops rockchip_usb2phy_ops = { + .init = rockchip_usb2phy_init, + .exit = rockchip_usb2phy_exit, + .power_on = rockchip_usb2phy_power_on, + .power_off = rockchip_usb2phy_power_off, +}; + +static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) +{ + struct rockchip_usb2phy *rphy = + container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); + int ret; + + /* turn on 480m clk output if it is off */ + if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { + ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); + if (ret) + return ret; + + /* waiting for the clk become stable */ + udelay(1200); + } + + return 0; +} + +static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) +{ + struct rockchip_usb2phy *rphy = + container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); + + /* turn off 480m clk output */ + property_enable(base, &rphy->phy_cfg->clkout_ctl, false); +} + +static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) +{ + struct rockchip_usb2phy *rphy = + container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); + + return property_enabled(base, &rphy->phy_cfg->clkout_ctl); +} + +static unsigned long +rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 480000000; +} + +static const struct clk_ops rockchip_usb2phy_clkout_ops = { + .enable = rockchip_usb2phy_clk480m_prepare, + .disable = rockchip_usb2phy_clk480m_unprepare, + .is_enabled = rockchip_usb2phy_clk480m_prepared, + .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, +}; + +static int rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) +{ + struct device_node *node = rphy->dev->device_node; + struct clk_init_data init = {}; + const char *clk_name; + int ret; + + init.flags = 0; + init.name = "clk_usbphy_480m"; + init.ops = &rockchip_usb2phy_clkout_ops; + + /* optional override of the clockname */ + of_property_read_string(node, "clock-output-names", &init.name); + + if (rphy->clk) { + clk_name = __clk_get_name(rphy->clk); + init.parent_names = &clk_name; + init.num_parents = 1; + } else { + init.parent_names = NULL; + init.num_parents = 0; + } + + rphy->clk480m_hw.init = &init; + + rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); + if (IS_ERR(rphy->clk480m)) { + ret = PTR_ERR(rphy->clk480m); + goto err_ret; + } + + ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); + if (ret < 0) + goto err_clk_provider; + + return 0; + +err_clk_provider: + clk_unregister(rphy->clk480m); +err_ret: + return ret; +} + +static int rockchip_usb2phy_probe(struct device_d *dev) +{ + const struct rockchip_usb2phy_cfg *phy_cfgs; + struct rockchip_usb2phy *rphy; + u32 reg, index; + int ret, port = 0; + struct device_node *child, *np = dev->device_node; + struct resource *iores; + + rphy = xzalloc(sizeof(*rphy)); + + rphy->dev = dev; + + rphy->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); + if (IS_ERR(rphy->grf_base)) + return PTR_ERR(rphy->grf_base); + + phy_cfgs = device_get_match_data(dev); + if (!phy_cfgs) + return -EINVAL; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + if (of_property_read_u32(np, "reg", ®)) + return -EINVAL; + } else { + reg = iores->start; + } + + /* find out a proper config which can be matched with dt. */ + index = 0; + while (phy_cfgs[index].reg) { + if (phy_cfgs[index].reg == reg) { + rphy->phy_cfg = &phy_cfgs[index]; + break; + } + ++index; + } + + if (!rphy->phy_cfg) { + dev_err(dev, "no phy-config can be matched\n"); + return -EINVAL; + } + + for_each_child_of_node(np, child) { + struct rockchip_usb2phy_phy *p; + struct phy *phy; + + if (!strcmp(child->name, "host-port")) { + port = USB2PHY_PORT_OTG; + } else if (!strcmp(child->name, "otg-port")) { + port = USB2PHY_PORT_HOST; + } else { + dev_warn(dev, "Ignoring unknown subnode %s\n", child->name); + continue; + } + + if (rphy->phys[port].phy) + return -EINVAL; + + phy = phy_create(dev, child, &rockchip_usb2phy_ops); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to create phy%d: %d\n", + port, ret); + return ret; + } + + p = xzalloc(sizeof(*p)); + + phy_set_drvdata(phy, p); + p->usb2phy = rphy; + p->port_cfg = &phy_cfgs->port_cfgs[port]; + + rphy->phys[port].phy = phy; + } + + if (rphy->phy_cfg->phy_tuning) + rphy->phy_cfg->phy_tuning(rphy); + + dev->priv = rphy; + + rphy->clk = clk_get(dev, "phyclk"); + rockchip_usb2phy_clk480m_register(rphy); + + rphy->provider = of_phy_provider_register(dev, rockchip_usb2phy_of_xlate); + if (IS_ERR(rphy->provider)) + return PTR_ERR(rphy->provider); + + return 0; +} + +static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + struct regmap *base = get_reg_base(rphy); + int ret = 0; + + /* Open pre-emphasize in non-chirp state for PHY0 otg port */ + if (rphy->phy_cfg->reg == 0x760) + ret = regmap_write(base, 0x76c, 0x00070004); + + return ret; +} + +static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .iddig_output = { 0x0100, 10, 10, 0, 1 }, + .iddig_en = { 0x0100, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x110, 1, 1, 0, 1 }, + .ls_det_st = { 0x114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x118, 1, 1, 0, 1 }, + .utmi_ls = { 0x120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0100, 3, 0, 5, 1 }, + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { + { + .reg = 0x17c, + .num_ports = 2, + .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, + .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, + .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, + .iddig_output = { 0x017c, 10, 10, 0, 1 }, + .iddig_en = { 0x017c, 9, 9, 0, 1 }, + .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, + .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, + .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, + .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, + .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, + .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, + .ls_det_en = { 0x017c, 12, 12, 0, 1 }, + .ls_det_st = { 0x017c, 13, 13, 0, 1 }, + .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, + .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, + .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, + .utmi_ls = { 0x014c, 7, 6, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0194, 14, 14, 0, 1 }, + .ls_det_st = { 0x0194, 15, 15, 0, 1 }, + .ls_det_clr = { 0x0194, 15, 15, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x017c, 3, 0, 5, 1 }, + .cp_det = { 0x02c0, 6, 6, 0, 1 }, + .dcp_det = { 0x02c0, 5, 5, 0, 1 }, + .dp_det = { 0x02c0, 7, 7, 0, 1 }, + .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, + .idp_src_en = { 0x0184, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { + { + .reg = 0x760, + .num_ports = 2, + .phy_tuning = rk322x_usb2phy_tuning, + .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .iddig_output = { 0x0760, 10, 10, 0, 1 }, + .iddig_en = { 0x0760, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, + .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, + .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, + .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, + .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, + .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, + .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, + .utmi_ls = { 0x0480, 3, 2, 0, 1 }, + .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0760, 3, 0, 5, 1 }, + .cp_det = { 0x0884, 4, 4, 0, 1 }, + .dcp_det = { 0x0884, 3, 3, 0, 1 }, + .dp_det = { 0x0884, 5, 5, 0, 1 }, + .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, + .idp_src_en = { 0x0768, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0x800, + .num_ports = 2, + .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0684, 1, 1, 0, 1 }, + .ls_det_st = { 0x0694, 1, 1, 0, 1 }, + .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0684, 0, 0, 0, 1 }, + .ls_det_st = { 0x0694, 0, 0, 0, 1 }, + .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .iddig_output = { 0x0100, 10, 10, 0, 1 }, + .iddig_en = { 0x0100, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x110, 1, 1, 0, 1 }, + .ls_det_st = { 0x114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x118, 1, 1, 0, 1 }, + .utmi_ls = { 0x120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0100, 3, 0, 5, 1 }, + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { + { + .reg = 0x700, + .num_ports = 2, + .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, + .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0700, 3, 0, 5, 1 }, + .cp_det = { 0x04b8, 30, 30, 0, 1 }, + .dcp_det = { 0x04b8, 29, 29, 0, 1 }, + .dp_det = { 0x04b8, 31, 31, 0, 1 }, + .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, + .idp_src_en = { 0x0718, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { + { + .reg = 0xe450, + .num_ports = 2, + .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, + .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, + .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, + .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, + .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, + .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, + .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, + .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, + .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, + .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, + .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, + .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, + .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, + .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, + .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, + .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, + .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0xe454, 3, 0, 5, 1 }, + .cp_det = { 0xe2ac, 2, 2, 0, 1 }, + .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, + .dp_det = { 0xe2ac, 0, 0, 0, 1 }, + .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, + .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, + .idp_src_en = { 0xe450, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, + .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, + .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0xe460, + .num_ports = 2, + .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, + .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, + .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, + .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, + .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, + .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, + .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, + .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, + .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, + .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, + .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, + .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, + .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, + .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, + .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, + .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, + .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0xe464, 3, 0, 5, 1 }, + .cp_det = { 0xe2ac, 5, 5, 0, 1 }, + .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, + .dp_det = { 0xe2ac, 3, 3, 0, 1 }, + .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, + .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, + .idp_src_en = { 0xe460, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, + .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, + .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, + .utmi_ls = { 0x0804, 13, 12, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, + .utmi_ls = { 0x0804, 9, 8, 0, 1 }, + .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, + .cp_det = { 0x0804, 1, 1, 0, 1 }, + .dcp_det = { 0x0804, 0, 0, 0, 1 }, + .dp_det = { 0x0804, 2, 2, 0, 1 }, + .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { + { + .reg = 0xfe8a0000, + .num_ports = 2, + .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, + .iddig_output = { 0x0000, 10, 10, 0, 1 }, + .iddig_en = { 0x0000, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, + .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0000, 3, 0, 5, 1 }, + .cp_det = { 0x00c0, 24, 24, 0, 1 }, + .dcp_det = { 0x00c0, 23, 23, 0, 1 }, + .dp_det = { 0x00c0, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, + .idp_src_en = { 0x0008, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0xfe8b0000, + .num_ports = 2, + .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; +static const struct of_device_id rockchip_usb2phy_dt_match[] = { + { .compatible = "rockchip,rk1808-usb2phy", .data = &rk1808_phy_cfgs }, + { .compatible = "rockchip,rk3128-usb2phy", .data = &rk312x_phy_cfgs }, + { .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs }, + { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs }, + { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, + { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, + { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, + { } +}; + +static struct driver_d rockchip_usb2phy_driver = { + .probe = rockchip_usb2phy_probe, + .name = "rockchip-usb2phy", + .of_compatible = rockchip_usb2phy_dt_match, +}; +coredevice_platform_driver(rockchip_usb2phy_driver); diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 0000000000..af4340f90d --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PIPE USB3.0 PCIE SATA combphy driver + * + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <errno.h> +#include <driver.h> +#include <malloc.h> +#include <usb/phy.h> +#include <linux/phy/phy.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/reset.h> +#include <mfd/syscon.h> +#include <linux/iopoll.h> +#include <dt-bindings/phy/phy.h> + +#define BIT_WRITEABLE_SHIFT 16 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const int num_clks; + const struct clk_bulk_data *clks; + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u8 mode; + void __iomem *mmio; + int num_clks; + struct clk_bulk_data *clks; + struct device_d *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_control *apb_rst; + struct reset_control *phy_rst; + const struct rockchip_combphy_cfg *cfg; +}; + +static inline bool param_read(struct regmap *base, + const struct combphy_reg *reg, u32 val) +{ + int ret; + u32 mask, orig, tmp; + + ret = regmap_read(base, reg->offset, &orig); + if (ret) + return false; + + mask = GENMASK(reg->bitend, reg->bitstart); + tmp = (orig & mask) >> reg->bitstart; + + return tmp == val; +} + +static int param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 mask, val; + + mask = GENMASK(cfg->pipe_phy_status.bitend, + cfg->pipe_phy_status.bitstart); + + regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); + val = (val & mask) >> cfg->pipe_phy_status.bitstart; + + return val; +} + +static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for pcie\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for usb3\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for sata\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for sgmii\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + switch (priv->mode) { + case PHY_TYPE_PCIE: + rockchip_combphy_pcie_init(priv); + break; + case PHY_TYPE_USB3: + rockchip_combphy_usb3_init(priv); + break; + case PHY_TYPE_SATA: + rockchip_combphy_sata_init(priv); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + return rockchip_combphy_sgmii_init(priv); + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + return 0; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + int ret; + + ret = clk_bulk_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clks\n"); + return ret; + } + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + ret = reset_control_deassert(priv->phy_rst); + if (ret) + goto err_clk; + + if (priv->mode == PHY_TYPE_USB3) { + ret = readx_poll_timeout(rockchip_combphy_is_ready, + priv, val, + val == cfg->pipe_phy_status.enable, + 1000); + if (ret) + dev_warn(priv->dev, "wait phy status ready timeout\n"); + } + + return 0; + +err_clk: + clk_bulk_disable(priv->num_clks, priv->clks); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable(priv->num_clks, priv->clks); + reset_control_assert(priv->phy_rst); + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, +}; + +static struct phy *rockchip_combphy_xlate(struct device_d *dev, + struct of_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev->priv; + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->mode != PHY_NONE && priv->mode != args->args[0]) + dev_warn(dev, "phy type select %d overwriting type %d\n", + args->args[0], priv->mode); + + priv->mode = args->args[0]; + + return priv->phy; +} + +static int rockchip_combphy_parse_dt(struct device_d *dev, + struct rockchip_combphy_priv *priv) +{ + struct device_node *np = dev->device_node; + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; + int ret, mac_id; + + ret = clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (ret) + priv->num_clks = 0; + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(np, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, + "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + if (!of_property_read_u32(np, "rockchip,sgmii-mac-sel", &mac_id) && + (mac_id > 0)) + param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + true); + + priv->apb_rst = reset_control_get(dev, "combphy-apb"); + if (IS_ERR(priv->apb_rst)) { + ret = PTR_ERR(priv->apb_rst); + + if (ret != -EPROBE_DEFER) + dev_warn(dev, "failed to get apb reset\n"); + + return ret; + } + + priv->phy_rst = reset_control_get(dev, "combphy"); + if (IS_ERR(priv->phy_rst)) { + ret = PTR_ERR(priv->phy_rst); + + if (ret != -EPROBE_DEFER) + dev_warn(dev, "failed to get phy reset\n"); + + return ret; + } + + return reset_control_assert(priv->phy_rst); +} + +static int rockchip_combphy_probe(struct device_d *dev) +{ + struct phy_provider *phy_provider; + struct rockchip_combphy_priv *priv; + const struct rockchip_combphy_cfg *phy_cfg; + struct resource *res; + int ret; + + phy_cfg = device_get_match_data(dev); + if (!phy_cfg) { + dev_err(dev, "No OF match data provided\n"); + return -EINVAL; + } + + priv = xzalloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + res = dev_request_mem_resource(dev, 0); + if (IS_ERR(res)) { + ret = PTR_ERR(res); + return ret; + } + + priv->mmio = IOMEM(res->start); + + priv->num_clks = phy_cfg->num_clks; + + priv->clks = memdup(phy_cfg->clks, + phy_cfg->num_clks * sizeof(struct clk_bulk_data)); + if (!priv->clks) + return -ENOMEM; + + priv->dev = dev; + priv->mode = PHY_NONE; + priv->cfg = phy_cfg; + + ret = rockchip_combphy_parse_dt(dev, priv); + if (ret) + return ret; + + priv->phy = phy_create(dev, NULL, &rochchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev->priv = priv; + phy_set_drvdata(priv->phy, priv); + + phy_provider = of_phy_provider_register(dev, rockchip_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + struct device_node *np = priv->dev->device_node; + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + struct clk *refclk = NULL; + unsigned long rate; + u32 val; + + /* Configure PHY reference clock frequency */ + refclk = priv->clks[0].clk; + if (!refclk) { + dev_err(priv->dev, "No refclk found\n"); + return -EINVAL; + } + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + case PHY_TYPE_SATA: + writel(0x41, priv->mmio + 0x38); + writel(0x8F, priv->mmio + 0x18); + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + case PHY_TYPE_SGMII: + param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + case PHY_TYPE_QSGMII: + param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(refclk); + + switch (rate) { + case 24000000: + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(7, 6); + val |= 0x01 << 6; + writel(val, priv->mmio + (0x0e << 2)); + + val = readl(priv->mmio + (0x0f << 2)); + val &= ~GENMASK(7, 0); + val |= 0x5f; + writel(val, priv->mmio + (0x0f << 2)); + } + break; + case 25000000: + param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case 100000000: + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Enable controlling random jitter, aka RMJ */ + writel(0x4, priv->mmio + (0xb << 2)); + + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + writel(0x32, priv->mmio + (0x11 << 2)); + writel(0xf0, priv->mmio + (0xa << 2)); + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(7, 4); + val |= 0x50; + writel(val, priv->mmio + (0x1f << 2)); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (of_property_read_bool(np, "rockchip,ext-refclk")) { + param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { + val = readl(priv->mmio + (0xc << 2)); + val |= 0x3 << 4 | 0x1 << 7; + writel(val, priv->mmio + (0xc << 2)); + + val = readl(priv->mmio + (0xd << 2)); + val |= 0x1; + writel(val, priv->mmio + (0xd << 2)); + } + } + + if (of_property_read_bool(np, "rockchip,enable-ssc")) { + val = readl(priv->mmio + (0x7 << 2)); + val |= BIT(4); + writel(val, priv->mmio + (0x7 << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct clk_bulk_data rk3568_clks[] = { + { .id = "refclk" }, + { .id = "apbclk" }, + { .id = "pipe_clk" }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .num_clks = ARRAY_SIZE(rk3568_clks), + .clks = rk3568_clks, + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, + { }, +}; + +static struct driver_d rockchip_combphy_driver = { + .probe = rockchip_combphy_probe, + .name = "naneng-combphy", + .of_compatible = rockchip_combphy_of_match, +}; +coredevice_platform_driver(rockchip_combphy_driver); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index be44067c8f..9b832c97d6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -332,63 +332,52 @@ static struct gpio_ops rockchip_gpio_ops = { .get_direction = rockchip_gpiov2_get_direction, }; -static int rockchip_gpiolib_register(struct device_d *dev, - struct rockchip_pinctrl *info) +static int rockchip_gpio_probe(struct device_d *dev) { + struct rockchip_pinctrl *info = dev->parent->priv; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_pin_bank *bank = ctrl->pin_banks; + struct rockchip_pin_bank *bank; + struct gpio_chip *gpio; void __iomem *reg_base; - int ret; - int i; + int ret, bankno; - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { - struct gpio_chip *gpio = &bank->bgpio_chip.gc; + bankno = of_alias_get_id(dev->device_node, "gpio"); + bank = &ctrl->pin_banks[bankno]; + gpio = &bank->bgpio_chip.gc; - if (!bank->valid) { - dev_warn(dev, "bank %s is not valid\n", bank->name); - continue; - } + if (!bank->valid) + dev_warn(dev, "bank %s is not valid\n", bank->name); - reg_base = bank->reg_base; - - if (ctrl->type == RK3568) { - gpio->ngpio = 32; - gpio->dev = dev; - gpio->ops = &rockchip_gpio_ops; - gpio->base = of_alias_get_id(bank->of_node, "gpio"); - if (gpio->base < 0) - return -EINVAL; - gpio->base *= 32; - } else { - ret = bgpio_init(&bank->bgpio_chip, dev, 4, - reg_base + RK_GPIO_EXT_PORT, - reg_base + RK_GPIO_SWPORT_DR, NULL, - reg_base + RK_GPIO_SWPORT_DDR, NULL, 0); - if (ret) - goto fail; - } + reg_base = bank->reg_base; - bank->bgpio_chip.gc.dev = of_find_device_by_node(bank->of_node); + if (ctrl->type == RK3568) { + gpio->ngpio = 32; + gpio->dev = dev; + gpio->ops = &rockchip_gpio_ops; + gpio->base = bankno; + if (gpio->base < 0) + return -EINVAL; + gpio->base *= 32; + } else { + ret = bgpio_init(&bank->bgpio_chip, dev, 4, + reg_base + RK_GPIO_EXT_PORT, + reg_base + RK_GPIO_SWPORT_DR, NULL, + reg_base + RK_GPIO_SWPORT_DDR, NULL, 0); + if (ret) + return ret; + } - bank->bgpio_chip.gc.ngpio = bank->nr_pins; - ret = gpiochip_add(&bank->bgpio_chip.gc); - if (ret) { - dev_err(dev, "failed to register gpio_chip %s, error code: %d\n", - bank->name, ret); - goto fail; - } + bank->bgpio_chip.gc.dev = dev; + bank->bgpio_chip.gc.ngpio = bank->nr_pins; + ret = gpiochip_add(&bank->bgpio_chip.gc); + if (ret) { + dev_err(dev, "failed to register gpio_chip %s, error code: %d\n", + bank->name, ret); + return ret; } return 0; -fail: - for (--i, --bank; i >= 0; --i, --bank) { - if (!bank->valid) - continue; - - gpiochip_remove(&bank->bgpio_chip.gc); - } - return ret; } static struct rockchip_pinctrl *to_rockchip_pinctrl(struct pinctrl_device *pdev) @@ -1010,8 +999,6 @@ static int rockchip_pinctrl_probe(struct device_d *dev) struct rockchip_pin_ctrl *ctrl; int ret; - of_platform_populate(dev->device_node, NULL, NULL); - info = xzalloc(sizeof(struct rockchip_pinctrl)); ctrl = rockchip_pinctrl_get_soc_data(info, dev); @@ -1038,9 +1025,9 @@ static int rockchip_pinctrl_probe(struct device_d *dev) info->pctl_dev.dev = dev; info->pctl_dev.ops = &rockchip_pinctrl_ops; - ret = rockchip_gpiolib_register(dev, info); - if (ret) - return ret; + dev->priv = info; + + of_platform_populate(dev->device_node, NULL, dev); if (!IS_ENABLED(CONFIG_PINCTRL)) return 0; @@ -1282,3 +1269,20 @@ static struct driver_d rockchip_pinctrl_driver = { }; core_platform_driver(rockchip_pinctrl_driver); + +static struct of_device_id rockchip_gpio_dt_match[] = { + { + .compatible = "rockchip,gpio-bank", + .data = &rk2928_pin_ctrl, + }, { + /* sentinel */ + } +}; + +static struct driver_d rockchip_gpio_driver = { + .name = "rockchip-gpio", + .probe = rockchip_gpio_probe, + .of_compatible = DRV_OF_COMPAT(rockchip_gpio_dt_match), +}; + +core_platform_driver(rockchip_gpio_driver); diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index f416acc999..49deaf4d98 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -643,14 +643,14 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) /* Initialize the TRB ring */ dep->trb_dequeue = 0; dep->trb_enqueue = 0; - memset(dep->trb_pool, 0, + memset_io(dep->trb_pool, 0, sizeof(struct dwc3_trb) * DWC3_TRB_NUM); /* Link TRB. The HWO bit is never reset */ trb_st_hw = &dep->trb_pool[0]; trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; - memset(trb_link, 0, sizeof(*trb_link)); + memset_io(trb_link, 0, sizeof(*trb_link)); trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); @@ -2908,10 +2908,10 @@ static void dwc3_gadget_poll(struct usb_gadget * g) buf = xzalloc(count); amount = min(count, evt->length - evt->lpos); - memcpy(buf, evt->buf + evt->lpos, amount); + memcpy_fromio(buf, evt->buf + evt->lpos, amount); if (amount < count) - memcpy(buf + amount, evt->buf, count - amount); + memcpy_fromio(buf + amount, evt->buf, count - amount); evt->lpos = (evt->lpos + count) % evt->length; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 8c4da9fd12..4dd4d1dddb 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -32,6 +32,8 @@ #include <usb/ehci.h> #include <linux/err.h> #include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/phy/phy.h> #include "ehci.h" @@ -1413,6 +1415,9 @@ static int ehci_probe(struct device_d *dev) struct ehci_platform_data *pdata = dev->platform_data; struct device_node *dn = dev->device_node; struct ehci_host *ehci; + struct clk_bulk_data *clks; + int num_clocks, ret; + struct phy *usb2_generic_phy; if (pdata) data.flags = pdata->flags; @@ -1440,6 +1445,27 @@ static int ehci_probe(struct device_d *dev) else data.hcor = NULL; + usb2_generic_phy = phy_optional_get(dev, "usb"); + if (IS_ERR(usb2_generic_phy)) + return PTR_ERR(usb2_generic_phy); + + ret = phy_init(usb2_generic_phy); + if (ret) + return ret; + + ret = phy_power_on(usb2_generic_phy); + if (ret) + return ret; + + ret = clk_bulk_get_all(dev, &clks); + if (ret < 0) + return ret; + + num_clocks = ret; + ret = clk_bulk_enable(num_clocks, clks); + if (ret) + return ret; + ehci = ehci_register(dev, &data); if (IS_ERR(ehci)) return PTR_ERR(ehci); |