usb: Add dwc2 host driver

This adds a driver for the dwc2 controller in host mode. The driver is
taken from U-Boot-2019.10 and tested on a Raspberry Pi 3.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 1914 insertions, 0 deletions

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d2029bc7d7..b0f32faee9 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -21,6 +21,9 @@ config USB_OHCI_AT91
 	depends on ARCH_AT91
 	bool "AT91 OHCI driver"
 
+config USB_DWC2_HOST
+	bool "DWC2 Host driver"
+
 config USB_XHCI
 	bool "xHCI driver"
 	depends on HAS_DMA
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 0478d34272..fa042e9a54 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_USB_EHCI_OMAP)	+= ehci-omap.o
 obj-$(CONFIG_USB_EHCI_ATMEL)	+= ehci-atmel.o
 obj-$(CONFIG_USB_OHCI)		+= ohci-hcd.o
 obj-$(CONFIG_USB_OHCI_AT91)	+= ohci-at91.o
+obj-$(CONFIG_USB_DWC2_HOST)	+= dwc2.o
 obj-$(CONFIG_USB_XHCI)		+= xhci-hcd.o xhci-hub.o
 obj-$(CONFIG_USB_XHCI_PCI)	+= xhci-pci.o
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
new file mode 100644
index 0000000000..1df1149686
--- /dev/null
+++ b/drivers/usb/host/dwc2.c
@@ -0,0 +1,1132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <usb/usb.h>
+#include <usb/usbroothubdes.h>
+#include <malloc.h>
+#include <init.h>
+#include <io.h>
+#include <of.h>
+#include <linux/iopoll.h>
+#include <dma.h>
+
+#include "dwc2.h"
+
+/* Use only HC channel 0. */
+#define DWC2_HC_CHANNEL			0
+
+#define DWC2_STATUS_BUF_SIZE		64
+#define DWC2_DATA_BUF_SIZE		(16 * 1024)
+
+#define MAX_DEVICE			16
+#define MAX_ENDPOINT			16
+
+struct dwc2_priv {
+	struct device_d *dev;
+	struct usb_host host;
+	uint8_t *dmabuf;
+
+	u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+	u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+	struct dwc2_core_regs *regs;
+	int root_hub_devnum;
+	bool ext_vbus;
+	/*
+	 * The hnp/srp capability must be disabled if the platform
+	 * does't support hnp/srp. Otherwise the force mode can't work.
+	 */
+	bool hnp_srp_disable;
+	bool oc_disable;
+};
+
+/*
+ * Initializes the FSLSPClkSel field of the HCFG register
+ * depending on the PHY type.
+ */
+static void init_fslspclksel(struct dwc2_priv *priv)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	uint32_t phyclk;
+
+	phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;	/* Full speed PHY */
+
+	clrsetbits_le32(&regs->host_regs.hcfg,
+			DWC2_HCFG_FSLSPCLKSEL_MASK,
+			phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
+}
+
+/*
+ * Flush a Tx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ * @param num Tx FIFO to flush.
+ */
+static void dwc_otg_flush_tx_fifo(struct dwc2_priv *priv, const int num)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct device_d *dev = priv->dev;
+	int ret;
+	uint32_t val;
+
+	writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
+	       &regs->grstctl);
+	ret = readl_poll_timeout(&regs->grstctl, val, !(val & DWC2_GRSTCTL_TXFFLSH),
+				 1000000);
+	if (ret)
+		dev_err(dev, "%s: Timeout!\n", __func__);
+
+	/* Wait for 3 PHY Clocks */
+	udelay(1);
+}
+
+/*
+ * Flush Rx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ */
+static void dwc_otg_flush_rx_fifo(struct dwc2_priv *priv)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct device_d *dev = priv->dev;
+	int ret;
+	uint32_t val;
+
+	writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
+	ret = readl_poll_timeout(&regs->grstctl, val, !(val & DWC2_GRSTCTL_RXFFLSH),
+				 1000000);
+	if (ret)
+		dev_err(dev, "%s: Timeout!\n", __func__);
+
+	/* Wait for 3 PHY Clocks */
+	udelay(1);
+}
+
+/*
+ * Do core a soft reset of the core.  Be careful with this because it
+ * resets all the internal state machines of the core.
+ */
+static void dwc_otg_core_reset(struct dwc2_priv *priv)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct device_d *dev = priv->dev;
+	uint32_t val;
+	int ret;
+
+	/* Wait for AHB master IDLE state. */
+	ret = readl_poll_timeout(&regs->grstctl, val, val & DWC2_GRSTCTL_AHBIDLE,
+				 1000000);
+	if (ret)
+		dev_err(dev, "%s: Timeout!\n", __func__);
+
+	/* Core Soft Reset */
+	writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
+	ret = readl_poll_timeout(&regs->grstctl, val, !(val & DWC2_GRSTCTL_CSFTRST),
+				 1000000);
+	if (ret)
+		dev_err(dev, "%s: Timeout!\n", __func__);
+
+	/*
+	 * Wait for core to come out of reset.
+	 * NOTE: This long sleep is _very_ important, otherwise the core will
+	 *       not stay in host mode after a connector ID change!
+	 */
+	mdelay(100);
+}
+
+/*
+ * This function initializes the DWC_otg controller registers for
+ * host mode.
+ *
+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
+ * request queues. Host channels are reset to ensure that they are ready for
+ * performing transfers.
+ *
+ * @param dev USB Device (NULL if driver model is not being used)
+ * @param regs Programming view of DWC_otg controller
+ *
+ */
+static void dwc_otg_core_host_init(struct dwc2_priv *priv)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct device_d *dev = priv->dev;
+	uint32_t nptxfifosize = 0;
+	uint32_t ptxfifosize = 0;
+	uint32_t hprt0 = 0;
+	uint32_t val;
+	int i, ret, num_channels;
+
+	/* Restart the Phy Clock */
+	writel(0, &regs->pcgcctl);
+
+	/* Initialize Host Configuration Register */
+	init_fslspclksel(priv);
+
+	/* Configure data FIFO sizes */
+	if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
+		/* Rx FIFO */
+		writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
+
+		/* Non-periodic Tx FIFO */
+		nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+				DWC2_FIFOSIZE_DEPTH_OFFSET;
+		nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+				DWC2_FIFOSIZE_STARTADDR_OFFSET;
+		writel(nptxfifosize, &regs->gnptxfsiz);
+
+		/* Periodic Tx FIFO */
+		ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+				DWC2_FIFOSIZE_DEPTH_OFFSET;
+		ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
+				CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+				DWC2_FIFOSIZE_STARTADDR_OFFSET;
+		writel(ptxfifosize, &regs->hptxfsiz);
+	}
+
+	/* Clear Host Set HNP Enable in the OTG Control Register */
+	clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
+
+	/* Make sure the FIFOs are flushed. */
+	dwc_otg_flush_tx_fifo(priv, 0x10);	/* All Tx FIFOs */
+	dwc_otg_flush_rx_fifo(priv);
+
+	/* Flush out any leftover queued requests. */
+	num_channels = readl(&regs->ghwcfg2);
+	num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
+	num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
+	num_channels += 1;
+
+	for (i = 0; i < num_channels; i++)
+		clrsetbits_le32(&regs->hc_regs[i].hcchar,
+				DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
+				DWC2_HCCHAR_CHDIS);
+
+	/* Halt all channels to put them into a known state. */
+	for (i = 0; i < num_channels; i++) {
+		clrsetbits_le32(&regs->hc_regs[i].hcchar,
+				DWC2_HCCHAR_EPDIR,
+				DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
+		ret = readl_poll_timeout(&regs->hc_regs[i].hcchar, val,
+				 !(val & DWC2_HCCHAR_CHEN),
+				 1000000);
+		if (ret)
+			dev_err(dev, "%s: Timeout!\n", __func__);
+	}
+
+	/* Turn on the vbus power. */
+	if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
+		hprt0 = readl(&regs->hprt0);
+		hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
+		hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
+		if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
+			hprt0 |= DWC2_HPRT0_PRTPWR;
+			writel(hprt0, &regs->hprt0);
+		}
+	}
+}
+
+/*
+ * This function initializes the DWC_otg controller registers and
+ * prepares the core for device mode or host mode operation.
+ *
+ * @param regs Programming view of the DWC_otg controller
+ */
+static void dwc_otg_core_init(struct dwc2_priv *priv)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	uint32_t ahbcfg = 0;
+	uint32_t usbcfg = 0;
+	uint8_t brst_sz = 32;
+
+	/* Common Initialization */
+	usbcfg = readl(&regs->gusbcfg);
+
+	/* Program the ULPI External VBUS bit if needed */
+	if (priv->ext_vbus) {
+		usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+		if (!priv->oc_disable) {
+			usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
+				  DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
+		}
+	} else {
+		usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+	}
+
+	/* Set external TS Dline pulsing */
+	usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
+	writel(usbcfg, &regs->gusbcfg);
+
+	/* Reset the Controller */
+	dwc_otg_core_reset(priv);
+
+	/* High speed PHY. */
+
+	/*
+	 * HS PHY parameters. These parameters are preserved during
+	 * soft reset so only program the first time. Do a soft reset
+	 * immediately after setting phyif.
+	 */
+	usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
+	usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+
+	if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) /* ULPI interface */
+		usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
+
+	writel(usbcfg, &regs->gusbcfg);
+
+	/* Reset after setting the PHY parameters */
+	dwc_otg_core_reset(priv);
+
+	usbcfg = readl(&regs->gusbcfg);
+	usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
+
+	if (priv->hnp_srp_disable)
+		usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
+
+	writel(usbcfg, &regs->gusbcfg);
+
+	/* Program the GAHBCFG Register. */
+	switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
+	case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
+		break;
+	case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
+		while (brst_sz > 1) {
+			ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
+			ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
+			brst_sz >>= 1;
+		}
+
+		ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
+		break;
+
+	case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
+		ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
+		ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
+		break;
+	}
+
+	writel(ahbcfg, &regs->gahbcfg);
+
+	/* Program the capabilities in GUSBCFG Register */
+	usbcfg = 0;
+
+	if (!priv->hnp_srp_disable)
+		usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
+
+	setbits_le32(&regs->gusbcfg, usbcfg);
+}
+
+/*
+ * Prepares a host channel for transferring packets to/from a specific
+ * endpoint. The HCCHARn register is set up with the characteristics specified
+ * in _hc. Host channel interrupts that may need to be serviced while this
+ * transfer is in progress are enabled.
+ *
+ * @param regs Programming view of DWC_otg controller
+ * @param hc Information needed to initialize the host channel
+ */
+static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
+		struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
+		uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
+{
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
+	uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
+			  (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
+			  (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
+			  (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
+			  (max_packet << DWC2_HCCHAR_MPS_OFFSET);
+
+	if (dev->speed == USB_SPEED_LOW)
+		hcchar |= DWC2_HCCHAR_LSPDDEV;
+
+	/*
+	 * Program the HCCHARn register with the endpoint characteristics
+	 * for the current transfer.
+	 */
+	writel(hcchar, &hc_regs->hcchar);
+
+	/* Program the HCSPLIT register, default to no SPLIT */
+	writel(0, &hc_regs->hcsplt);
+}
+
+static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
+				  uint8_t hub_devnum, uint8_t hub_port)
+{
+	uint32_t hcsplt = 0;
+
+	hcsplt = DWC2_HCSPLT_SPLTENA;
+	hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
+	hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
+
+	/* Program the HCSPLIT register for SPLITs */
+	writel(hcsplt, &hc_regs->hcsplt);
+}
+
+/*
+ * DWC2 to USB API interface
+ */
+/* Direction: In ; Request: Status */
+static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
+					   struct usb_device *dev, void *buffer,
+					   int txlen, struct devrequest *cmd)
+{
+	uint32_t hprt0 = 0;
+	uint32_t port_status = 0;
+	uint32_t port_change = 0;
+	int len = 0;
+	int stat = 0;
+
+	switch (cmd->requesttype & ~USB_DIR_IN) {
+	case 0:
+		*(uint16_t *)buffer = cpu_to_le16(1);
+		len = 2;
+		break;
+	case USB_RECIP_INTERFACE:
+	case USB_RECIP_ENDPOINT:
+		*(uint16_t *)buffer = cpu_to_le16(0);
+		len = 2;
+		break;
+	case USB_TYPE_CLASS:
+		*(uint32_t *)buffer = cpu_to_le32(0);
+		len = 4;
+		break;
+	case USB_RECIP_OTHER | USB_TYPE_CLASS:
+		hprt0 = readl(&regs->hprt0);
+		if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
+			port_status |= USB_PORT_STAT_CONNECTION;
+		if (hprt0 & DWC2_HPRT0_PRTENA)
+			port_status |= USB_PORT_STAT_ENABLE;
+		if (hprt0 & DWC2_HPRT0_PRTSUSP)
+			port_status |= USB_PORT_STAT_SUSPEND;
+		if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
+			port_status |= USB_PORT_STAT_OVERCURRENT;
+		if (hprt0 & DWC2_HPRT0_PRTRST)
+			port_status |= USB_PORT_STAT_RESET;
+		if (hprt0 & DWC2_HPRT0_PRTPWR)
+			port_status |= USB_PORT_STAT_POWER;
+
+		if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
+			port_status |= USB_PORT_STAT_LOW_SPEED;
+		else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
+			 DWC2_HPRT0_PRTSPD_HIGH)
+			port_status |= USB_PORT_STAT_HIGH_SPEED;
+
+		if (hprt0 & DWC2_HPRT0_PRTENCHNG)
+			port_change |= USB_PORT_STAT_C_ENABLE;
+		if (hprt0 & DWC2_HPRT0_PRTCONNDET)
+			port_change |= USB_PORT_STAT_C_CONNECTION;
+		if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
+			port_change |= USB_PORT_STAT_C_OVERCURRENT;
+
+		*(uint32_t *)buffer = cpu_to_le32(port_status |
+					(port_change << 16));
+		len = 4;
+		break;
+	default:
+		pr_err("%s: unsupported root hub command\n", __func__);
+		stat = USB_ST_STALLED;
+	}
+
+	dev->act_len = min(len, txlen);
+	dev->status = stat;
+
+	return stat;
+}
+
+/* Direction: In ; Request: Descriptor */
+static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
+					       void *buffer, int txlen,
+					       struct devrequest *cmd)
+{
+	unsigned char data[32];
+	uint32_t dsc;
+	int len = 0;
+	int stat = 0;
+	uint16_t wValue = cpu_to_le16(cmd->value);
+	uint16_t wLength = cpu_to_le16(cmd->length);
+
+	switch (cmd->requesttype & ~USB_DIR_IN) {
+	case 0:
+		switch (wValue & 0xff00) {
+		case 0x0100:	/* device descriptor */
+			len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
+			memcpy(buffer, root_hub_dev_des, len);
+			break;
+		case 0x0200:	/* configuration descriptor */
+			len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
+			memcpy(buffer, root_hub_config_des, len);
+			break;
+		case 0x0300:	/* string descriptors */
+			switch (wValue & 0xff) {
+			case 0x00:
+				len = min3(txlen, (int)sizeof(root_hub_str_index0),
+					   (int)wLength);
+				memcpy(buffer, root_hub_str_index0, len);
+				break;
+			case 0x01:
+				len = min3(txlen, (int)sizeof(root_hub_str_index1),
+					   (int)wLength);
+				memcpy(buffer, root_hub_str_index1, len);
+				break;
+			}
+			break;
+		default:
+			stat = USB_ST_STALLED;
+		}
+		break;
+
+	case USB_TYPE_CLASS:
+		/* Root port config, set 1 port and nothing else. */
+		dsc = 0x00000001;
+
+		data[0] = 9;		/* min length; */
+		data[1] = 0x29;
+		data[2] = dsc & RH_A_NDP;
+		data[3] = 0;
+		if (dsc & RH_A_PSM)
+			data[3] |= 0x1;
+		if (dsc & RH_A_NOCP)
+			data[3] |= 0x10;
+		else if (dsc & RH_A_OCPM)
+			data[3] |= 0x8;
+
+		/* corresponds to data[4-7] */
+		data[5] = (dsc & RH_A_POTPGT) >> 24;
+		data[7] = dsc & RH_B_DR;
+		if (data[2] < 7) {
+			data[8] = 0xff;
+		} else {
+			data[0] += 2;
+			data[8] = (dsc & RH_B_DR) >> 8;
+			data[9] = 0xff;
+			data[10] = data[9];
+		}
+
+		len = min3(txlen, (int)data[0], (int)wLength);
+		memcpy(buffer, data, len);
+		break;
+	default:
+		pr_err("%s: unsupported root hub command\n", __func__);
+		stat = USB_ST_STALLED;
+	}
+
+	dev->act_len = min(len, txlen);
+	dev->status = stat;
+
+	return stat;
+}
+
+/* Direction: In ; Request: Configuration */
+static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
+						  void *buffer, int txlen,
+						  struct devrequest *cmd)
+{
+	int len = 0;
+	int stat = 0;
+
+	switch (cmd->requesttype & ~USB_DIR_IN) {
+	case 0:
+		*(uint8_t *)buffer = 0x01;
+		len = 1;
+		break;
+	default:
+		pr_err("%s: unsupported root hub command\n", __func__);
+		stat = USB_ST_STALLED;
+	}
+
+	dev->act_len = min(len, txlen);
+	dev->status = stat;
+
+	return stat;
+}
+
+/* Direction: In */
+static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
+				    struct usb_device *dev, void *buffer,
+				    int txlen, struct devrequest *cmd)
+{
+	switch (cmd->request) {
+	case USB_REQ_GET_STATUS:
+		return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
+						       txlen, cmd);
+	case USB_REQ_GET_DESCRIPTOR:
+		return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
+							   txlen, cmd);
+	case USB_REQ_GET_CONFIGURATION:
+		return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
+							      txlen, cmd);
+	default:
+		pr_err("%s: unsupported root hub command\n", __func__);
+		return USB_ST_STALLED;
+	}
+}
+
+/* Direction: Out */
+static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
+				     struct usb_device *dev,
+				     void *buffer, int txlen,
+				     struct devrequest *cmd)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	int len = 0;
+	int stat = 0;
+	uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
+	uint16_t wValue = cpu_to_le16(cmd->value);
+
+	switch (bmrtype_breq & ~USB_DIR_IN) {
+	case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
+	case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
+		break;
+
+	case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
+		switch (wValue) {
+		case USB_PORT_FEAT_C_CONNECTION:
+			setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
+			break;
+		}
+		break;
+
+	case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
+		switch (wValue) {
+		case USB_PORT_FEAT_SUSPEND:
+			break;
+
+		case USB_PORT_FEAT_RESET:
+			clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+					DWC2_HPRT0_PRTCONNDET |
+					DWC2_HPRT0_PRTENCHNG |
+					DWC2_HPRT0_PRTOVRCURRCHNG,
+					DWC2_HPRT0_PRTRST);
+			mdelay(50);
+			clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
+			break;
+
+		case USB_PORT_FEAT_POWER:
+			clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+					DWC2_HPRT0_PRTCONNDET |
+					DWC2_HPRT0_PRTENCHNG |
+					DWC2_HPRT0_PRTOVRCURRCHNG,
+					DWC2_HPRT0_PRTRST);
+			break;
+
+		case USB_PORT_FEAT_ENABLE:
+			break;
+		}
+		break;
+	case (USB_REQ_SET_ADDRESS << 8):
+		priv->root_hub_devnum = wValue;
+		break;
+	case (USB_REQ_SET_CONFIGURATION << 8):
+		break;
+	default:
+		pr_err("%s: unsupported root hub command\n", __func__);
+		stat = USB_ST_STALLED;
+	}
+
+	len = min(len, txlen);
+
+	dev->act_len = len;
+	dev->status = stat;
+
+	return stat;
+}
+
+static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
+				 unsigned long pipe, void *buffer, int txlen,
+				 struct devrequest *cmd)
+{
+	int stat = 0;
+
+	if (usb_pipeint(pipe)) {
+		pr_err("Root-Hub submit IRQ: NOT implemented\n");
+		return 0;
+	}
+
+	if (cmd->requesttype & USB_DIR_IN)
+		stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
+	else
+		stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
+
+	mdelay(1);
+
+	return stat;
+}
+
+static int wait_for_chhltd(struct dwc2_priv *priv, uint32_t *sub,
+			   u8 *toggle, int timeout_ms)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
+	struct device_d *dev = priv->dev;
+	int ret;
+	uint32_t hcint, hctsiz;
+	uint32_t val;
+	int timeout_us = timeout_ms * 1000;
+
+	ret = readl_poll_timeout(&hc_regs->hcint, val,
+				 val & DWC2_HCINT_CHHLTD, timeout_us);
+	if (ret) {
+		clrsetbits_le32(&hc_regs->hcchar, 0, DWC2_HCCHAR_CHDIS);
+		readl_poll_timeout(&hc_regs->hcint, val,
+					 val & DWC2_HCINT_CHHLTD, 10000);
+
+		return ret;
+	}
+
+	hcint = readl(&hc_regs->hcint);
+	hctsiz = readl(&hc_regs->hctsiz);
+	*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
+		DWC2_HCTSIZ_XFERSIZE_OFFSET;
+	*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
+
+	dev_dbg(dev, "%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
+	      *toggle);
+
+	if (hcint & DWC2_HCINT_XFERCOMP)
+		return 0;
+
+	if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
+		return -EAGAIN;
+
+	dev_dbg(dev, "%s: Error (HCINT=%08x)\n", __func__, hcint);
+
+	return -EINVAL;
+}
+
+static int dwc2_eptype[] = {
+	DWC2_HCCHAR_EPTYPE_ISOC,
+	DWC2_HCCHAR_EPTYPE_INTR,
+	DWC2_HCCHAR_EPTYPE_CONTROL,
+	DWC2_HCCHAR_EPTYPE_BULK,
+};
+
+static int transfer_chunk(struct dwc2_priv *priv, u8 *pid, int in, void *buffer,
+			  int num_packets, int xfer_len, int *actual_len,
+			  int odd_frame, int timeout_ms)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
+	int ret = 0;
+	uint32_t sub = 0;
+	enum dma_data_direction dir;
+	dma_addr_t dma = 0;
+
+	dev_dbg(priv->dev, "%s: chunk: pid %d xfer_len %u pkts %u\n",
+		__func__, *pid, xfer_len, num_packets);
+
+	writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+	       (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+	       (*pid << DWC2_HCTSIZ_PID_OFFSET),
+	       &hc_regs->hctsiz);
+
+	if (xfer_len) {
+		if (in) {
+			dir = DMA_FROM_DEVICE;
+		} else {
+			memcpy(priv->dmabuf, buffer, xfer_len);
+			dir = DMA_TO_DEVICE;
+		}
+		dma = dma_map_single(priv->dev, priv->dmabuf, xfer_len, dir);
+	}
+
+	writel(dma, &hc_regs->hcdma);
+
+	/* Clear old interrupt conditions for this host channel. */
+	writel(0x3fff, &hc_regs->hcint);
+
+	/* Set host channel enable after all other setup is complete. */
+	clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+			DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
+			DWC2_HCCHAR_ODDFRM,
+			(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+			(odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
+			DWC2_HCCHAR_CHEN);
+
+	ret = wait_for_chhltd(priv, &sub, pid, timeout_ms);
+
+	if (xfer_len)
+		dma_unmap_single(priv->dev, dma, xfer_len, dir);
+
+	if (in) {
+		xfer_len -= sub;
+
+		memcpy(buffer, priv->dmabuf, xfer_len);
+	}
+
+	if (!ret)
+		*actual_len = xfer_len;
+
+	return ret;
+}
+
+static int usb_find_usb2_hub_address_port(struct usb_device *udev,
+                               uint8_t *hub_address, uint8_t *hub_port)
+{
+	/* Find out the nearest parent which is high speed */
+	while (udev->parent->parent) {
+		if (udev->parent->speed != USB_SPEED_HIGH) {
+			udev = udev->parent;
+		} else {
+			*hub_address = udev->parent->devnum;
+			*hub_port = udev->portnr;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
+	      unsigned long pipe, u8 *pid, int in, void *buffer, int len,
+	      int timeout_ms)
+{
+	struct dwc2_core_regs *regs = priv->regs;
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
+	struct dwc2_host_regs *host_regs = &regs->host_regs;
+	int devnum = usb_pipedevice(pipe);
+	int ep = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	int eptype = dwc2_eptype[usb_pipetype(pipe)];
+	int done = 0;
+	int ret = 0;
+	int do_split = 0;
+	int complete_split = 0;
+	uint32_t xfer_len;
+	uint32_t num_packets;
+	int stop_transfer = 0;
+	uint32_t max_xfer_len;
+	int ssplit_frame_num = 0;
+
+	dev_dbg(priv->dev, "%s: msg: pipe %lx pid %d in %d len %d\n",
+		__func__, pipe, *pid, in, len);
+
+	max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
+	if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
+		max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+	if (max_xfer_len > DWC2_DATA_BUF_SIZE)
+		max_xfer_len = DWC2_DATA_BUF_SIZE;
+
+	/* Make sure that max_xfer_len is a multiple of max packet size. */
+	num_packets = max_xfer_len / max;
+	max_xfer_len = num_packets * max;
+
+	/* Initialize channel */
+	dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
+			eptype, max);
+
+	/* Check if the target is a FS/LS device behind a HS hub */
+	if (dev->speed != USB_SPEED_HIGH) {
+		uint8_t hub_addr;
+		uint8_t hub_port;
+		uint32_t hprt0 = readl(&regs->hprt0);
+
+		if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_HIGH) {
+			ret = usb_find_usb2_hub_address_port(dev, &hub_addr,
+						       &hub_port);
+			if (ret)
+				return ret;
+			dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
+
+			do_split = 1;
+			num_packets = 1;
+			max_xfer_len = max;
+		}
+	}
+
+	do {
+		int actual_len = 0;
+		uint32_t hcint;
+		int odd_frame = 0;
+		xfer_len = len - done;
+
+		if (xfer_len > max_xfer_len)
+			xfer_len = max_xfer_len;
+		else if (xfer_len > max)
+			num_packets = (xfer_len + max - 1) / max;
+		else
+			num_packets = 1;
+
+		if (complete_split)
+			setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+		else if (do_split)
+			clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+
+		if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
+			int uframe_num = readl(&host_regs->hfnum);
+			if (!(uframe_num & 0x1))
+				odd_frame = 1;
+		}
+
+		ret = transfer_chunk(priv, pid, in, (char *)buffer + done,
+				     num_packets, xfer_len, &actual_len,
+				     odd_frame, timeout_ms);
+
+		hcint = readl(&hc_regs->hcint);
+		if (complete_split) {
+			stop_transfer = 0;
+			if (hcint & DWC2_HCINT_NYET) {
+				int frame_num = DWC2_HFNUM_MAX_FRNUM &
+						readl(&host_regs->hfnum);
+				ret = 0;
+				if (((frame_num - ssplit_frame_num) &
+				    DWC2_HFNUM_MAX_FRNUM) > 4)
+					ret = -EAGAIN;
+			} else
+				complete_split = 0;
+		} else if (do_split) {
+			if (hcint & DWC2_HCINT_ACK) {
+				ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
+						   readl(&host_regs->hfnum);
+				ret = 0;
+				complete_split = 1;
+			}
+		}
+
+		if (ret)
+			break;
+
+		if (actual_len < xfer_len)
+			stop_transfer = 1;
+
+		done += actual_len;
+
+	/*
+	 * Transactions are done when when either all data is transferred or
+	 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
+	 * is executed.
+	 */
+	} while (((done < len) && !stop_transfer) || complete_split);
+
+	writel(0, &hc_regs->hcintmsk);
+	writel(0xFFFFFFFF, &hc_regs->hcint);
+
+	dev->status = 0;
+	dev->act_len = done;
+
+	return ret;
+}
+
+#define to_dwc2(ptr) container_of(ptr, struct dwc2_priv, host)
+
+static int dwc2_init_common(struct usb_host *host)
+{
+	struct dwc2_priv *priv = to_dwc2(host);
+	struct dwc2_core_regs *regs = priv->regs;
+	int i, j;
+
+	priv->ext_vbus = 0;
+
+	dwc_otg_core_init(priv);
+	dwc_otg_core_host_init(priv);
+
+	clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+			DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
+			DWC2_HPRT0_PRTOVRCURRCHNG,
+			DWC2_HPRT0_PRTRST);
+	mdelay(50);
+	clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
+		     DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
+		     DWC2_HPRT0_PRTRST);
+
+	for (i = 0; i < MAX_DEVICE; i++) {
+		for (j = 0; j < MAX_ENDPOINT; j++) {
+			priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+			priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+		}
+	}
+
+	return 0;
+}
+
+static void dwc2_uninit_common(struct dwc2_core_regs *regs)
+{
+	/* Put everything in reset. */
+	clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+			DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
+			DWC2_HPRT0_PRTOVRCURRCHNG,
+			DWC2_HPRT0_PRTRST);
+}
+
+static int dwc2_submit_control_msg(struct usb_device *udev,
+				   unsigned long pipe, void *buffer, int len,
+				   struct devrequest *setup, int timeout_ms)
+{
+	struct usb_host *host = udev->host;
+	struct dwc2_priv *priv = to_dwc2(host);
+	int devnum = usb_pipedevice(pipe);
+	int ret, act_len;
+	u8 pid;
+	/* For CONTROL endpoint pid should start with DATA1 */
+	int status_direction;
+
+	if (devnum == priv->root_hub_devnum) {
+		udev->status = 0;
+		udev->speed = USB_SPEED_HIGH;
+		return dwc_otg_submit_rh_msg(priv, udev, pipe, buffer, len,
+					     setup);
+	}
+
+	/* SETUP stage */
+	pid = DWC2_HC_PID_SETUP;
+	do {
+		ret = chunk_msg(priv, udev, pipe, &pid, 0, setup, 8, timeout_ms);
+	} while (ret == -EAGAIN);
+
+	if (ret)
+		return ret;
+
+	/* DATA stage */
+	act_len = 0;
+	if (buffer) {
+		pid = DWC2_HC_PID_DATA1;
+		do {
+			ret = chunk_msg(priv, udev, pipe, &pid, usb_pipein(pipe),
+					buffer, len, timeout_ms);
+			act_len += udev->act_len;
+			buffer += udev->act_len;
+			len -= udev->act_len;
+		} while (ret == -EAGAIN);
+		if (ret)
+			return ret;
+		status_direction = usb_pipeout(pipe);
+	} else {
+		/* No-data CONTROL always ends with an IN transaction */
+		status_direction = 1;
+	}
+
+	/* STATUS stage */
+	pid = DWC2_HC_PID_DATA1;
+	do {
+		ret = chunk_msg(priv, udev, pipe, &pid, status_direction,
+				NULL, 0, timeout_ms);
+	} while (ret == -EAGAIN);
+
+	if (ret)
+		return ret;
+
+	udev->act_len = act_len;
+
+	return 0;
+}
+
+static int dwc2_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
+				void *buffer, int len, int timeout_ms)
+{
+	struct usb_host *host = udev->host;
+	struct dwc2_priv *priv = to_dwc2(host);
+	int devnum = usb_pipedevice(pipe);
+	int ep = usb_pipeendpoint(pipe);
+	u8* pid;
+
+	if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
+		udev->status = 0;
+		return -EINVAL;
+	}
+
+	if (usb_pipein(pipe))
+		pid = &priv->in_data_toggle[devnum][ep];
+	else
+		pid = &priv->out_data_toggle[devnum][ep];
+
+	return chunk_msg(priv, udev, pipe, pid, usb_pipein(pipe), buffer, len,
+			 timeout_ms);
+}
+
+static int dwc2_submit_int_msg(struct usb_device *udev, unsigned long pipe,
+			       void *buffer, int len, int interval)
+{
+	uint64_t start;
+	int ret;
+
+	start = get_time_ns();
+
+	while (1) {
+		ret = dwc2_submit_bulk_msg(udev, pipe, buffer, len, 0);
+		if (ret != -EAGAIN)
+			return ret;
+		if (is_timeout(start, USB_CNTL_TIMEOUT * MSECOND))
+			return -ETIMEDOUT;
+	}
+}
+
+static int dwc2_detect(struct device_d *dev)
+{
+	struct dwc2_priv *priv = dev->priv;
+
+        return usb_host_detect(&priv->host);
+}
+
+static int dwc2_probe(struct device_d *dev)
+{
+	struct resource *iores;
+	struct dwc2_priv *priv;
+	struct usb_host *host;
+	struct device_node *np = dev->device_node;
+	int ret;
+	uint32_t snpsid;
+
+	priv = xzalloc(sizeof(*priv));
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+
+	priv->regs = IOMEM(iores->start);
+	priv->dev = dev;
+
+	snpsid = readl(&priv->regs->gsnpsid);
+	dev_info(dev, "Core Release: %x.%03x\n",
+		 snpsid >> 12 & 0xf, snpsid & 0xfff);
+
+	if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
+	    (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
+		dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
+			 snpsid);
+		return -ENODEV;
+	}
+
+	priv->oc_disable = of_property_read_bool(np, "disable-over-current");
+	priv->hnp_srp_disable = of_property_read_bool(np, "hnp-srp-disable");
+	priv->dmabuf = dma_alloc(DWC2_DATA_BUF_SIZE);
+
+	host = &priv->host;
+
+	host->init = dwc2_init_common;
+	host->submit_int_msg = dwc2_submit_int_msg;
+	host->submit_control_msg = dwc2_submit_control_msg;
+	host->submit_bulk_msg = dwc2_submit_bulk_msg;
+
+	dev->priv = priv;
+	dev->detect = dwc2_detect;
+
+	ret = usb_register_host(host);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void dwc2_remove(struct device_d *dev)
+{
+	struct dwc2_priv *priv = dev->priv;
+
+	dwc2_uninit_common(priv->regs);
+}
+
+static const struct of_device_id dwc2_dt_ids[] = {
+	{ .compatible = "brcm,bcm2835-usb" },
+	{ .compatible = "brcm,bcm2708-usb" },
+	{ .compatible = "snps,dwc2" },
+	{ /* sentinel */ }
+};
+
+static struct driver_d dwc2_driver = {
+	.name = "dwc2",
+	.probe = dwc2_probe,
+	.remove = dwc2_remove,
+	.of_compatible = DRV_OF_COMPAT(dwc2_dt_ids),
+};
+device_platform_driver(dwc2_driver);
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
new file mode 100644
index 0000000000..bdf338f1ed
--- /dev/null
+++ b/drivers/usb/host/dwc2.h
@@ -0,0 +1,778 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __DWC2_H__
+#define __DWC2_H__
+
+struct dwc2_hc_regs {
+	u32			hcchar;		/* 0x00 */
+	u32			hcsplt;
+	u32			hcint;
+	u32			hcintmsk;
+	u32			hctsiz;		/* 0x10 */
+	u32			hcdma;
+	u32			reserved;
+	u32			hcdmab;
+};
+
+struct dwc2_host_regs {
+	u32			hcfg;		/* 0x00 */
+	u32			hfir;
+	u32			hfnum;
+	u32			_pad_0x40c;
+	u32			hptxsts;	/* 0x10 */
+	u32			haint;
+	u32			haintmsk;
+	u32			hflbaddr;
+};
+
+struct dwc2_core_regs {
+	u32			gotgctl;	/* 0x000 */
+	u32			gotgint;
+	u32			gahbcfg;
+	u32			gusbcfg;
+	u32			grstctl;	/* 0x010 */
+	u32			gintsts;
+	u32			gintmsk;
+	u32			grxstsr;
+	u32			grxstsp;	/* 0x020 */
+	u32			grxfsiz;
+	u32			gnptxfsiz;
+	u32			gnptxsts;
+	u32			gi2cctl;	/* 0x030 */
+	u32			gpvndctl;
+	u32			ggpio;
+	u32			guid;
+	u32			gsnpsid;	/* 0x040 */
+	u32			ghwcfg1;
+	u32			ghwcfg2;
+	u32			ghwcfg3;
+	u32			ghwcfg4;	/* 0x050 */
+	u32			glpmcfg;
+	u32			_pad_0x58_0x9c[42];
+	u32			hptxfsiz;	/* 0x100 */
+	u32			dptxfsiz_dieptxf[15];
+	u32			_pad_0x140_0x3fc[176];
+	struct dwc2_host_regs	host_regs;	/* 0x400 */
+	u32			_pad_0x420_0x43c[8];
+	u32			hprt0;		/* 0x440 */
+	u32			_pad_0x444_0x4fc[47];
+	struct dwc2_hc_regs	hc_regs[16];	/* 0x500 */
+	u32			_pad_0x700_0xe00[448];
+	u32			pcgcctl;	/* 0xe00 */
+};
+
+#define DWC2_GOTGCTL_SESREQSCS				(1 << 0)
+#define DWC2_GOTGCTL_SESREQSCS_OFFSET			0
+#define DWC2_GOTGCTL_SESREQ				(1 << 1)
+#define DWC2_GOTGCTL_SESREQ_OFFSET			1
+#define DWC2_GOTGCTL_HSTNEGSCS				(1 << 8)
+#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET			8
+#define DWC2_GOTGCTL_HNPREQ				(1 << 9)
+#define DWC2_GOTGCTL_HNPREQ_OFFSET			9
+#define DWC2_GOTGCTL_HSTSETHNPEN			(1 << 10)
+#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET			10
+#define DWC2_GOTGCTL_DEVHNPEN				(1 << 11)
+#define DWC2_GOTGCTL_DEVHNPEN_OFFSET			11
+#define DWC2_GOTGCTL_CONIDSTS				(1 << 16)
+#define DWC2_GOTGCTL_CONIDSTS_OFFSET			16
+#define DWC2_GOTGCTL_DBNCTIME				(1 << 17)
+#define DWC2_GOTGCTL_DBNCTIME_OFFSET			17
+#define DWC2_GOTGCTL_ASESVLD				(1 << 18)
+#define DWC2_GOTGCTL_ASESVLD_OFFSET			18
+#define DWC2_GOTGCTL_BSESVLD				(1 << 19)
+#define DWC2_GOTGCTL_BSESVLD_OFFSET			19
+#define DWC2_GOTGCTL_OTGVER				(1 << 20)
+#define DWC2_GOTGCTL_OTGVER_OFFSET			20
+#define DWC2_GOTGINT_SESENDDET				(1 << 2)
+#define DWC2_GOTGINT_SESENDDET_OFFSET			2
+#define DWC2_GOTGINT_SESREQSUCSTSCHNG			(1 << 8)
+#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET		8
+#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG			(1 << 9)
+#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET		9
+#define DWC2_GOTGINT_RESERVER10_16_MASK			(0x7F << 10)
+#define DWC2_GOTGINT_RESERVER10_16_OFFSET		10
+#define DWC2_GOTGINT_HSTNEGDET				(1 << 17)
+#define DWC2_GOTGINT_HSTNEGDET_OFFSET			17
+#define DWC2_GOTGINT_ADEVTOUTCHNG			(1 << 18)
+#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET		18
+#define DWC2_GOTGINT_DEBDONE				(1 << 19)
+#define DWC2_GOTGINT_DEBDONE_OFFSET			19
+#define DWC2_GAHBCFG_GLBLINTRMSK			(1 << 0)
+#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET			0
+#define DWC2_GAHBCFG_HBURSTLEN_SINGLE			(0 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR			(1 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR4			(3 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR8			(5 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR16			(7 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_MASK			(0xF << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_OFFSET			1
+#define DWC2_GAHBCFG_DMAENABLE				(1 << 5)
+#define DWC2_GAHBCFG_DMAENABLE_OFFSET			5
+#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL		(1 << 7)
+#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET	7
+#define DWC2_GAHBCFG_PTXFEMPLVL				(1 << 8)
+#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET			8
+#define DWC2_GUSBCFG_TOUTCAL_MASK			(0x7 << 0)
+#define DWC2_GUSBCFG_TOUTCAL_OFFSET			0
+#define DWC2_GUSBCFG_PHYIF				(1 << 3)
+#define DWC2_GUSBCFG_PHYIF_OFFSET			3
+#define DWC2_GUSBCFG_ULPI_UTMI_SEL			(1 << 4)
+#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET		4
+#define DWC2_GUSBCFG_FSINTF				(1 << 5)
+#define DWC2_GUSBCFG_FSINTF_OFFSET			5
+#define DWC2_GUSBCFG_PHYSEL				(1 << 6)
+#define DWC2_GUSBCFG_PHYSEL_OFFSET			6
+#define DWC2_GUSBCFG_DDRSEL				(1 << 7)
+#define DWC2_GUSBCFG_DDRSEL_OFFSET			7
+#define DWC2_GUSBCFG_SRPCAP				(1 << 8)
+#define DWC2_GUSBCFG_SRPCAP_OFFSET			8
+#define DWC2_GUSBCFG_HNPCAP				(1 << 9)
+#define DWC2_GUSBCFG_HNPCAP_OFFSET			9
+#define DWC2_GUSBCFG_USBTRDTIM_MASK			(0xF << 10)
+#define DWC2_GUSBCFG_USBTRDTIM_OFFSET			10
+#define DWC2_GUSBCFG_NPTXFRWNDEN			(1 << 14)
+#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET			14
+#define DWC2_GUSBCFG_PHYLPWRCLKSEL			(1 << 15)
+#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET		15
+#define DWC2_GUSBCFG_OTGUTMIFSSEL			(1 << 16)
+#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET		16
+#define DWC2_GUSBCFG_ULPI_FSLS				(1 << 17)
+#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET			17
+#define DWC2_GUSBCFG_ULPI_AUTO_RES			(1 << 18)
+#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET		18
+#define DWC2_GUSBCFG_ULPI_CLK_SUS_M			(1 << 19)
+#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET		19
+#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV			(1 << 20)
+#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET		20
+#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR		(1 << 21)
+#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET	21
+#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE			(1 << 22)
+#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET		22
+#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH		(1 << 24)
+#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH_OFFSET	24
+#define DWC2_GUSBCFG_IC_USB_CAP				(1 << 26)
+#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET			26
+#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE		(1 << 27)
+#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET	27
+#define DWC2_GUSBCFG_TX_END_DELAY			(1 << 28)
+#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET		28
+#define DWC2_GUSBCFG_FORCEHOSTMODE			(1 << 29)
+#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET		29
+#define DWC2_GUSBCFG_FORCEDEVMODE			(1 << 30)
+#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET		30
+#define DWC2_GLPMCTL_LPM_CAP_EN				(1 << 0)
+#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET			0
+#define DWC2_GLPMCTL_APPL_RESP				(1 << 1)
+#define DWC2_GLPMCTL_APPL_RESP_OFFSET			1
+#define DWC2_GLPMCTL_HIRD_MASK				(0xF << 2)
+#define DWC2_GLPMCTL_HIRD_OFFSET			2
+#define DWC2_GLPMCTL_REM_WKUP_EN			(1 << 6)
+#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET			6
+#define DWC2_GLPMCTL_EN_UTMI_SLEEP			(1 << 7)
+#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET		7
+#define DWC2_GLPMCTL_HIRD_THRES_MASK			(0x1F << 8)
+#define DWC2_GLPMCTL_HIRD_THRES_OFFSET			8
+#define DWC2_GLPMCTL_LPM_RESP_MASK			(0x3 << 13)
+#define DWC2_GLPMCTL_LPM_RESP_OFFSET			13
+#define DWC2_GLPMCTL_PRT_SLEEP_STS			(1 << 15)
+#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET		15
+#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK		(1 << 16)
+#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET	16
+#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK		(0xF << 17)
+#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET		17
+#define DWC2_GLPMCTL_RETRY_COUNT_MASK			(0x7 << 21)
+#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET			21
+#define DWC2_GLPMCTL_SEND_LPM				(1 << 24)
+#define DWC2_GLPMCTL_SEND_LPM_OFFSET			24
+#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK		(0x7 << 25)
+#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET		25
+#define DWC2_GLPMCTL_HSIC_CONNECT			(1 << 30)
+#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET		30
+#define DWC2_GLPMCTL_INV_SEL_HSIC			(1 << 31)
+#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET		31
+#define DWC2_GRSTCTL_CSFTRST				(1 << 0)
+#define DWC2_GRSTCTL_CSFTRST_OFFSET			0
+#define DWC2_GRSTCTL_HSFTRST				(1 << 1)
+#define DWC2_GRSTCTL_HSFTRST_OFFSET			1
+#define DWC2_GRSTCTL_HSTFRM				(1 << 2)
+#define DWC2_GRSTCTL_HSTFRM_OFFSET			2
+#define DWC2_GRSTCTL_INTKNQFLSH				(1 << 3)
+#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET			3
+#define DWC2_GRSTCTL_RXFFLSH				(1 << 4)
+#define DWC2_GRSTCTL_RXFFLSH_OFFSET			4
+#define DWC2_GRSTCTL_TXFFLSH				(1 << 5)
+#define DWC2_GRSTCTL_TXFFLSH_OFFSET			5
+#define DWC2_GRSTCTL_TXFNUM_MASK			(0x1F << 6)
+#define DWC2_GRSTCTL_TXFNUM_OFFSET			6
+#define DWC2_GRSTCTL_DMAREQ				(1 << 30)
+#define DWC2_GRSTCTL_DMAREQ_OFFSET			30
+#define DWC2_GRSTCTL_AHBIDLE				(1 << 31)
+#define DWC2_GRSTCTL_AHBIDLE_OFFSET			31
+#define DWC2_GINTMSK_MODEMISMATCH			(1 << 1)
+#define DWC2_GINTMSK_MODEMISMATCH_OFFSET		1
+#define DWC2_GINTMSK_OTGINTR				(1 << 2)
+#define DWC2_GINTMSK_OTGINTR_OFFSET			2
+#define DWC2_GINTMSK_SOFINTR				(1 << 3)
+#define DWC2_GINTMSK_SOFINTR_OFFSET			3
+#define DWC2_GINTMSK_RXSTSQLVL				(1 << 4)
+#define DWC2_GINTMSK_RXSTSQLVL_OFFSET			4
+#define DWC2_GINTMSK_NPTXFEMPTY				(1 << 5)
+#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET			5
+#define DWC2_GINTMSK_GINNAKEFF				(1 << 6)
+#define DWC2_GINTMSK_GINNAKEFF_OFFSET			6
+#define DWC2_GINTMSK_GOUTNAKEFF				(1 << 7)
+#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET			7
+#define DWC2_GINTMSK_I2CINTR				(1 << 9)
+#define DWC2_GINTMSK_I2CINTR_OFFSET			9
+#define DWC2_GINTMSK_ERLYSUSPEND			(1 << 10)
+#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET			10
+#define DWC2_GINTMSK_USBSUSPEND				(1 << 11)
+#define DWC2_GINTMSK_USBSUSPEND_OFFSET			11
+#define DWC2_GINTMSK_USBRESET				(1 << 12)
+#define DWC2_GINTMSK_USBRESET_OFFSET			12
+#define DWC2_GINTMSK_ENUMDONE				(1 << 13)
+#define DWC2_GINTMSK_ENUMDONE_OFFSET			13
+#define DWC2_GINTMSK_ISOOUTDROP				(1 << 14)
+#define DWC2_GINTMSK_ISOOUTDROP_OFFSET			14
+#define DWC2_GINTMSK_EOPFRAME				(1 << 15)
+#define DWC2_GINTMSK_EOPFRAME_OFFSET			15
+#define DWC2_GINTMSK_EPMISMATCH				(1 << 17)
+#define DWC2_GINTMSK_EPMISMATCH_OFFSET			17
+#define DWC2_GINTMSK_INEPINTR				(1 << 18)
+#define DWC2_GINTMSK_INEPINTR_OFFSET			18
+#define DWC2_GINTMSK_OUTEPINTR				(1 << 19)
+#define DWC2_GINTMSK_OUTEPINTR_OFFSET			19
+#define DWC2_GINTMSK_INCOMPLISOIN			(1 << 20)
+#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET		20
+#define DWC2_GINTMSK_INCOMPLISOOUT			(1 << 21)
+#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET		21
+#define DWC2_GINTMSK_PORTINTR				(1 << 24)
+#define DWC2_GINTMSK_PORTINTR_OFFSET			24
+#define DWC2_GINTMSK_HCINTR				(1 << 25)
+#define DWC2_GINTMSK_HCINTR_OFFSET			25
+#define DWC2_GINTMSK_PTXFEMPTY				(1 << 26)
+#define DWC2_GINTMSK_PTXFEMPTY_OFFSET			26
+#define DWC2_GINTMSK_LPMTRANRCVD			(1 << 27)
+#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET			27
+#define DWC2_GINTMSK_CONIDSTSCHNG			(1 << 28)
+#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET		28
+#define DWC2_GINTMSK_DISCONNECT				(1 << 29)
+#define DWC2_GINTMSK_DISCONNECT_OFFSET			29
+#define DWC2_GINTMSK_SESSREQINTR			(1 << 30)
+#define DWC2_GINTMSK_SESSREQINTR_OFFSET			30
+#define DWC2_GINTMSK_WKUPINTR				(1 << 31)
+#define DWC2_GINTMSK_WKUPINTR_OFFSET			31
+#define DWC2_GINTSTS_CURMODE_DEVICE			(0 << 0)
+#define DWC2_GINTSTS_CURMODE_HOST			(1 << 0)
+#define DWC2_GINTSTS_CURMODE				(1 << 0)
+#define DWC2_GINTSTS_CURMODE_OFFSET			0
+#define DWC2_GINTSTS_MODEMISMATCH			(1 << 1)
+#define DWC2_GINTSTS_MODEMISMATCH_OFFSET		1
+#define DWC2_GINTSTS_OTGINTR				(1 << 2)
+#define DWC2_GINTSTS_OTGINTR_OFFSET			2
+#define DWC2_GINTSTS_SOFINTR				(1 << 3)
+#define DWC2_GINTSTS_SOFINTR_OFFSET			3
+#define DWC2_GINTSTS_RXSTSQLVL				(1 << 4)
+#define DWC2_GINTSTS_RXSTSQLVL_OFFSET			4
+#define DWC2_GINTSTS_NPTXFEMPTY				(1 << 5)
+#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET			5
+#define DWC2_GINTSTS_GINNAKEFF				(1 << 6)
+#define DWC2_GINTSTS_GINNAKEFF_OFFSET			6
+#define DWC2_GINTSTS_GOUTNAKEFF				(1 << 7)
+#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET			7
+#define DWC2_GINTSTS_I2CINTR				(1 << 9)
+#define DWC2_GINTSTS_I2CINTR_OFFSET			9
+#define DWC2_GINTSTS_ERLYSUSPEND			(1 << 10)
+#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET			10
+#define DWC2_GINTSTS_USBSUSPEND				(1 << 11)
+#define DWC2_GINTSTS_USBSUSPEND_OFFSET			11
+#define DWC2_GINTSTS_USBRESET				(1 << 12)
+#define DWC2_GINTSTS_USBRESET_OFFSET			12
+#define DWC2_GINTSTS_ENUMDONE				(1 << 13)
+#define DWC2_GINTSTS_ENUMDONE_OFFSET			13
+#define DWC2_GINTSTS_ISOOUTDROP				(1 << 14)
+#define DWC2_GINTSTS_ISOOUTDROP_OFFSET			14
+#define DWC2_GINTSTS_EOPFRAME				(1 << 15)
+#define DWC2_GINTSTS_EOPFRAME_OFFSET			15
+#define DWC2_GINTSTS_INTOKENRX				(1 << 16)
+#define DWC2_GINTSTS_INTOKENRX_OFFSET			16
+#define DWC2_GINTSTS_EPMISMATCH				(1 << 17)
+#define DWC2_GINTSTS_EPMISMATCH_OFFSET			17
+#define DWC2_GINTSTS_INEPINT				(1 << 18)
+#define DWC2_GINTSTS_INEPINT_OFFSET			18
+#define DWC2_GINTSTS_OUTEPINTR				(1 << 19)
+#define DWC2_GINTSTS_OUTEPINTR_OFFSET			19
+#define DWC2_GINTSTS_INCOMPLISOIN			(1 << 20)
+#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET		20
+#define DWC2_GINTSTS_INCOMPLISOOUT			(1 << 21)
+#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET		21
+#define DWC2_GINTSTS_PORTINTR				(1 << 24)
+#define DWC2_GINTSTS_PORTINTR_OFFSET			24
+#define DWC2_GINTSTS_HCINTR				(1 << 25)
+#define DWC2_GINTSTS_HCINTR_OFFSET			25
+#define DWC2_GINTSTS_PTXFEMPTY				(1 << 26)
+#define DWC2_GINTSTS_PTXFEMPTY_OFFSET			26
+#define DWC2_GINTSTS_LPMTRANRCVD			(1 << 27)
+#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET			27
+#define DWC2_GINTSTS_CONIDSTSCHNG			(1 << 28)
+#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET		28
+#define DWC2_GINTSTS_DISCONNECT				(1 << 29)
+#define DWC2_GINTSTS_DISCONNECT_OFFSET			29
+#define DWC2_GINTSTS_SESSREQINTR			(1 << 30)
+#define DWC2_GINTSTS_SESSREQINTR_OFFSET			30
+#define DWC2_GINTSTS_WKUPINTR				(1 << 31)
+#define DWC2_GINTSTS_WKUPINTR_OFFSET			31
+#define DWC2_GRXSTS_EPNUM_MASK				(0xF << 0)
+#define DWC2_GRXSTS_EPNUM_OFFSET			0
+#define DWC2_GRXSTS_BCNT_MASK				(0x7FF << 4)
+#define DWC2_GRXSTS_BCNT_OFFSET				4
+#define DWC2_GRXSTS_DPID_MASK				(0x3 << 15)
+#define DWC2_GRXSTS_DPID_OFFSET				15
+#define DWC2_GRXSTS_PKTSTS_MASK				(0xF << 17)
+#define DWC2_GRXSTS_PKTSTS_OFFSET			17
+#define DWC2_GRXSTS_FN_MASK				(0xF << 21)
+#define DWC2_GRXSTS_FN_OFFSET				21
+#define DWC2_FIFOSIZE_STARTADDR_MASK			(0xFFFF << 0)
+#define DWC2_FIFOSIZE_STARTADDR_OFFSET			0
+#define DWC2_FIFOSIZE_DEPTH_MASK			(0xFFFF << 16)
+#define DWC2_FIFOSIZE_DEPTH_OFFSET			16
+#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK		(0xFFFF << 0)
+#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET		0
+#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK		(0xFF << 16)
+#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET		16
+#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE		(1 << 24)
+#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET		24
+#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK		(0x3 << 25)
+#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET		25
+#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK		(0xF << 27)
+#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET		27
+#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK			(0xFFFF << 0)
+#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET			0
+#define DWC2_GI2CCTL_RWDATA_MASK			(0xFF << 0)
+#define DWC2_GI2CCTL_RWDATA_OFFSET			0
+#define DWC2_GI2CCTL_REGADDR_MASK			(0xFF << 8)
+#define DWC2_GI2CCTL_REGADDR_OFFSET			8
+#define DWC2_GI2CCTL_ADDR_MASK				(0x7F << 16)
+#define DWC2_GI2CCTL_ADDR_OFFSET			16
+#define DWC2_GI2CCTL_I2CEN				(1 << 23)
+#define DWC2_GI2CCTL_I2CEN_OFFSET			23
+#define DWC2_GI2CCTL_ACK				(1 << 24)
+#define DWC2_GI2CCTL_ACK_OFFSET				24
+#define DWC2_GI2CCTL_I2CSUSPCTL				(1 << 25)
+#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET			25
+#define DWC2_GI2CCTL_I2CDEVADDR_MASK			(0x3 << 26)
+#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET			26
+#define DWC2_GI2CCTL_RW					(1 << 30)
+#define DWC2_GI2CCTL_RW_OFFSET				30
+#define DWC2_GI2CCTL_BSYDNE				(1 << 31)
+#define DWC2_GI2CCTL_BSYDNE_OFFSET			31
+#define DWC2_HWCFG1_EP_DIR0_MASK			(0x3 << 0)
+#define DWC2_HWCFG1_EP_DIR0_OFFSET			0
+#define DWC2_HWCFG1_EP_DIR1_MASK			(0x3 << 2)
+#define DWC2_HWCFG1_EP_DIR1_OFFSET			2
+#define DWC2_HWCFG1_EP_DIR2_MASK			(0x3 << 4)
+#define DWC2_HWCFG1_EP_DIR2_OFFSET			4
+#define DWC2_HWCFG1_EP_DIR3_MASK			(0x3 << 6)
+#define DWC2_HWCFG1_EP_DIR3_OFFSET			6
+#define DWC2_HWCFG1_EP_DIR4_MASK			(0x3 << 8)
+#define DWC2_HWCFG1_EP_DIR4_OFFSET			8
+#define DWC2_HWCFG1_EP_DIR5_MASK			(0x3 << 10)
+#define DWC2_HWCFG1_EP_DIR5_OFFSET			10
+#define DWC2_HWCFG1_EP_DIR6_MASK			(0x3 << 12)
+#define DWC2_HWCFG1_EP_DIR6_OFFSET			12
+#define DWC2_HWCFG1_EP_DIR7_MASK			(0x3 << 14)
+#define DWC2_HWCFG1_EP_DIR7_OFFSET			14
+#define DWC2_HWCFG1_EP_DIR8_MASK			(0x3 << 16)
+#define DWC2_HWCFG1_EP_DIR8_OFFSET			16
+#define DWC2_HWCFG1_EP_DIR9_MASK			(0x3 << 18)
+#define DWC2_HWCFG1_EP_DIR9_OFFSET			18
+#define DWC2_HWCFG1_EP_DIR10_MASK			(0x3 << 20)
+#define DWC2_HWCFG1_EP_DIR10_OFFSET			20
+#define DWC2_HWCFG1_EP_DIR11_MASK			(0x3 << 22)
+#define DWC2_HWCFG1_EP_DIR11_OFFSET			22
+#define DWC2_HWCFG1_EP_DIR12_MASK			(0x3 << 24)
+#define DWC2_HWCFG1_EP_DIR12_OFFSET			24
+#define DWC2_HWCFG1_EP_DIR13_MASK			(0x3 << 26)
+#define DWC2_HWCFG1_EP_DIR13_OFFSET			26
+#define DWC2_HWCFG1_EP_DIR14_MASK			(0x3 << 28)
+#define DWC2_HWCFG1_EP_DIR14_OFFSET			28
+#define DWC2_HWCFG1_EP_DIR15_MASK			(0x3 << 30)
+#define DWC2_HWCFG1_EP_DIR15_OFFSET			30
+#define DWC2_HWCFG2_OP_MODE_MASK			(0x7 << 0)
+#define DWC2_HWCFG2_OP_MODE_OFFSET			0
+#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY		(0x0 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA		(0x1 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA		(0x2 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_MASK			(0x3 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_OFFSET			3
+#define DWC2_HWCFG2_POINT2POINT				(1 << 5)
+#define DWC2_HWCFG2_POINT2POINT_OFFSET			5
+#define DWC2_HWCFG2_HS_PHY_TYPE_MASK			(0x3 << 6)
+#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET			6
+#define DWC2_HWCFG2_FS_PHY_TYPE_MASK			(0x3 << 8)
+#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET			8
+#define DWC2_HWCFG2_NUM_DEV_EP_MASK			(0xF << 10)
+#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET			10
+#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK			(0xF << 14)
+#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET		14
+#define DWC2_HWCFG2_PERIO_EP_SUPPORTED			(1 << 18)
+#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET		18
+#define DWC2_HWCFG2_DYNAMIC_FIFO			(1 << 19)
+#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET			19
+#define DWC2_HWCFG2_MULTI_PROC_INT			(1 << 20)
+#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET		20
+#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK		(0x3 << 22)
+#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET		22
+#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK		(0x3 << 24)
+#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET	24
+#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1F << 26)
+#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET		26
+#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK		(0xF << 0)
+#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET		0
+#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK		(0x7 << 4)
+#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET	4
+#define DWC2_HWCFG3_OTG_FUNC				(1 << 7)
+#define DWC2_HWCFG3_OTG_FUNC_OFFSET			7
+#define DWC2_HWCFG3_I2C					(1 << 8)
+#define DWC2_HWCFG3_I2C_OFFSET				8
+#define DWC2_HWCFG3_VENDOR_CTRL_IF			(1 << 9)
+#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET		9
+#define DWC2_HWCFG3_OPTIONAL_FEATURES			(1 << 10)
+#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET		10
+#define DWC2_HWCFG3_SYNCH_RESET_TYPE			(1 << 11)
+#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET		11
+#define DWC2_HWCFG3_OTG_ENABLE_IC_USB			(1 << 12)
+#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET		12
+#define DWC2_HWCFG3_OTG_ENABLE_HSIC			(1 << 13)
+#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET		13
+#define DWC2_HWCFG3_OTG_LPM_EN				(1 << 15)
+#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET			15
+#define DWC2_HWCFG3_DFIFO_DEPTH_MASK			(0xFFFF << 16)
+#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET			16
+#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK		(0xF << 0)
+#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET		0
+#define DWC2_HWCFG4_POWER_OPTIMIZ			(1 << 4)
+#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET		4
+#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK			(0x1FF << 5)
+#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET			5
+#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK		(0x3 << 14)
+#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET		14
+#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK		(0xF << 16)
+#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET		16
+#define DWC2_HWCFG4_IDDIG_FILT_EN			(1 << 20)
+#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET		20
+#define DWC2_HWCFG4_VBUS_VALID_FILT_EN			(1 << 21)
+#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET		21
+#define DWC2_HWCFG4_A_VALID_FILT_EN			(1 << 22)
+#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET		22
+#define DWC2_HWCFG4_B_VALID_FILT_EN			(1 << 23)
+#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET		23
+#define DWC2_HWCFG4_SESSION_END_FILT_EN			(1 << 24)
+#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET		24
+#define DWC2_HWCFG4_DED_FIFO_EN				(1 << 25)
+#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET			25
+#define DWC2_HWCFG4_NUM_IN_EPS_MASK			(0xF << 26)
+#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET			26
+#define DWC2_HWCFG4_DESC_DMA				(1 << 30)
+#define DWC2_HWCFG4_DESC_DMA_OFFSET			30
+#define DWC2_HWCFG4_DESC_DMA_DYN			(1 << 31)
+#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET			31
+#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ			0
+#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ			1
+#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ			2
+#define DWC2_HCFG_FSLSPCLKSEL_MASK			(0x3 << 0)
+#define DWC2_HCFG_FSLSPCLKSEL_OFFSET			0
+#define DWC2_HCFG_FSLSSUPP				(1 << 2)
+#define DWC2_HCFG_FSLSSUPP_OFFSET			2
+#define DWC2_HCFG_DESCDMA				(1 << 23)
+#define DWC2_HCFG_DESCDMA_OFFSET			23
+#define DWC2_HCFG_FRLISTEN_MASK				(0x3 << 24)
+#define DWC2_HCFG_FRLISTEN_OFFSET			24
+#define DWC2_HCFG_PERSCHEDENA				(1 << 26)
+#define DWC2_HCFG_PERSCHEDENA_OFFSET			26
+#define DWC2_HCFG_PERSCHEDSTAT				(1 << 27)
+#define DWC2_HCFG_PERSCHEDSTAT_OFFSET			27
+#define DWC2_HFIR_FRINT_MASK				(0xFFFF << 0)
+#define DWC2_HFIR_FRINT_OFFSET				0
+#define DWC2_HFNUM_FRNUM_MASK				(0xFFFF << 0)
+#define DWC2_HFNUM_FRNUM_OFFSET				0
+#define DWC2_HFNUM_FRREM_MASK				(0xFFFF << 16)
+#define DWC2_HFNUM_FRREM_OFFSET				16
+#define DWC2_HFNUM_MAX_FRNUM				0x3FFF
+#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK			(0xFFFF << 0)
+#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET		0
+#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK			(0xFF << 16)
+#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET		16
+#define DWC2_HPTXSTS_PTXQTOP_TERMINATE			(1 << 24)
+#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET		24
+#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK			(0x3 << 25)
+#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET		25
+#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK			(0xF << 27)
+#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET		27
+#define DWC2_HPTXSTS_PTXQTOP_ODD			(1 << 31)
+#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET			31
+#define DWC2_HPRT0_PRTCONNSTS				(1 << 0)
+#define DWC2_HPRT0_PRTCONNSTS_OFFSET			0
+#define DWC2_HPRT0_PRTCONNDET				(1 << 1)
+#define DWC2_HPRT0_PRTCONNDET_OFFSET			1
+#define DWC2_HPRT0_PRTENA				(1 << 2)
+#define DWC2_HPRT0_PRTENA_OFFSET			2
+#define DWC2_HPRT0_PRTENCHNG				(1 << 3)
+#define DWC2_HPRT0_PRTENCHNG_OFFSET			3
+#define DWC2_HPRT0_PRTOVRCURRACT			(1 << 4)
+#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET			4
+#define DWC2_HPRT0_PRTOVRCURRCHNG			(1 << 5)
+#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET		5
+#define DWC2_HPRT0_PRTRES				(1 << 6)
+#define DWC2_HPRT0_PRTRES_OFFSET			6
+#define DWC2_HPRT0_PRTSUSP				(1 << 7)
+#define DWC2_HPRT0_PRTSUSP_OFFSET			7
+#define DWC2_HPRT0_PRTRST				(1 << 8)
+#define DWC2_HPRT0_PRTRST_OFFSET			8
+#define DWC2_HPRT0_PRTLNSTS_MASK			(0x3 << 10)
+#define DWC2_HPRT0_PRTLNSTS_OFFSET			10
+#define DWC2_HPRT0_PRTPWR				(1 << 12)
+#define DWC2_HPRT0_PRTPWR_OFFSET			12
+#define DWC2_HPRT0_PRTTSTCTL_MASK			(0xF << 13)
+#define DWC2_HPRT0_PRTTSTCTL_OFFSET			13
+#define DWC2_HPRT0_PRTSPD_HIGH				(0 << 17)
+#define DWC2_HPRT0_PRTSPD_FULL				(1 << 17)
+#define DWC2_HPRT0_PRTSPD_LOW				(2 << 17)
+#define DWC2_HPRT0_PRTSPD_MASK				(0x3 << 17)
+#define DWC2_HPRT0_PRTSPD_OFFSET			17
+#define DWC2_HAINT_CH0					(1 << 0)
+#define DWC2_HAINT_CH0_OFFSET				0
+#define DWC2_HAINT_CH1					(1 << 1)
+#define DWC2_HAINT_CH1_OFFSET				1
+#define DWC2_HAINT_CH2					(1 << 2)
+#define DWC2_HAINT_CH2_OFFSET				2
+#define DWC2_HAINT_CH3					(1 << 3)
+#define DWC2_HAINT_CH3_OFFSET				3
+#define DWC2_HAINT_CH4					(1 << 4)
+#define DWC2_HAINT_CH4_OFFSET				4
+#define DWC2_HAINT_CH5					(1 << 5)
+#define DWC2_HAINT_CH5_OFFSET				5
+#define DWC2_HAINT_CH6					(1 << 6)
+#define DWC2_HAINT_CH6_OFFSET				6
+#define DWC2_HAINT_CH7					(1 << 7)
+#define DWC2_HAINT_CH7_OFFSET				7
+#define DWC2_HAINT_CH8					(1 << 8)
+#define DWC2_HAINT_CH8_OFFSET				8
+#define DWC2_HAINT_CH9					(1 << 9)
+#define DWC2_HAINT_CH9_OFFSET				9
+#define DWC2_HAINT_CH10					(1 << 10)
+#define DWC2_HAINT_CH10_OFFSET				10
+#define DWC2_HAINT_CH11					(1 << 11)
+#define DWC2_HAINT_CH11_OFFSET				11
+#define DWC2_HAINT_CH12					(1 << 12)
+#define DWC2_HAINT_CH12_OFFSET				12
+#define DWC2_HAINT_CH13					(1 << 13)
+#define DWC2_HAINT_CH13_OFFSET				13
+#define DWC2_HAINT_CH14					(1 << 14)
+#define DWC2_HAINT_CH14_OFFSET				14
+#define DWC2_HAINT_CH15					(1 << 15)
+#define DWC2_HAINT_CH15_OFFSET				15
+#define DWC2_HAINT_CHINT_MASK				0xffff
+#define DWC2_HAINT_CHINT_OFFSET				0
+#define DWC2_HAINTMSK_CH0				(1 << 0)
+#define DWC2_HAINTMSK_CH0_OFFSET			0
+#define DWC2_HAINTMSK_CH1				(1 << 1)
+#define DWC2_HAINTMSK_CH1_OFFSET			1
+#define DWC2_HAINTMSK_CH2				(1 << 2)
+#define DWC2_HAINTMSK_CH2_OFFSET			2
+#define DWC2_HAINTMSK_CH3				(1 << 3)
+#define DWC2_HAINTMSK_CH3_OFFSET			3
+#define DWC2_HAINTMSK_CH4				(1 << 4)
+#define DWC2_HAINTMSK_CH4_OFFSET			4
+#define DWC2_HAINTMSK_CH5				(1 << 5)
+#define DWC2_HAINTMSK_CH5_OFFSET			5
+#define DWC2_HAINTMSK_CH6				(1 << 6)
+#define DWC2_HAINTMSK_CH6_OFFSET			6
+#define DWC2_HAINTMSK_CH7				(1 << 7)
+#define DWC2_HAINTMSK_CH7_OFFSET			7
+#define DWC2_HAINTMSK_CH8				(1 << 8)
+#define DWC2_HAINTMSK_CH8_OFFSET			8
+#define DWC2_HAINTMSK_CH9				(1 << 9)
+#define DWC2_HAINTMSK_CH9_OFFSET			9
+#define DWC2_HAINTMSK_CH10				(1 << 10)
+#define DWC2_HAINTMSK_CH10_OFFSET			10
+#define DWC2_HAINTMSK_CH11				(1 << 11)
+#define DWC2_HAINTMSK_CH11_OFFSET			11
+#define DWC2_HAINTMSK_CH12				(1 << 12)
+#define DWC2_HAINTMSK_CH12_OFFSET			12
+#define DWC2_HAINTMSK_CH13				(1 << 13)
+#define DWC2_HAINTMSK_CH13_OFFSET			13
+#define DWC2_HAINTMSK_CH14				(1 << 14)
+#define DWC2_HAINTMSK_CH14_OFFSET			14
+#define DWC2_HAINTMSK_CH15				(1 << 15)
+#define DWC2_HAINTMSK_CH15_OFFSET			15
+#define DWC2_HAINTMSK_CHINT_MASK			0xffff
+#define DWC2_HAINTMSK_CHINT_OFFSET			0
+#define DWC2_HCCHAR_MPS_MASK				(0x7FF << 0)
+#define DWC2_HCCHAR_MPS_OFFSET				0
+#define DWC2_HCCHAR_EPNUM_MASK				(0xF << 11)
+#define DWC2_HCCHAR_EPNUM_OFFSET			11
+#define DWC2_HCCHAR_EPDIR				(1 << 15)
+#define DWC2_HCCHAR_EPDIR_OFFSET			15
+#define DWC2_HCCHAR_LSPDDEV				(1 << 17)
+#define DWC2_HCCHAR_LSPDDEV_OFFSET			17
+#define DWC2_HCCHAR_EPTYPE_CONTROL			0
+#define DWC2_HCCHAR_EPTYPE_ISOC				1
+#define DWC2_HCCHAR_EPTYPE_BULK				2
+#define DWC2_HCCHAR_EPTYPE_INTR				3
+#define DWC2_HCCHAR_EPTYPE_MASK				(0x3 << 18)
+#define DWC2_HCCHAR_EPTYPE_OFFSET			18
+#define DWC2_HCCHAR_MULTICNT_MASK			(0x3 << 20)
+#define DWC2_HCCHAR_MULTICNT_OFFSET			20
+#define DWC2_HCCHAR_DEVADDR_MASK			(0x7F << 22)
+#define DWC2_HCCHAR_DEVADDR_OFFSET			22
+#define DWC2_HCCHAR_ODDFRM				(1 << 29)
+#define DWC2_HCCHAR_ODDFRM_OFFSET			29
+#define DWC2_HCCHAR_CHDIS				(1 << 30)
+#define DWC2_HCCHAR_CHDIS_OFFSET			30
+#define DWC2_HCCHAR_CHEN				(1 << 31)
+#define DWC2_HCCHAR_CHEN_OFFSET				31
+#define DWC2_HCSPLT_PRTADDR_MASK			(0x7F << 0)
+#define DWC2_HCSPLT_PRTADDR_OFFSET			0
+#define DWC2_HCSPLT_HUBADDR_MASK			(0x7F << 7)
+#define DWC2_HCSPLT_HUBADDR_OFFSET			7
+#define DWC2_HCSPLT_XACTPOS_MASK			(0x3 << 14)
+#define DWC2_HCSPLT_XACTPOS_OFFSET			14
+#define DWC2_HCSPLT_COMPSPLT				(1 << 16)
+#define DWC2_HCSPLT_COMPSPLT_OFFSET			16
+#define DWC2_HCSPLT_SPLTENA				(1 << 31)
+#define DWC2_HCSPLT_SPLTENA_OFFSET			31
+#define DWC2_HCINT_XFERCOMP				(1 << 0)
+#define DWC2_HCINT_XFERCOMP_OFFSET			0
+#define DWC2_HCINT_CHHLTD				(1 << 1)
+#define DWC2_HCINT_CHHLTD_OFFSET			1
+#define DWC2_HCINT_AHBERR				(1 << 2)
+#define DWC2_HCINT_AHBERR_OFFSET			2
+#define DWC2_HCINT_STALL				(1 << 3)
+#define DWC2_HCINT_STALL_OFFSET				3
+#define DWC2_HCINT_NAK					(1 << 4)
+#define DWC2_HCINT_NAK_OFFSET				4
+#define DWC2_HCINT_ACK					(1 << 5)
+#define DWC2_HCINT_ACK_OFFSET				5
+#define DWC2_HCINT_NYET					(1 << 6)
+#define DWC2_HCINT_NYET_OFFSET				6
+#define DWC2_HCINT_XACTERR				(1 << 7)
+#define DWC2_HCINT_XACTERR_OFFSET			7
+#define DWC2_HCINT_BBLERR				(1 << 8)
+#define DWC2_HCINT_BBLERR_OFFSET			8
+#define DWC2_HCINT_FRMOVRUN				(1 << 9)
+#define DWC2_HCINT_FRMOVRUN_OFFSET			9
+#define DWC2_HCINT_DATATGLERR				(1 << 10)
+#define DWC2_HCINT_DATATGLERR_OFFSET			10
+#define DWC2_HCINT_BNA					(1 << 11)
+#define DWC2_HCINT_BNA_OFFSET				11
+#define DWC2_HCINT_XCS_XACT				(1 << 12)
+#define DWC2_HCINT_XCS_XACT_OFFSET			12
+#define DWC2_HCINT_FRM_LIST_ROLL			(1 << 13)
+#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET			13
+#define DWC2_HCINTMSK_XFERCOMPL				(1 << 0)
+#define DWC2_HCINTMSK_XFERCOMPL_OFFSET			0
+#define DWC2_HCINTMSK_CHHLTD				(1 << 1)
+#define DWC2_HCINTMSK_CHHLTD_OFFSET			1
+#define DWC2_HCINTMSK_AHBERR				(1 << 2)
+#define DWC2_HCINTMSK_AHBERR_OFFSET			2
+#define DWC2_HCINTMSK_STALL				(1 << 3)
+#define DWC2_HCINTMSK_STALL_OFFSET			3
+#define DWC2_HCINTMSK_NAK				(1 << 4)
+#define DWC2_HCINTMSK_NAK_OFFSET			4
+#define DWC2_HCINTMSK_ACK				(1 << 5)
+#define DWC2_HCINTMSK_ACK_OFFSET			5
+#define DWC2_HCINTMSK_NYET				(1 << 6)
+#define DWC2_HCINTMSK_NYET_OFFSET			6
+#define DWC2_HCINTMSK_XACTERR				(1 << 7)
+#define DWC2_HCINTMSK_XACTERR_OFFSET			7
+#define DWC2_HCINTMSK_BBLERR				(1 << 8)
+#define DWC2_HCINTMSK_BBLERR_OFFSET			8
+#define DWC2_HCINTMSK_FRMOVRUN				(1 << 9)
+#define DWC2_HCINTMSK_FRMOVRUN_OFFSET			9
+#define DWC2_HCINTMSK_DATATGLERR			(1 << 10)
+#define DWC2_HCINTMSK_DATATGLERR_OFFSET			10
+#define DWC2_HCINTMSK_BNA				(1 << 11)
+#define DWC2_HCINTMSK_BNA_OFFSET			11
+#define DWC2_HCINTMSK_XCS_XACT				(1 << 12)
+#define DWC2_HCINTMSK_XCS_XACT_OFFSET			12
+#define DWC2_HCINTMSK_FRM_LIST_ROLL			(1 << 13)
+#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET		13
+#define DWC2_HCTSIZ_XFERSIZE_MASK			0x7ffff
+#define DWC2_HCTSIZ_XFERSIZE_OFFSET			0
+#define DWC2_HCTSIZ_SCHINFO_MASK			0xff
+#define DWC2_HCTSIZ_SCHINFO_OFFSET			0
+#define DWC2_HCTSIZ_NTD_MASK				(0xff << 8)
+#define DWC2_HCTSIZ_NTD_OFFSET				8
+#define DWC2_HCTSIZ_PKTCNT_MASK				(0x3ff << 19)
+#define DWC2_HCTSIZ_PKTCNT_OFFSET			19
+#define DWC2_HCTSIZ_PID_MASK				(0x3 << 29)
+#define DWC2_HCTSIZ_PID_OFFSET				29
+#define DWC2_HCTSIZ_DOPNG				(1 << 31)
+#define DWC2_HCTSIZ_DOPNG_OFFSET			31
+#define DWC2_HCDMA_CTD_MASK				(0xFF << 3)
+#define DWC2_HCDMA_CTD_OFFSET				3
+#define DWC2_HCDMA_DMA_ADDR_MASK			(0x1FFFFF << 11)
+#define DWC2_HCDMA_DMA_ADDR_OFFSET			11
+#define DWC2_PCGCCTL_STOPPCLK				(1 << 0)
+#define DWC2_PCGCCTL_STOPPCLK_OFFSET			0
+#define DWC2_PCGCCTL_GATEHCLK				(1 << 1)
+#define DWC2_PCGCCTL_GATEHCLK_OFFSET			1
+#define DWC2_PCGCCTL_PWRCLMP				(1 << 2)
+#define DWC2_PCGCCTL_PWRCLMP_OFFSET			2
+#define DWC2_PCGCCTL_RSTPDWNMODULE			(1 << 3)
+#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET		3
+#define DWC2_PCGCCTL_PHYSUSPENDED			(1 << 4)
+#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET		4
+#define DWC2_PCGCCTL_ENBL_SLEEP_GATING			(1 << 5)
+#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET		5
+#define DWC2_PCGCCTL_PHY_IN_SLEEP			(1 << 6)
+#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET		6
+#define DWC2_PCGCCTL_DEEP_SLEEP				(1 << 7)
+#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET			7
+#define DWC2_SNPSID_DEVID_VER_2xx			(0x4f542 << 12)
+#define DWC2_SNPSID_DEVID_VER_3xx			(0x4f543 << 12)
+#define DWC2_SNPSID_DEVID_MASK				(0xfffff << 12)
+#define DWC2_SNPSID_DEVID_OFFSET			12
+
+/* Host controller specific */
+#define DWC2_HC_PID_DATA0		0
+#define DWC2_HC_PID_DATA2		1
+#define DWC2_HC_PID_DATA1		2
+#define DWC2_HC_PID_MDATA		3
+#define DWC2_HC_PID_SETUP		3
+
+/* roothub.a masks */
+#define RH_A_NDP	(0xff << 0)	/* number of downstream ports */
+#define RH_A_PSM	(1 << 8)	/* power switching mode */
+#define RH_A_NPS	(1 << 9)	/* no power switching */
+#define RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define RH_A_OCPM	(1 << 11)	/* over current protection mode */
+#define RH_A_NOCP	(1 << 12)	/* no over current protection */
+#define RH_A_POTPGT	(0xff << 24)	/* power on to power good time */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff	/* device removable flags */
+#define RH_B_PPCM	0xffff0000	/* port power control mask */
+
+/* Default driver configuration */
+#define CONFIG_DWC2_MAX_CHANNELS		16	/* Max # of EPs */
+#define CONFIG_DWC2_HOST_RX_FIFO_SIZE		(516 + CONFIG_DWC2_MAX_CHANNELS)
+#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE	0x100	/* nPeriodic TX FIFO */
+#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE	0x200	/* Periodic TX FIFO */
+#define CONFIG_DWC2_MAX_TRANSFER_SIZE		65535
+#define CONFIG_DWC2_MAX_PACKET_COUNT		511
+
+#define DWC2_PHY_TYPE_FS		0
+#define DWC2_PHY_TYPE_UTMI		1
+#define DWC2_PHY_TYPE_ULPI		2
+#define CONFIG_DWC2_PHY_TYPE		DWC2_PHY_TYPE_UTMI	/* PHY type */
+#define CONFIG_DWC2_UTMI_WIDTH		8	/* UTMI bus width (8/16) */
+
+#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS		/* ULPI PHY controls VBUS */
+#define CONFIG_DWC2_TX_THR_LENGTH		64
+
+#endif	/* __DWC2_H__ */