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authorSascha Hauer <s.hauer@pengutronix.de>2019-07-18 12:58:27 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-08-06 13:55:03 +0200
commit6b309a2f91dca742a05a53922ff70970f28b428d (patch)
treeb2da19c21e02e02b7294f5c312d3c858e8c7a9f8 /drivers
parent2f1cfea510284f1ab6aa9b7268a4dba28748ee0e (diff)
downloadbarebox-6b309a2f91dca742a05a53922ff70970f28b428d.tar.gz
barebox-6b309a2f91dca742a05a53922ff70970f28b428d.tar.xz
mtd: nand-mxs: Make ecc strength configurable via device tree
According to the binding doc the mxs NAND driver supports the "nand-ecc-strength" and "nand-ecc-step-size" options. This adds support for these options to the driver. The "nand-ecc-step-size" is not really configurable, the only accepted value is 512 so this is merely to sanity check that there's nothing specified that we can't yet support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/nand/nand_mxs.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 7555b1013d..b016c5bff0 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -336,14 +336,31 @@ static int mxs_nand_calc_geo(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct mxs_nand_info *nand_info = chip->priv;
int ecc_chunk_count = mxs_nand_ecc_chunk_cnt(mtd->writesize);
- int ecc_strength;
int gf_len = 13; /* length of Galois Field for non-DDR nand */
+ int max_ecc_strength;
- ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
- / (gf_len * ecc_chunk_count);
+ nand_of_parse_node(mtd, mtd->parent->device_node);
+ max_ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
+ / (gf_len * ecc_chunk_count);
/* We need the minor even number. */
- chip->ecc.strength = rounddown(ecc_strength, 2);
+ max_ecc_strength = rounddown(max_ecc_strength, 2);
+
+ if (chip->ecc.strength) {
+ if (chip->ecc.strength > max_ecc_strength) {
+ dev_err(nand_info->dev, "invalid ecc strength %d (maximum %d)\n",
+ chip->ecc.strength, max_ecc_strength);
+ return -EINVAL;
+ }
+ } else {
+ chip->ecc.strength = max_ecc_strength;
+ }
+
+ if (chip->ecc.size && chip->ecc.size != MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
+ dev_err(nand_info->dev, "invalid ecc size %d, this driver only supports %d\n",
+ chip->ecc.size, MXS_NAND_CHUNK_DATA_CHUNK_SIZE);
+ return -EINVAL;
+ }
chip->ecc.bytes = DIV_ROUND_UP(13 * chip->ecc.strength, 8);
chip->ecc.size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;