diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-27 21:58:41 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-27 21:58:41 +0200 |
commit | 8b0bf1ee077715ceb0535fbda799038ea62baef8 (patch) | |
tree | 2ef39a48cc78e4b2ec9d37643d4f7c6c320f0341 /drivers | |
parent | 67f0e7aedefcb06b38ef50ddd32b0a280bbb10e8 (diff) | |
parent | a66ffa8dab14b82f9f9edddb03d6358b861ff5c0 (diff) | |
download | barebox-8b0bf1ee077715ceb0535fbda799038ea62baef8.tar.gz barebox-8b0bf1ee077715ceb0535fbda799038ea62baef8.tar.xz |
Merge branch 'for-next/misc'
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/vexpress/clk-sp810.c | 4 | ||||
-rw-r--r-- | drivers/i2c/busses/Kconfig | 1 | ||||
-rw-r--r-- | drivers/i2c/busses/i2c-designware.c | 7 | ||||
-rw-r--r-- | drivers/i2c/busses/i2c-versatile.c | 13 | ||||
-rw-r--r-- | drivers/mci/Kconfig | 1 | ||||
-rw-r--r-- | drivers/mci/dw_mmc.c | 3 | ||||
-rw-r--r-- | drivers/mfd/Kconfig | 2 | ||||
-rw-r--r-- | drivers/mfd/rave-sp.c | 5 | ||||
-rw-r--r-- | drivers/mfd/smsc-superio.c | 3 | ||||
-rw-r--r-- | drivers/mtd/ubi/eba.c | 12 | ||||
-rw-r--r-- | drivers/net/designware_generic.c | 5 | ||||
-rw-r--r-- | drivers/net/phy/at803x.c | 178 | ||||
-rw-r--r-- | drivers/net/phy/dp83867.c | 9 | ||||
-rw-r--r-- | drivers/net/phy/marvell.c | 6 | ||||
-rw-r--r-- | drivers/net/phy/micrel.c | 108 | ||||
-rw-r--r-- | drivers/pci/pci-tegra.c | 5 | ||||
-rw-r--r-- | drivers/pwm/core.c | 5 | ||||
-rw-r--r-- | drivers/reset/Kconfig | 1 | ||||
-rw-r--r-- | drivers/serial/serial_pl010.c | 27 | ||||
-rw-r--r-- | drivers/serial/serial_pl010.h | 23 | ||||
-rw-r--r-- | drivers/usb/otg/otgdev.c | 5 | ||||
-rw-r--r-- | drivers/watchdog/f71808e_wdt.c | 59 | ||||
-rw-r--r-- | drivers/watchdog/rave-sp-wdt.c | 5 |
23 files changed, 359 insertions, 128 deletions
diff --git a/drivers/clk/vexpress/clk-sp810.c b/drivers/clk/vexpress/clk-sp810.c index 78ec67fd15..968921203b 100644 --- a/drivers/clk/vexpress/clk-sp810.c +++ b/drivers/clk/vexpress/clk-sp810.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 ARM Limited - */ +// SPDX-FileCopyrightText: 2013 ARM Limited #include <common.h> #include <io.h> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 21d2cb21cf..3bc8d1b8d2 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -59,5 +59,6 @@ config I2C_STM32 bool "STM32 I2C master driver" select RESET_CONTROLLER depends on HAVE_CLK + depends on ARCH_STM32MP || COMPILE_TEST endmenu diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c index 33f89148f0..bb9a0b7c4a 100644 --- a/drivers/i2c/busses/i2c-designware.c +++ b/drivers/i2c/busses/i2c-designware.c @@ -121,6 +121,8 @@ static inline struct dw_i2c_dev *to_dw_i2c_dev(struct i2c_adapter *a) static void i2c_dw_enable(struct dw_i2c_dev *dw, bool enable) { + u32 reg = 0; + /* * This subrotine is an implementation of an algorithm * described in "Cyclone V Hard Processor System Technical @@ -128,12 +130,13 @@ static void i2c_dw_enable(struct dw_i2c_dev *dw, bool enable) */ int timeout = MAX_T_POLL_COUNT; - enable = enable ? DW_IC_ENABLE_ENABLE : 0; + if (enable) + reg |= DW_IC_ENABLE_ENABLE; do { uint32_t ic_enable_status; - writel(enable, dw->base + DW_IC_ENABLE); + writel(reg, dw->base + DW_IC_ENABLE); ic_enable_status = readl(dw->base + DW_IC_ENABLE_STATUS); if ((ic_enable_status & DW_IC_ENABLE_STATUS_IC_EN) == enable) diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index 6a00c2a2eb..ece483f6f5 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c @@ -1,13 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2006 ARM Ltd. + /* - * i2c-versatile.c - * - * Copyright (C) 2006 ARM Ltd. - * written by Russell King, Deep Blue Solutions Ltd. + * i2c-versatile.c * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * written by Russell King, Deep Blue Solutions Ltd. */ + #include <common.h> #include <driver.h> #include <i2c/i2c.h> diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig index 3026b25cad..f7dc5c5089 100644 --- a/drivers/mci/Kconfig +++ b/drivers/mci/Kconfig @@ -177,6 +177,7 @@ config MCI_STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" depends on ARM_AMBA depends on RESET_CONTROLLER + depends on ARCH_STM32MP || COMPILE_TEST help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c index ab8270814b..0ada65e90e 100644 --- a/drivers/mci/dw_mmc.c +++ b/drivers/mci/dw_mmc.c @@ -124,7 +124,7 @@ static int dwmci_prepare_data_dma(struct dwmci_host *host, { unsigned long ctrl; unsigned int i = 0, flags, cnt, blk_cnt; - unsigned long data_start, start_addr; + unsigned start_addr; struct dwmci_idmac *desc = host->idmac; blk_cnt = data->blocks; @@ -134,7 +134,6 @@ static int dwmci_prepare_data_dma(struct dwmci_host *host, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); - data_start = (uint32_t)desc; dwmci_writel(host, DWMCI_DBADDR, (uint32_t)desc); if (data->flags & MMC_DATA_READ) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 42346154e6..d03d481898 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -73,12 +73,14 @@ config MFD_SUPERIO config FINTEK_SUPERIO bool "Fintek Super I/O chip" select MFD_SUPERIO + depends on X86 || COMPILE_TEST help Select this to probe for IO-port connected Fintek Super I/O chips. config SMSC_SUPERIO bool "SMSC Super I/O chip" select MFD_SUPERIO + depends on X86 || COMPILE_TEST help Select this to probe for IO-port connected SMSC Super I/O chips. diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c index c6ad57d517..8fc46b66bb 100644 --- a/drivers/mfd/rave-sp.c +++ b/drivers/mfd/rave-sp.c @@ -787,10 +787,7 @@ static int rave_sp_add_params(struct rave_sp *sp) p = dev_add_param_ip(dev, "netmask", NULL, rave_sp_req_ip_addr, &sp->netmask, sp); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } static int rave_sp_probe(struct device_d *dev) diff --git a/drivers/mfd/smsc-superio.c b/drivers/mfd/smsc-superio.c index 349c878cef..ff83aa1a44 100644 --- a/drivers/mfd/smsc-superio.c +++ b/drivers/mfd/smsc-superio.c @@ -106,8 +106,9 @@ static void smsc_superio_find(u16 sioaddr, u16 id_reg) static int smsc_superio_detect(void) { u16 ports[] = { 0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370 }; + int i; - for (int i = 0; i < ARRAY_SIZE(ports); i++) + for (i = 0; i < ARRAY_SIZE(ports); i++) smsc_superio_find(ports[i], SIO_REG_DEVID); return 0; diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index cca6ec4ba9..071bbca236 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -324,9 +324,7 @@ static int leb_read_lock(struct ubi_device *ubi, int vol_id, int lnum) struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); - if (IS_ERR(le)) - return PTR_ERR(le); - return 0; + return PTR_ERR_OR_ZERO(le); } /** @@ -362,9 +360,7 @@ static int leb_write_lock(struct ubi_device *ubi, int vol_id, int lnum) struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); - if (IS_ERR(le)) - return PTR_ERR(le); - return 0; + return PTR_ERR_OR_ZERO(le); } /** @@ -383,9 +379,7 @@ static int leb_write_trylock(struct ubi_device *ubi, int vol_id, int lnum) struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); - if (IS_ERR(le)) - return PTR_ERR(le); - return 0; + return PTR_ERR_OR_ZERO(le); } /** diff --git a/drivers/net/designware_generic.c b/drivers/net/designware_generic.c index 809c7b7b69..90fca1951d 100644 --- a/drivers/net/designware_generic.c +++ b/drivers/net/designware_generic.c @@ -21,10 +21,7 @@ static int dwc_ether_probe(struct device_d *dev) struct dw_eth_dev *dwc; dwc = dwc_drv_probe(dev); - if (IS_ERR(dwc)) - return PTR_ERR(dwc); - - return 0; + return PTR_ERR_OR_ZERO(dwc); } static __maybe_unused struct of_device_id dwc_ether_compatible[] = { diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b43cb0d23e..de053a36fb 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -11,6 +11,9 @@ #include <init.h> #include <linux/phy.h> #include <linux/string.h> +#include <linux/bitfield.h> +#include <linux/mdio.h> +#include <dt-bindings/net/qca-ar803x.h> #define AT803X_INTR_ENABLE 0x12 #define AT803X_INTR_STATUS 0x13 @@ -27,6 +30,164 @@ #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05 #define AT803X_DEBUG_RGMII_TX_CLK_DLY (1 << 8) +/* AT803x supports either the XTAL input pad, an internal PLL or the + * DSP as clock reference for the clock output pad. The XTAL reference + * is only used for 25 MHz output, all other frequencies need the PLL. + * The DSP as a clock reference is used in synchronous ethernet + * applications. + * + * By default the PLL is only enabled if there is a link. Otherwise + * the PHY will go into low power state and disabled the PLL. You can + * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always + * enabled. + */ +#define AT803X_MMD7_CLK25M 0x8016 +#define AT803X_CLK_OUT_MASK GENMASK(4, 2) +#define AT803X_CLK_OUT_25MHZ_XTAL 0 +#define AT803X_CLK_OUT_25MHZ_DSP 1 +#define AT803X_CLK_OUT_50MHZ_PLL 2 +#define AT803X_CLK_OUT_50MHZ_DSP 3 +#define AT803X_CLK_OUT_62_5MHZ_PLL 4 +#define AT803X_CLK_OUT_62_5MHZ_DSP 5 +#define AT803X_CLK_OUT_125MHZ_PLL 6 +#define AT803X_CLK_OUT_125MHZ_DSP 7 + +/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask + * but doesn't support choosing between XTAL/PLL and DSP. + */ +#define AT8035_CLK_OUT_MASK GENMASK(4, 3) + +#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) +#define AT803X_CLK_OUT_STRENGTH_FULL 0 +#define AT803X_CLK_OUT_STRENGTH_HALF 1 +#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 + +#define ATH9331_PHY_ID 0x004dd041 +#define ATH8030_PHY_ID 0x004dd076 +#define ATH8031_PHY_ID 0x004dd074 +#define ATH8032_PHY_ID 0x004dd023 +#define ATH8035_PHY_ID 0x004dd072 +#define AT8030_PHY_ID_MASK 0xffffffef + +struct at803x_priv { + u16 clk_25m_reg; + u16 clk_25m_mask; +}; + +static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) +{ + struct phy_driver *drv = to_phy_driver(phydev->dev.driver); + + return (phydev->phy_id & drv->phy_id_mask) + == (phy_id & drv->phy_id_mask); +} + +static int at803x_parse_dt(struct phy_device *phydev) +{ + const struct device_d *dev = &phydev->dev; + const struct device_node *node = dev->device_node; + struct at803x_priv *priv = phydev->priv; + unsigned int sel, mask; + u32 freq, strength; + int ret; + + ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); + if (!ret) { + mask = AT803X_CLK_OUT_MASK; + switch (freq) { + case 25000000: + sel = AT803X_CLK_OUT_25MHZ_XTAL; + break; + case 50000000: + sel = AT803X_CLK_OUT_50MHZ_PLL; + break; + case 62500000: + sel = AT803X_CLK_OUT_62_5MHZ_PLL; + break; + case 125000000: + sel = AT803X_CLK_OUT_125MHZ_PLL; + break; + default: + dev_err(dev, "invalid qca,clk-out-frequency\n"); + return -EINVAL; + } + + priv->clk_25m_reg |= FIELD_PREP(mask, sel); + priv->clk_25m_mask |= mask; + + /* Fixup for the AR8030/AR8035. This chip has another mask and + * doesn't support the DSP reference. Eg. the lowest bit of the + * mask. The upper two bits select the same frequencies. Mask + * the lowest bit here. + * + * Warning: + * There was no datasheet for the AR8030 available so this is + * just a guess. But the AR8035 is listed as pin compatible + * to the AR8030 so there might be a good chance it works on + * the AR8030 too. + */ + if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || + at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { + priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; + priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; + } + } + + ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); + if (!ret) { + priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; + switch (strength) { + case AR803X_STRENGTH_FULL: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; + break; + case AR803X_STRENGTH_HALF: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; + break; + case AR803X_STRENGTH_QUARTER: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; + break; + default: + dev_err(dev, "invalid qca,clk-out-strength\n"); + return -EINVAL; + } + } + + return 0; +} + +static int at803x_probe(struct phy_device *phydev) +{ + struct at803x_priv *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return at803x_parse_dt(phydev); +} + +static int at803x_clk_out_config(struct phy_device *phydev) +{ + struct at803x_priv *priv = phydev->priv; + int val; + + if (!priv->clk_25m_mask) + return 0; + + val = phy_read_mmd_indirect(phydev, AT803X_MMD7_CLK25M, MDIO_MMD_AN); + if (val < 0) + return val; + + val &= ~priv->clk_25m_mask; + val |= priv->clk_25m_reg; + + phy_write_mmd_indirect(phydev, AT803X_MMD7_CLK25M, MDIO_MMD_AN, val); + + return 0; +} + static int at803x_config_init(struct phy_device *phydev) { int ret; @@ -46,33 +207,36 @@ static int at803x_config_init(struct phy_device *phydev) return ret; } - return 0; + return at803x_clk_out_config(phydev); } static struct phy_driver at803x_driver[] = { { /* ATHEROS 8035 */ - .phy_id = 0x004dd072, - .phy_id_mask = 0xffffffef, + .phy_id = ATH8035_PHY_ID, + .phy_id_mask = AT8030_PHY_ID_MASK, .drv.name = "Atheros 8035 ethernet", + .probe = at803x_probe, .config_init = at803x_config_init, .features = PHY_GBIT_FEATURES, .config_aneg = &genphy_config_aneg, .read_status = &genphy_read_status, }, { /* ATHEROS 8030 */ - .phy_id = 0x004dd076, - .phy_id_mask = 0xffffffef, + .phy_id = ATH8030_PHY_ID, + .phy_id_mask = AT8030_PHY_ID_MASK, .drv.name = "Atheros 8030 ethernet", .config_init = at803x_config_init, + .probe = at803x_probe, .features = PHY_GBIT_FEATURES, .config_aneg = &genphy_config_aneg, .read_status = &genphy_read_status, }, { /* ATHEROS 8031 */ - .phy_id = 0x004dd074, - .phy_id_mask = 0xffffffef, + .phy_id = ATH8031_PHY_ID, + .phy_id_mask = AT8030_PHY_ID_MASK, .drv.name = "Atheros 8031 ethernet", + .probe = at803x_probe, .config_init = at803x_config_init, .features = PHY_GBIT_FEATURES, .config_aneg = &genphy_config_aneg, diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index b3328b7e44..929a407b09 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -18,9 +18,10 @@ #include <linux/phy.h> #include <dt-bindings/net/ti-dp83867.h> +#include <linux/mdio.h> #define DP83867_PHY_ID 0x2000a231 -#define DP83867_DEVADDR 0x1f +#define DP83867_DEVADDR MDIO_MMD_VEND2 #define MII_DP83867_PHYCTRL 0x10 #define MII_DP83867_MICR 0x12 @@ -177,12 +178,6 @@ static int dp83867_of_init(struct phy_device *phydev) &dp83867->fifo_depth); } -static inline bool phy_interface_is_rgmii(struct phy_device *phydev) -{ - return phydev->interface >= PHY_INTERFACE_MODE_RGMII && - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; -} - static inline bool phy_interface_is_sgmii(struct phy_device *phydev) { return phydev->interface == PHY_INTERFACE_MODE_SGMII || diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 73d6453b36..af39ed68fd 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -168,12 +168,6 @@ static int marvell_read_status(struct phy_device *phydev) #define MII_88E1510_GEN_CTRL_REG_1 0x14 -static inline bool phy_interface_is_rgmii(struct phy_device *phydev) -{ - return phydev->interface >= PHY_INTERFACE_MODE_RGMII && - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; -}; - /* * Set and/or override some configuration registers based on the * marvell,reg-init property stored in the of_node for the phydev. diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 8f0b81d8fa..4655430573 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -17,7 +17,9 @@ #include <linux/mii.h> #include <linux/ethtool.h> #include <linux/phy.h> +#include <linux/mdio.h> #include <linux/micrel_phy.h> +#include <linux/bitfield.h> /* Operation Mode Strap Override */ #define MII_KSZPHY_OMSO 0x16 @@ -155,9 +157,50 @@ static int ksz9021_config_init(struct phy_device *phydev) /* MMD Address 0x2 */ #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 +#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) +#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) + #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 +#define MII_KSZ9031RN_RXD3 GENMASK(15, 12) +#define MII_KSZ9031RN_RXD2 GENMASK(11, 8) +#define MII_KSZ9031RN_RXD1 GENMASK(7, 4) +#define MII_KSZ9031RN_RXD0 GENMASK(3, 0) + #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 +#define MII_KSZ9031RN_TXD3 GENMASK(15, 12) +#define MII_KSZ9031RN_TXD2 GENMASK(11, 8) +#define MII_KSZ9031RN_TXD1 GENMASK(7, 4) +#define MII_KSZ9031RN_TXD0 GENMASK(3, 0) + #define MII_KSZ9031RN_CLK_PAD_SKEW 8 +#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) +#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) + +/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To + * provide different RGMII options we need to configure delay offset + * for each pad relative to build in delay. + */ +/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of + * 1.80ns + */ +#define RX_ID 0x7 +#define RX_CLK_ID 0x19 + +/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the + * internal 1.2ns delay. + */ +#define RX_ND 0xc +#define RX_CLK_ND 0x0 + +/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ +#define TX_ID 0x0 +#define TX_CLK_ID 0x1f + +/* set tx and tx_clk to "No delay adjustment" to keep 0ns + * dealy + */ +#define TX_ND 0x7 +#define TX_CLK_ND 0xf static int ksz9031_of_load_skew_values(struct phy_device *phydev, const struct device_node *of_node, @@ -179,7 +222,7 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev, return 0; if (matches < numfields) - newval = phy_read_mmd_indirect(phydev, reg, 2); + newval = phy_read_mmd_indirect(phydev, reg, MDIO_MMD_WIS); else newval = 0; @@ -193,7 +236,7 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev, << (field_sz * i)); } - phy_write_mmd_indirect(phydev, reg, 2, newval); + phy_write_mmd_indirect(phydev, reg, MDIO_MMD_WIS, newval); return 0; } @@ -206,6 +249,61 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev) return genphy_restart_aneg(phydev); } +static int ksz9031_config_rgmii_delay(struct phy_device *phydev) +{ + u16 rx, tx, rx_clk, tx_clk; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + tx = TX_ND; + tx_clk = TX_CLK_ND; + rx = RX_ND; + rx_clk = RX_CLK_ND; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + tx = TX_ID; + tx_clk = TX_CLK_ID; + rx = RX_ID; + rx_clk = RX_CLK_ID; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + tx = TX_ND; + tx_clk = TX_CLK_ND; + rx = RX_ID; + rx_clk = RX_CLK_ID; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + tx = TX_ID; + tx_clk = TX_CLK_ID; + rx = RX_ND; + rx_clk = RX_CLK_ND; + break; + default: + return 0; + } + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_CONTROL_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | + FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_RX_DATA_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | + FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | + FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | + FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_TX_DATA_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | + FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | + FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | + FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); + + phy_write_mmd_indirect(phydev, MII_KSZ9031RN_CLK_PAD_SKEW, 2, + FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | + FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); + return 0; +} + static int ksz9031_config_init(struct phy_device *phydev) { const struct device_d *dev = &phydev->dev; @@ -226,6 +324,12 @@ static int ksz9031_config_init(struct phy_device *phydev) of_node = dev->parent->device_node; if (of_node) { + if (phy_interface_is_rgmii(phydev)) { + ret = ksz9031_config_rgmii_delay(phydev); + if (ret < 0) + return ret; + } + ksz9031_of_load_skew_values(phydev, of_node, MII_KSZ9031RN_CLK_PAD_SKEW, 5, clk_skews, 2); diff --git a/drivers/pci/pci-tegra.c b/drivers/pci/pci-tegra.c index 7f10b7af2e..b534285c97 100644 --- a/drivers/pci/pci-tegra.c +++ b/drivers/pci/pci-tegra.c @@ -822,10 +822,7 @@ static int tegra_pcie_resets_get(struct tegra_pcie *pcie) return PTR_ERR(pcie->afi_rst); pcie->pcie_xrst = reset_control_get(pcie->dev, "pcie_x"); - if (IS_ERR(pcie->pcie_xrst)) - return PTR_ERR(pcie->pcie_xrst); - - return 0; + return PTR_ERR_OR_ZERO(pcie->pcie_xrst); } static int tegra_pcie_get_resources(struct tegra_pcie *pcie) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 878f4d72bb..aba6c2a709 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -122,10 +122,7 @@ int pwmchip_add(struct pwm_chip *chip, struct device_d *dev) p = dev_add_param_bool(&pwm->dev, "inverted", apply_params, NULL, &pwm->params.polarity, pwm); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } EXPORT_SYMBOL_GPL(pwmchip_add); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 9befc5e55f..316ece9e71 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -23,6 +23,7 @@ config RESET_IMX7 config RESET_STM32 bool "STM32 Reset Driver" + depends on ARCH_STM32MP || COMPILE_TEST help This enables the reset controller driver for STM32MP and STM32 MCUs. diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c index 74a0c81d3e..f2cf944e8f 100644 --- a/drivers/serial/serial_pl010.c +++ b/drivers/serial/serial_pl010.c @@ -1,24 +1,9 @@ -/* - * Copyright (C) 2010 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, <philippe.robin@arm.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2000 Rob Taylor <robt@flyingpig.com>, Flying Pig Systems +// SPDX-FileCopyrightText: 2004 ARM Ltd. +// SPDX-FileCopyrightText: 2010 Matthias Kaehlcke <matthias@kaehlcke.net> + +/* Contributor: Philippe Robin <philippe.robin@arm.com> */ /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ diff --git a/drivers/serial/serial_pl010.h b/drivers/serial/serial_pl010.h index f442339ea3..ba81a66da0 100644 --- a/drivers/serial/serial_pl010.h +++ b/drivers/serial/serial_pl010.h @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2010 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * (C) Copyright 2003, 2004 - * ARM Ltd. - * Philippe Robin, <philippe.robin@arm.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2003, 2004 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2010 Matthias Kaehlcke <matthias@kaehlcke.net> */ + +/* Contributor: Philippe Robin <philippe.robin@arm.com> */ struct hldc_struct { uint32_t ctrl; diff --git a/drivers/usb/otg/otgdev.c b/drivers/usb/otg/otgdev.c index 7017796e8c..52f43b75d2 100644 --- a/drivers/usb/otg/otgdev.c +++ b/drivers/usb/otg/otgdev.c @@ -62,8 +62,5 @@ int usb_register_otg_device(struct device_d *parent, param_mode = dev_add_param_enum(&otg_device, "mode", otg_set_mode, NULL, &otg_mode, otg_mode_names, ARRAY_SIZE(otg_mode_names), ctx); - if (IS_ERR(param_mode)) - return PTR_ERR(param_mode); - - return 0; + return PTR_ERR_OR_ZERO(param_mode); } diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c index 6f2d30ec77..925c2f809d 100644 --- a/drivers/watchdog/f71808e_wdt.c +++ b/drivers/watchdog/f71808e_wdt.c @@ -11,7 +11,6 @@ #include <init.h> #include <asm/io.h> -#include <linux/bitops.h> #include <driver.h> #include <watchdog.h> #include <printk.h> @@ -114,30 +113,50 @@ static inline void superio_exit(u16 base) outb(SIO_LOCK_KEY, base); } +static inline u8 f71808e_wdt_conf_in(struct f71808e_wdt *wd) +{ + return superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF); +} + +static inline void f71808e_wdt_conf_out(struct f71808e_wdt *wd, u8 wdt_conf) +{ + /* + * Writing 1 to WDTMOUT_STS clears it. Writing 0 keeps the old state. + * We want the latter, so the OS driver can check it later on. + */ + wdt_conf &= ~BIT(F71808FG_FLAG_WDTMOUT_STS); + superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF, wdt_conf); +} + static void f71808e_wdt_keepalive(struct f71808e_wdt *wd) { + u8 wdt_conf; + superio_enter(wd->sioaddr); superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); + wdt_conf = f71808e_wdt_conf_in(wd); + if (wd->minutes_mode) /* select minutes for timer units */ - superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_UNIT); + wdt_conf |= BIT(F71808FG_FLAG_WD_UNIT); else /* select seconds for timer units */ - superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_UNIT); + wdt_conf &= ~BIT(F71808FG_FLAG_WD_UNIT); + + f71808e_wdt_conf_out(wd, wdt_conf); /* Set timer value */ - superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME, - wd->timer_val); + superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME, wd->timer_val); superio_exit(wd->sioaddr); } static void f71808e_wdt_start(struct f71808e_wdt *wd) { + u8 wdt_conf; + /* Make sure we don't die as soon as the watchdog is enabled below */ f71808e_wdt_keepalive(wd); @@ -158,36 +177,38 @@ static void f71808e_wdt_start(struct f71808e_wdt *wd) superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF, F71808FG_FLAG_WDOUT_EN); - superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_EN); + wdt_conf = f71808e_wdt_conf_in(wd); + wdt_conf |= BIT(F71808FG_FLAG_WD_EN); + f71808e_wdt_conf_out(wd, wdt_conf); if (wd->pulse_width > 0) { /* Select "pulse" output mode with given duration */ - u8 wdt_conf = superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF); - /* Set WD_PSWIDTH bits (1:0) */ wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_width & 0x03); /* Set WD_PULSE to "pulse" mode */ wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE); - superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF, wdt_conf); } else { /* Select "level" output mode */ - superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_PULSE); + wdt_conf &= ~BIT(F71808FG_FLAG_WD_PULSE); } + f71808e_wdt_conf_out(wd, wdt_conf); + superio_exit(wd->sioaddr); } static void f71808e_wdt_stop(struct f71808e_wdt *wd) { + u8 wdt_conf; + superio_enter(wd->sioaddr); superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); - superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, - F71808FG_FLAG_WD_EN); + wdt_conf = f71808e_wdt_conf_in(wd); + wdt_conf &= ~BIT(F71808FG_FLAG_WD_EN); + f71808e_wdt_conf_out(wd, wdt_conf); superio_exit(wd->sioaddr); } @@ -222,14 +243,14 @@ static int f71808e_wdt_init(struct f71808e_wdt *wd, struct device_d *dev) { struct watchdog *wdd = &wd->wdd; const char * const *names = pulse_width_names; - unsigned long wdt_conf; + u8 wdt_conf; int ret; superio_enter(wd->sioaddr); superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); - wdt_conf = superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF); + wdt_conf = f71808e_wdt_conf_in(wd); superio_exit(wd->sioaddr); @@ -262,7 +283,7 @@ static int f71808e_wdt_init(struct f71808e_wdt *wd, struct device_d *dev) } - if (test_bit(F71808FG_FLAG_WD_EN, &wdt_conf)) + if (wdt_conf & BIT(F71808FG_FLAG_WD_EN)) wdd->running = WDOG_HW_RUNNING; else wdd->running = WDOG_HW_NOT_RUNNING; diff --git a/drivers/watchdog/rave-sp-wdt.c b/drivers/watchdog/rave-sp-wdt.c index dc673ee35f..cad63e22f9 100644 --- a/drivers/watchdog/rave-sp-wdt.c +++ b/drivers/watchdog/rave-sp-wdt.c @@ -299,10 +299,7 @@ static int rave_sp_wdt_add_params(struct rave_sp_wdt *sp_wd) rave_sp_wdt_set_boot_source, rave_sp_wdt_get_boot_source, &sp_wd->boot_source, "%u", sp_wd); - if (IS_ERR(p)) - return PTR_ERR(p); - - return 0; + return PTR_ERR_OR_ZERO(p); } static int rave_sp_wdt_probe(struct device_d *dev) |