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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:35:17 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:40 +0100 |
commit | 6e6d9a2ff045f09d5a03e876becea5e6a1dabe90 (patch) | |
tree | bcf5e71df4472e374d03cc15ca22b4f841d9c73d /dts/Bindings/arc | |
parent | 8e2fd5380a4fd7cee428513dc8eab068912b49f1 (diff) | |
download | barebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.gz barebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.xz |
dts: update to v4.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arc')
-rw-r--r-- | dts/Bindings/arc/archs-idu-intc.txt | 46 | ||||
-rw-r--r-- | dts/Bindings/arc/archs-intc.txt | 22 | ||||
-rw-r--r-- | dts/Bindings/arc/interrupts.txt | 24 |
3 files changed, 0 insertions, 92 deletions
diff --git a/dts/Bindings/arc/archs-idu-intc.txt b/dts/Bindings/arc/archs-idu-intc.txt deleted file mode 100644 index 0dcb7c7d3e..0000000000 --- a/dts/Bindings/arc/archs-idu-intc.txt +++ /dev/null @@ -1,46 +0,0 @@ -* ARC-HS Interrupt Distribution Unit - - This optional 2nd level interrupt controller can be used in SMP configurations for - dynamic IRQ routing, load balancing of common/external IRQs towards core intc. - -Properties: - -- compatible: "snps,archs-idu-intc" -- interrupt-controller: This is an interrupt controller. -- interrupt-parent: <reference to parent core intc> -- #interrupt-cells: Must be <2>. -- interrupts: <...> specifies the upstream core irqs - - First cell specifies the "common" IRQ from peripheral to IDU - Second cell specifies the irq distribution mode to cores - 0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - core_intc: core-interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - idu_intc: idu-interrupt-controller { - compatible = "snps,archs-idu-intc"; - interrupt-controller; - interrupt-parent = <&core_intc>; - - /* - * <hwirq distribution> - * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 - */ - #interrupt-cells = <2>; - - /* upstream core irqs: downstream these are "COMMON" irq 0,1.. */ - interrupts = <24 25 26 27 28 29 30 31>; - }; - - some_device: serial@c0fc1000 { - interrupt-parent = <&idu_intc>; - interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */ - }; diff --git a/dts/Bindings/arc/archs-intc.txt b/dts/Bindings/arc/archs-intc.txt deleted file mode 100644 index 69f326d6a5..0000000000 --- a/dts/Bindings/arc/archs-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) - -Properties: - -- compatible: "snps,archs-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 16 to 256 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = <16 17 18 19 20 21 22 23 24 25>; - }; diff --git a/dts/Bindings/arc/interrupts.txt b/dts/Bindings/arc/interrupts.txt deleted file mode 100644 index 9a5d562435..0000000000 --- a/dts/Bindings/arc/interrupts.txt +++ /dev/null @@ -1,24 +0,0 @@ -* ARC700 incore Interrupt Controller - - The core interrupt controller provides 32 prioritised interrupts (2 levels) - to ARC700 core. - -Properties: - -- compatible: "snps,arc700-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 0 to 31 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,arc700-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; |