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authorSascha Hauer <s.hauer@pengutronix.de>2019-01-14 09:09:57 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-01-14 09:09:57 +0100
commit33fdc89d4cbd74aa54c28dc61d62972ab164e64d (patch)
treeda5ceff551dc1fdf2f2cc40e97a08035f9ef84fb /dts/Bindings/arm/altera
parent13a52906ce67ed2ce67bfc10714934ffa6c5d646 (diff)
downloadbarebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.gz
barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.xz
dts: update to v5.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/altera')
-rw-r--r--dts/Bindings/arm/altera/socfpga-clk-manager.txt11
-rw-r--r--dts/Bindings/arm/altera/socfpga-clk-manager.yaml31
2 files changed, 31 insertions, 11 deletions
diff --git a/dts/Bindings/arm/altera/socfpga-clk-manager.txt b/dts/Bindings/arm/altera/socfpga-clk-manager.txt
deleted file mode 100644
index 2c28f1d12..000000000
--- a/dts/Bindings/arm/altera/socfpga-clk-manager.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Altera SOCFPGA Clock Manager
-
-Required properties:
-- compatible : "altr,clk-mgr"
-- reg : Should contain base address and length for Clock Manager
-
-Example:
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
- };
diff --git a/dts/Bindings/arm/altera/socfpga-clk-manager.yaml b/dts/Bindings/arm/altera/socfpga-clk-manager.yaml
new file mode 100644
index 000000000..e4131fa42
--- /dev/null
+++ b/dts/Bindings/arm/altera/socfpga-clk-manager.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA Clock Manager
+
+maintainers:
+ - Dinh Nguyen <dinguyen@kernel.org>
+
+description: test
+
+properties:
+ compatible:
+ items:
+ - const: altr,clk-mgr
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+examples:
+ - |
+ clkmgr@ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
+ };
+
+...