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authorSascha Hauer <s.hauer@pengutronix.de>2017-11-28 11:02:14 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-11-28 11:06:44 +0100
commit2e9cce8fb1f577088e2b20ae2f461130e13ad190 (patch)
treef82ae53e88d36e07608be1b3159da296ed025ef1 /dts/Bindings/arm/amlogic/smp-sram.txt
parentc68d466d263827692aa809e6b34abb90a1cab515 (diff)
downloadbarebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.gz
barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.xz
dts: update to v4.15-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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+Amlogic Meson8 and Meson8b SRAM for smp bringup:
+------------------------------------------------
+
+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+ "amlogic,meson8-smp-sram"
+ "amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+ sram: sram@d9000000 {
+ compatible = "mmio-sram";
+ reg = <0xd9000000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd9000000 0x20000>;
+
+ smp-sram@1ff80 {
+ compatible = "amlogic,meson8b-smp-sram";
+ reg = <0x1ff80 0x8>;
+ };
+ };