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authorSascha Hauer <s.hauer@pengutronix.de>2022-01-27 11:22:53 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2022-01-28 15:31:59 +0100
commit5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08 (patch)
tree0634f20e5f75f3d44242af47eebd9ea1ce0163f6 /dts/Bindings/arm/arm-dsu-pmu.txt
parentdb35548372eaee835fbf9bae68c08362ba59d49d (diff)
downloadbarebox-5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08.tar.gz
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dts: update to v5.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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-* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
-
-ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
-with a shared L3 memory system, control logic and external interfaces to
-form a multicore cluster. The PMU enables to gather various statistics on
-the operations of the DSU. The PMU provides independent 32bit counters that
-can count any of the supported events, along with a 64bit cycle counter.
-The PMU is accessed via CPU system registers and has no MMIO component.
-
-** DSU PMU required properties:
-
-- compatible : should be one of :
-
- "arm,dsu-pmu"
-
-- interrupts : Exactly 1 SPI must be listed.
-
-- cpus : List of phandles for the CPUs connected to this DSU instance.
-
-
-** Example:
-
-dsu-pmu-0 {
- compatible = "arm,dsu-pmu";
- interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
- cpus = <&cpu_0>, <&cpu_1>;
-};