path: root/dts/Bindings/arm/arm-dsu-pmu.txt
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authorSascha Hauer <>2018-02-27 09:40:19 +0100
committerSascha Hauer <>2018-03-01 14:29:51 +0100
commita9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch)
tree35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/Bindings/arm/arm-dsu-pmu.txt
parent5ba0e42cb24afdf59d48930daf495c148312fc67 (diff)
dts: update to v4.16-rc1
Also includeded: ARM: dts: am33xx: do not delete no longer existing clocks Several clocks are removed from the am33xx dts files with v4.16-rc1. Remove the corresponding /delete-node/ directives aswell to avoid dtc breakage. Also included: ARM: dts: imx6qdl: SolidRun: Fix upstream include Upstream dts file way renamed, so change include name accordingly. Signed-off-by: Sascha Hauer <>
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+* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
+with a shared L3 memory system, control logic and external interfaces to
+form a multicore cluster. The PMU enables to gather various statistics on
+the operations of the DSU. The PMU provides independent 32bit counters that
+can count any of the supported events, along with a 64bit cycle counter.
+The PMU is accessed via CPU system registers and has no MMIO component.
+** DSU PMU required properties:
+- compatible : should be one of :
+ "arm,dsu-pmu"
+- interrupts : Exactly 1 SPI must be listed.
+- cpus : List of phandles for the CPUs connected to this DSU instance.
+** Example:
+dsu-pmu-0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu_0>, <&cpu_1>;