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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-28 11:02:14 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-28 11:06:44 +0100 |
commit | 2e9cce8fb1f577088e2b20ae2f461130e13ad190 (patch) | |
tree | f82ae53e88d36e07608be1b3159da296ed025ef1 /dts/Bindings/arm/bcm | |
parent | c68d466d263827692aa809e6b34abb90a1cab515 (diff) | |
download | barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.gz barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.xz |
dts: update to v4.15-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/bcm')
-rw-r--r-- | dts/Bindings/arm/bcm/brcm,brcmstb.txt | 6 | ||||
-rw-r--r-- | dts/Bindings/arm/bcm/brcm,hr2.txt | 14 |
2 files changed, 19 insertions, 1 deletions
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt index 0d0c1ae81b..790e6b0b83 100644 --- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt +++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt @@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY. Required properties: - compatible : should contain one of these + "brcm,brcmstb-ddr-phy-v71.1" + "brcm,brcmstb-ddr-phy-v72.0" "brcm,brcmstb-ddr-phy-v225.1" "brcm,brcmstb-ddr-phy-v240.1" "brcm,brcmstb-ddr-phy-v240.2" @@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh Power-Down (SRPD), among other things. Required properties: -- compatible : should contain "brcm,brcmstb-memc-ddr" +- compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range Example: diff --git a/dts/Bindings/arm/bcm/brcm,hr2.txt b/dts/Bindings/arm/bcm/brcm,hr2.txt new file mode 100644 index 0000000000..a124c7fc4d --- /dev/null +++ b/dts/Bindings/arm/bcm/brcm,hr2.txt @@ -0,0 +1,14 @@ +Broadcom Hurricane 2 device tree bindings +--------------------------------------- + +Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs +are based on Broadcom's iProc SoC architecture and feature a single core Cortex +A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND +flash and a PCIe attached integrated switching engine. + +Boards with Hurricane SoCs shall have the following properties: + +Required root node property: + +BCM53342 +compatible = "brcm,bcm53342", "brcm,hr2"; |