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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-02-27 09:40:19 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-01 14:29:51 +0100 |
commit | a9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch) | |
tree | 35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/Bindings/arm/bcm | |
parent | 5ba0e42cb24afdf59d48930daf495c148312fc67 (diff) | |
download | barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.gz barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.xz |
dts: update to v4.16-rc1
Also includeded:
ARM: dts: am33xx: do not delete no longer existing clocks
Several clocks are removed from the am33xx dts files with v4.16-rc1.
Remove the corresponding /delete-node/ directives aswell to avoid
dtc breakage.
Also included:
ARM: dts: imx6qdl: SolidRun: Fix upstream include
Upstream dts file way renamed, so change include name accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/bcm')
-rw-r--r-- | dts/Bindings/arm/bcm/brcm,brcmstb.txt | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt index 790e6b0b83..c052caad36 100644 --- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt +++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt @@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general system control is required: - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon" - - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon" + - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl", + "brcm,brcmstb-cpu-biu-ctrl", + "syscon" - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon" -hif-cpubiuctrl node +cpu-biu-ctrl node ------------------- -SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit -(BIU) block which controls and interfaces the CPU complex to the different -Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block -offers a feature called Write Pairing which consists in collapsing two adjacent -cache lines into a single (bursted) write transaction towards the memory -controller (MEMC) to maximize write bandwidth. +SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a +specific Bus Interface Unit (BIU) block which controls and interfaces the CPU +complex to the different Memory Controller Ports (MCP), one per memory +controller (MEMC). This BIU block offers a feature called Write Pairing which +consists in collapsing two adjacent cache lines into a single (bursted) write +transaction towards the memory controller (MEMC) to maximize write bandwidth. Required properties: - - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon" + - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon" Optional properties: @@ -52,7 +54,7 @@ example: }; hif_cpubiuctrl: syscon@3e2400 { - compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon"; + compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"; reg = <0x3e2400 0x5b4>; brcm,write-pairing; }; |