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| author | Lucas Stach <l.stach@pengutronix.de> | 2017-07-31 20:03:05 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2017-07-31 20:03:05 +0200 |
| commit | d14b844b08635c717fb52a294ed8d6872e260315 (patch) | |
| tree | 18607dcdd29688b2fa9528f79423183a68e9898d /dts/Bindings/arm/cci.txt | |
| parent | 858b797e529e26c19bfa893fdb37ed67ff7a6006 (diff) | |
| download | barebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.gz barebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.xz | |
dts: update to v4.13-rc2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/cci.txt')
| -rw-r--r-- | dts/Bindings/arm/cci.txt | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/dts/Bindings/arm/cci.txt b/dts/Bindings/arm/cci.txt index 0f2153e8fa..9600761f2d 100644 --- a/dts/Bindings/arm/cci.txt +++ b/dts/Bindings/arm/cci.txt @@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register space and multiple sets of interface control registers, one per slave interface. -Bindings for the CCI node follow the ePAPR standard, available from: - -www.power.org/documentation/epapr-version-1-1/ - -with the addition of the bindings described in this document which are -specific to ARM. - * CCI interconnect node Description: Describes a CCI cache coherent Interconnect component @@ -50,10 +43,10 @@ specific to ARM. as a tuple of cells, containing child address, parent address and the size of the region in the child address space. - Definition: A standard property. Follow rules in the ePAPR for - hierarchical bus addressing. CCI interfaces - addresses refer to the parent node addressing - scheme to declare their register bases. + Definition: A standard property. Follow rules in the Devicetree + Specification for hierarchical bus addressing. CCI + interfaces addresses refer to the parent node + addressing scheme to declare their register bases. CCI interconnect node can define the following child nodes: |