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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-19 08:56:20 +0200 |
commit | 6940ba22c66ac1c713500027bf5f6832442a1410 (patch) | |
tree | a460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/Bindings/arm/coresight-cpu-debug.txt | |
parent | e66a790177410d7433e6672d97bb0b54455ba669 (diff) | |
download | barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.gz barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.xz |
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/coresight-cpu-debug.txt')
-rw-r--r-- | dts/Bindings/arm/coresight-cpu-debug.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/dts/Bindings/arm/coresight-cpu-debug.txt b/dts/Bindings/arm/coresight-cpu-debug.txt index 298291211e..f1de3247c1 100644 --- a/dts/Bindings/arm/coresight-cpu-debug.txt +++ b/dts/Bindings/arm/coresight-cpu-debug.txt @@ -26,8 +26,8 @@ Required properties: processor core is clocked by the internal CPU clock, so it is enabled with CPU clock by default. -- cpu : the CPU phandle the debug module is affined to. When omitted - the module is considered to belong to CPU0. +- cpu : the CPU phandle the debug module is affined to. Do not assume it + to default to CPU0 if omitted. Optional properties: |