path: root/dts/Bindings/arm/coresight.txt
diff options
authorSascha Hauer <>2019-12-19 05:46:54 +0100
committerSascha Hauer <>2019-12-19 05:46:54 +0100
commit574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (patch)
tree3fbe9ed379bc0d6c536860845e85a4ede4b36bbc /dts/Bindings/arm/coresight.txt
parent179dedbc6d85d7ea7c8013513b364a75f32943e8 (diff)
dts: update to v5.5-rc1
Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'dts/Bindings/arm/coresight.txt')
1 files changed, 9 insertions, 0 deletions
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index fcc3bacfd8..d02c42d21f 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -87,6 +87,15 @@ its hardware characteristcs.
* port or ports: see "Graph bindings for Coresight" below.
+* Optional properties for all components:
+ * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
+ hardware will lose register context on CPU power down (e.g. CPUIdle).
+ An example of where this may be needed are systems which contain a
+ coresight component and CPU in the same power domain. When the CPU
+ powers down the coresight component also powers down and loses its
+ context. This property is currently only used for the ETM 4.x driver.
* Optional properties for ETM/PTMs:
* arm,cp14: must be present if the system accesses ETM/PTM management