|author||Sascha Hauer <email@example.com>||2019-08-19 08:56:20 +0200|
|committer||Sascha Hauer <firstname.lastname@example.org>||2019-08-19 08:56:20 +0200|
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <email@example.com>
Diffstat (limited to 'dts/Bindings/arm/coresight.txt')
1 files changed, 5 insertions, 3 deletions
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 8a88ddebc1..fcc3bacfd8 100644
@@ -59,6 +59,11 @@ its hardware characteristcs.
* port or ports: see "Graph bindings for Coresight" below.
+* Additional required property for Embedded Trace Macrocell (version 3.x and
+ version 4.x):
+ * cpu: the cpu phandle this ETM/PTM is affined to. Do not
+ assume it to default to CPU0 if omitted.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
set as described above, another entry is required to describe the
@@ -87,9 +92,6 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
- * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
- source is considered to belong to CPU0.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR