path: root/dts/Bindings/arm/coresight.txt
diff options
authorSascha Hauer <>2019-08-19 08:56:20 +0200
committerSascha Hauer <>2019-08-19 08:56:20 +0200
commit6940ba22c66ac1c713500027bf5f6832442a1410 (patch)
treea460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/Bindings/arm/coresight.txt
parente66a790177410d7433e6672d97bb0b54455ba669 (diff)
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'dts/Bindings/arm/coresight.txt')
1 files changed, 5 insertions, 3 deletions
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 8a88ddebc1..fcc3bacfd8 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -59,6 +59,11 @@ its hardware characteristcs.
* port or ports: see "Graph bindings for Coresight" below.
+* Additional required property for Embedded Trace Macrocell (version 3.x and
+ version 4.x):
+ * cpu: the cpu phandle this ETM/PTM is affined to. Do not
+ assume it to default to CPU0 if omitted.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
set as described above, another entry is required to describe the
@@ -87,9 +92,6 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
- * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
- source is considered to belong to CPU0.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR