path: root/dts/Bindings/arm/coresight.txt
diff options
authorSascha Hauer <>2015-07-08 14:44:21 +0200
committerSascha Hauer <>2015-07-08 14:44:21 +0200
commit87360e3dd42bb627a9f2611f961728c0789e1c21 (patch)
treeafefc88c862d9feafb0cdb075badeb8d32d8efd2 /dts/Bindings/arm/coresight.txt
parent80936d6aaeea1b10ce4eb81c54eece2f55f8e209 (diff)
dts: update to v4.2-rc1
Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'dts/Bindings/arm/coresight.txt')
1 files changed, 8 insertions, 4 deletions
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 88602b7541..65a6db2271 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -17,15 +17,19 @@ its hardware characteristcs.
- "arm,coresight-tmc", "arm,primecell";
- "arm,coresight-funnel", "arm,primecell";
- "arm,coresight-etm3x", "arm,primecell";
+ - "qcom,coresight-replicator1x", "arm,primecell";
* reg: physical base address and length of the register
set(s) of the component.
- * clocks: the clock associated to this component.
+ * clocks: the clocks associated to this component.
- * clock-names: the name of the clock as referenced by the code.
- Since we are using the AMBA framework, the name should be
- "apb_pclk".
+ * clock-names: the name of the clocks referenced by the code.
+ Since we are using the AMBA framework, the name of the clock
+ providing the interconnect should be "apb_pclk", and some
+ coresight blocks also have an additional clock "atclk", which
+ clocks the core of that coresight component. The latter clock
+ is optional.
* port or ports: The representation of the component's port
layout using the generic DT graph presentation found in