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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 08:14:56 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 08:14:56 +0200 |
commit | 6b85c20d46812bdbc062b863261c3e5100e30556 (patch) | |
tree | e067c9889eaf55d5e793b05a14000276f2669e9f /dts/Bindings/arm/hisilicon | |
parent | 9d8c00bdf7c1e8b614a797f0a15fa45bf6387224 (diff) | |
download | barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.gz barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.xz |
dts: update to v4.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/hisilicon')
-rw-r--r-- | dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt | 33 | ||||
-rw-r--r-- | dts/Bindings/arm/hisilicon/hisilicon.txt | 23 |
2 files changed, 56 insertions, 0 deletions
diff --git a/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt new file mode 100644 index 0000000000..10bd35f920 --- /dev/null +++ b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt @@ -0,0 +1,33 @@ +Hisilicon Hip06 Low Pin Count device + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + Hip06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +Required properties: +- compatible: value should be as follows: + (a) "hisilicon,hip06-lpc" + (b) "hisilicon,hip07-lpc" +- #address-cells: must be 2 which stick to the ISA/EISA binding doc. +- #size-cells: must be 1 which stick to the ISA/EISA binding doc. +- reg: base memory range where the LPC register set is mapped. + +Note: + The node name before '@' must be "isa" to represent the binding stick to the + ISA/EISA binding specification. + +Example: + +isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0xa01b0000 0x0 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; +}; diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt index 7111fbc82a..199cd36fe1 100644 --- a/dts/Bindings/arm/hisilicon/hisilicon.txt +++ b/dts/Bindings/arm/hisilicon/hisilicon.txt @@ -75,6 +75,29 @@ Example: }; ----------------------------------------------------------------------- +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + +----------------------------------------------------------------------- Hisilicon Hi6220 system controller Required properties: |