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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-01 09:47:17 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-02 11:01:29 +0200 |
| commit | a595ff6eea05b919567f96d71e7e2c7b6236b8ac (patch) | |
| tree | 2d7cea529b6a06be744116e29e8a97b0c8de1981 /dts/Bindings/arm/hisilicon | |
| parent | 7955f4315187665690f51e20698d4c12c68e008f (diff) | |
| download | barebox-a595ff6eea05b919567f96d71e7e2c7b6236b8ac.tar.gz barebox-a595ff6eea05b919567f96d71e7e2c7b6236b8ac.tar.xz | |
dts: update to v3.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/hisilicon')
| -rw-r--r-- | dts/Bindings/arm/hisilicon/hisilicon.txt | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt index df0a452b85..934f00025c 100644 --- a/dts/Bindings/arm/hisilicon/hisilicon.txt +++ b/dts/Bindings/arm/hisilicon/hisilicon.txt @@ -31,6 +31,17 @@ Example: reboot-offset = <0x4>; }; +----------------------------------------------------------------------- +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. + +----------------------------------------------------------------------- PCTRL: Peripheral misc control register Required Properties: |