diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:35:17 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:40 +0100 |
commit | 6e6d9a2ff045f09d5a03e876becea5e6a1dabe90 (patch) | |
tree | bcf5e71df4472e374d03cc15ca22b4f841d9c73d /dts/Bindings/arm/mediatek/mediatek,sysirq.txt | |
parent | 8e2fd5380a4fd7cee428513dc8eab068912b49f1 (diff) | |
download | barebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.gz barebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.xz |
dts: update to v4.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/mediatek/mediatek,sysirq.txt')
-rw-r--r-- | dts/Bindings/arm/mediatek/mediatek,sysirq.txt | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt b/dts/Bindings/arm/mediatek/mediatek,sysirq.txt deleted file mode 100644 index afef6a85ac..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt +++ /dev/null @@ -1,32 +0,0 @@ -+Mediatek 65xx/67xx/81xx sysirq - -Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI -interrupt. - -Required properties: -- compatible: should be one of: - "mediatek,mt8173-sysirq" - "mediatek,mt8135-sysirq" - "mediatek,mt8127-sysirq" - "mediatek,mt6795-sysirq" - "mediatek,mt6592-sysirq" - "mediatek,mt6589-sysirq" - "mediatek,mt6582-sysirq" - "mediatek,mt6580-sysirq" - "mediatek,mt6577-sysirq" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Use the same format as specified by GIC in - Documentation/devicetree/bindings/arm/gic.txt -- interrupt-parent: phandle of irq parent for sysirq. The parent must - use the same interrupt-cells format as GIC. -- reg: Physical base address of the intpol registers and length of memory - mapped region. - -Example: - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; |