summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/arm/renesas,prr.txt
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2019-01-14 09:09:57 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-01-14 09:09:57 +0100
commit33fdc89d4cbd74aa54c28dc61d62972ab164e64d (patch)
treeda5ceff551dc1fdf2f2cc40e97a08035f9ef84fb /dts/Bindings/arm/renesas,prr.txt
parent13a52906ce67ed2ce67bfc10714934ffa6c5d646 (diff)
downloadbarebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.gz
barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.xz
dts: update to v5.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/renesas,prr.txt')
-rw-r--r--dts/Bindings/arm/renesas,prr.txt20
1 files changed, 20 insertions, 0 deletions
diff --git a/dts/Bindings/arm/renesas,prr.txt b/dts/Bindings/arm/renesas,prr.txt
new file mode 100644
index 0000000000..08e482e953
--- /dev/null
+++ b/dts/Bindings/arm/renesas,prr.txt
@@ -0,0 +1,20 @@
+Renesas Product Register
+
+Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
+allows to retrieve SoC product and revision information. If present, a device
+node for this register should be added.
+
+Required properties:
+ - compatible: Must be one of:
+ "renesas,prr"
+ "renesas,bsid"
+ - reg: Base address and length of the register block.
+
+
+Examples
+--------
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };