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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-06 08:07:28 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-06 08:07:28 +0200 |
| commit | bb2de9a333d17bb1b048ad208002501226b83f03 (patch) | |
| tree | 8ef2e876ba43af235c45cb2280885e9c67ba5548 /dts/Bindings/arm/tegra | |
| parent | 79e6629b02fb3a296b5dc70f16dec0f8d415ccf8 (diff) | |
| download | barebox-bb2de9a333d17bb1b048ad208002501226b83f03.tar.gz barebox-bb2de9a333d17bb1b048ad208002501226b83f03.tar.xz | |
dts: update to v4.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/tegra')
| -rw-r--r-- | dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt | 34 | ||||
| -rw-r--r-- | dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | 8 |
2 files changed, 41 insertions, 1 deletions
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt new file mode 100644 index 0000000000..078a58b030 --- /dev/null +++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -0,0 +1,34 @@ +NVIDIA Tegra Power Management Controller (PMC) + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-pmc": for Tegra186 +- reg: Must contain an (offset, length) pair of the register set for each + entry in reg-names. +- reg-names: Must include the following entries: + - "pmc" + - "wake" + - "aotag" + - "scratch" + +Optional properties: +- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. + +Example: + +SoC DTSI: + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0 0x0c360000 0 0x10000>, + <0 0x0c370000 0 0x10000>, + <0 0x0c380000 0 0x10000>, + <0 0x0c390000 0 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + }; + +Board DTS: + + pmc@c360000 { + nvidia,invert-interrupt; + }; diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt index ccf0adddc8..a855c1bffc 100644 --- a/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt +++ b/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt @@ -1,7 +1,13 @@ NVIDIA Tegra Flow Controller Required properties: -- compatible: Should be "nvidia,tegra<chip>-flowctrl" +- compatible: Should contain one of the following: + - "nvidia,tegra20-flowctrl": for Tegra20 + - "nvidia,tegra30-flowctrl": for Tegra30 + - "nvidia,tegra114-flowctrl": for Tegra114 + - "nvidia,tegra124-flowctrl": for Tegra124 + - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132 + - "nvidia,tegra210-flowctrl": for Tegra210 - reg: Should contain one register range (address and length) Example: |