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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-29 14:38:07 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-29 14:38:07 +0200 |
commit | d9a15385467936649b6c2cfeb7ab377002ddce0f (patch) | |
tree | 39175107fc884a29fbba83f47d104f493833fe19 /dts/Bindings/bus | |
parent | bfe946c9593513b0ad1b440bcd997b263487b945 (diff) | |
download | barebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.gz barebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.xz |
dts: update to v4.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/bus')
-rw-r--r-- | dts/Bindings/bus/nvidia,tegra210-aconnect.txt | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt new file mode 100644 index 0000000000..7ff13be175 --- /dev/null +++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt @@ -0,0 +1,45 @@ +NVIDIA Tegra ACONNECT Bus + +The Tegra ACONNECT bus is an AXI switch which is used to connnect various +components inside the Audio Processing Engine (APE). All CPU accesses to +the APE subsystem go through the ACONNECT via an APB to AXI wrapper. + +Required properties: +- compatible: Must be "nvidia,tegra210-aconnect". +- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE), + and APE interface clock (TEGRA210_CLK_APB2APE). +- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding + 'clocks' entries. +- power-domains: Must contain a phandle that points to the audio powergate + (namely 'aud') for Tegra210. +- #address-cells: The number of cells used to represent physical base addresses + in the aconnect address space. Should be 1. +- #size-cells: The number of cells used to represent the size of an address + range in the aconnect address space. Should be 1. +- ranges: Mapping of the aconnect address space to the CPU address space. + +All devices accessed via the ACONNNECT are described by child-nodes. + +Example: + + aconnect@702c0000 { + compatible = "nvidia,tegra210-aconnect"; + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&pd_audio>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; + + status = "disabled"; + + child1 { + ... + }; + + child2 { + ... + }; + }; |