dts: update to v4.2-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 24 insertions, 0 deletions

diff --git a/dts/Bindings/clock/renesas,h8300-div-clock.txt b/dts/Bindings/clock/renesas,h8300-div-clock.txt
new file mode 100644
index 0000000000..36c2b52824
--- /dev/null
+++ b/dts/Bindings/clock/renesas,h8300-div-clock.txt
@@ -0,0 +1,24 @@
+* Renesas H8/300 divider clock
+
+Required Properties:
+
+  - compatible: Must be "renesas,sh73a0-h8300-div-clock"
+
+  - clocks: Reference to the parent clocks ("extal1" and "extal2")
+
+  - #clock-cells: Must be 1
+
+  - reg: Base address and length of the divide rate selector
+
+  - renesas,width: bit width of selector
+
+Example
+-------
+
+		cclk: cclk {
+			compatible = "renesas,h8300-div-clock";
+			clocks = <&xclk>;
+			#clock-cells = <0>;
+			reg = <0xfee01b 2>;
+			renesas,width = <2>;
+		};