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authorSascha Hauer <s.hauer@pengutronix.de>2020-11-09 12:38:26 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-11-09 13:42:10 +0100
commit119c632f12509eab4bc58daf629c4b16fffcedca (patch)
tree34366b3095d957178b46be47f628a3926ad35ac3 /dts/Bindings/clock
parent89b766c63f94b5fe94db75a6f197c9e6c0f9da7e (diff)
downloadbarebox-119c632f12509eab4bc58daf629c4b16fffcedca.tar.gz
barebox-119c632f12509eab4bc58daf629c4b16fffcedca.tar.xz
dts: update to v5.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock')
-rw-r--r--dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml7
-rw-r--r--dts/Bindings/clock/arm,syscon-icst.yaml2
-rw-r--r--dts/Bindings/clock/baikal,bt1-ccu-div.yaml6
-rw-r--r--dts/Bindings/clock/baikal,bt1-ccu-pll.yaml2
-rw-r--r--dts/Bindings/clock/idt,versaclock5.yaml20
-rw-r--r--dts/Bindings/clock/imx23-clock.yaml4
-rw-r--r--dts/Bindings/clock/imx28-clock.yaml6
-rw-r--r--dts/Bindings/clock/imx6q-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6sl-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6sll-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6sx-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6ul-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx8m-clock.yaml125
-rw-r--r--dts/Bindings/clock/imx8mm-clock.yaml68
-rw-r--r--dts/Bindings/clock/imx8mn-clock.yaml70
-rw-r--r--dts/Bindings/clock/imx8mp-clock.yaml70
-rw-r--r--dts/Bindings/clock/imx8mq-clock.yaml72
-rw-r--r--dts/Bindings/clock/imx8qxp-lpcg.yaml2
-rw-r--r--dts/Bindings/clock/intel,cgu-lgm.yaml2
-rw-r--r--dts/Bindings/clock/qcom,dispcc-sm8x50.yaml93
-rw-r--r--dts/Bindings/clock/qcom,gcc-sm8250.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sc7180-videocc.yaml65
-rw-r--r--dts/Bindings/clock/qcom,videocc.yaml (renamed from dts/Bindings/clock/qcom,sdm845-videocc.yaml)18
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.yaml1
-rw-r--r--dts/Bindings/clock/sifive/fu540-prci.txt46
-rw-r--r--dts/Bindings/clock/sifive/fu540-prci.yaml60
-rw-r--r--dts/Bindings/clock/sprd,sc9863a-clk.yaml2
-rw-r--r--dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml2
28 files changed, 343 insertions, 412 deletions
diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
index 4d382128b7..3b45344ed7 100644
--- a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -36,6 +36,8 @@ properties:
- allwinner,sun9i-a80-ccu
- allwinner,sun50i-a64-ccu
- allwinner,sun50i-a64-r-ccu
+ - allwinner,sun50i-a100-ccu
+ - allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h5-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h6-r-ccu
@@ -78,6 +80,7 @@ if:
- allwinner,sun8i-a83t-r-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun50i-a64-r-ccu
+ - allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h6-r-ccu
then:
@@ -94,7 +97,9 @@ else:
if:
properties:
compatible:
- const: allwinner,sun50i-h6-ccu
+ enum:
+ - allwinner,sun50i-a100-ccu
+ - allwinner,sun50i-h6-ccu
then:
properties:
diff --git a/dts/Bindings/clock/arm,syscon-icst.yaml b/dts/Bindings/clock/arm,syscon-icst.yaml
index 444aeea27d..eb241587ef 100644
--- a/dts/Bindings/clock/arm,syscon-icst.yaml
+++ b/dts/Bindings/clock/arm,syscon-icst.yaml
@@ -89,6 +89,8 @@ required:
- compatible
- clocks
+additionalProperties: false
+
examples:
- |
vco1: clock {
diff --git a/dts/Bindings/clock/baikal,bt1-ccu-div.yaml b/dts/Bindings/clock/baikal,bt1-ccu-div.yaml
index 2821425ee4..bd4cefbb12 100644
--- a/dts/Bindings/clock/baikal,bt1-ccu-div.yaml
+++ b/dts/Bindings/clock/baikal,bt1-ccu-div.yaml
@@ -134,7 +134,11 @@ properties:
"#reset-cells":
const: 1
-unevaluatedProperties: false
+ clocks: true
+
+ clock-names: true
+
+additionalProperties: false
required:
- compatible
diff --git a/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml b/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml
index 97131bfa6f..624984d51c 100644
--- a/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml
+++ b/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml
@@ -101,7 +101,7 @@ properties:
clock-names:
const: ref_clk
-unevaluatedProperties: false
+additionalProperties: false
required:
- compatible
diff --git a/dts/Bindings/clock/idt,versaclock5.yaml b/dts/Bindings/clock/idt,versaclock5.yaml
index 28c6461b9a..2ac1131fd9 100644
--- a/dts/Bindings/clock/idt,versaclock5.yaml
+++ b/dts/Bindings/clock/idt,versaclock5.yaml
@@ -50,6 +50,15 @@ properties:
'#clock-cells':
const: 1
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ xin, clkin ]
+ clocks:
+ minItems: 1
+ maxItems: 2
+
patternProperties:
"^OUT[1-4]$":
type: object
@@ -93,19 +102,12 @@ allOf:
maxItems: 1
else:
# Devices without builtin crystal
- properties:
- clock-names:
- minItems: 1
- maxItems: 2
- items:
- enum: [ xin, clkin ]
- clocks:
- minItems: 1
- maxItems: 2
required:
- clock-names
- clocks
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clk/versaclock.h>
diff --git a/dts/Bindings/clock/imx23-clock.yaml b/dts/Bindings/clock/imx23-clock.yaml
index ad21899981..5e296a00e1 100644
--- a/dts/Bindings/clock/imx23-clock.yaml
+++ b/dts/Bindings/clock/imx23-clock.yaml
@@ -87,6 +87,8 @@ examples:
serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
- interrupts = <24 25 23>;
+ interrupts = <24>;
clocks = <&clks 32>;
+ dmas = <&dma_apbx 6>, <&dma_apbx 7>;
+ dma-names = "rx", "tx";
};
diff --git a/dts/Bindings/clock/imx28-clock.yaml b/dts/Bindings/clock/imx28-clock.yaml
index f1af110812..f831b780f9 100644
--- a/dts/Bindings/clock/imx28-clock.yaml
+++ b/dts/Bindings/clock/imx28-clock.yaml
@@ -108,8 +108,10 @@ examples:
};
serial@8006a000 {
- compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ compatible = "fsl,imx28-auart";
reg = <0x8006a000 0x2000>;
- interrupts = <112 70 71>;
+ interrupts = <112>;
+ dmas = <&dma_apbx 8>, <&dma_apbx 9>;
+ dma-names = "rx", "tx";
clocks = <&clks 45>;
};
diff --git a/dts/Bindings/clock/imx6q-clock.yaml b/dts/Bindings/clock/imx6q-clock.yaml
index 92a8e545e2..4f4637eddb 100644
--- a/dts/Bindings/clock/imx6q-clock.yaml
+++ b/dts/Bindings/clock/imx6q-clock.yaml
@@ -57,6 +57,8 @@ required:
- interrupts
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6sl-clock.yaml b/dts/Bindings/clock/imx6sl-clock.yaml
index c97bf95b41..b83c8f43d6 100644
--- a/dts/Bindings/clock/imx6sl-clock.yaml
+++ b/dts/Bindings/clock/imx6sl-clock.yaml
@@ -33,6 +33,8 @@ required:
- interrupts
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6sll-clock.yaml b/dts/Bindings/clock/imx6sll-clock.yaml
index de48924be1..484894a4b2 100644
--- a/dts/Bindings/clock/imx6sll-clock.yaml
+++ b/dts/Bindings/clock/imx6sll-clock.yaml
@@ -49,6 +49,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6sx-clock.yaml b/dts/Bindings/clock/imx6sx-clock.yaml
index e50cddee43..e6c795657c 100644
--- a/dts/Bindings/clock/imx6sx-clock.yaml
+++ b/dts/Bindings/clock/imx6sx-clock.yaml
@@ -53,6 +53,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6ul-clock.yaml b/dts/Bindings/clock/imx6ul-clock.yaml
index 36ce7667c9..6a51a3f51c 100644
--- a/dts/Bindings/clock/imx6ul-clock.yaml
+++ b/dts/Bindings/clock/imx6ul-clock.yaml
@@ -49,6 +49,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx8m-clock.yaml b/dts/Bindings/clock/imx8m-clock.yaml
new file mode 100644
index 0000000000..625f573a7b
--- /dev/null
+++ b/dts/Bindings/clock/imx8m-clock.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Family Clock Control Module Binding
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+description: |
+ NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
+ controller, which generates and supplies to all modules.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-ccm
+ - fsl,imx8mn-ccm
+ - fsl,imx8mp-ccm
+ - fsl,imx8mq-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 6
+ maxItems: 7
+
+ clock-names:
+ minItems: 6
+ maxItems: 7
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
+ for the full list of i.MX8M clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-ccm
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ items:
+ - description: 32k osc
+ - description: 25m osc
+ - description: 27m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+ clock-names:
+ minItems: 7
+ maxItems: 7
+ items:
+ - const: ckil
+ - const: osc_25m
+ - const: osc_27m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+ else:
+ properties:
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+ items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ clock-controller@30380000 {
+ compatible = "fsl,imx8mm-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+ - |
+ clock-controller@30390000 {
+ compatible = "fsl,imx8mq-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>,
+ <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
+ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4";
+ };
+
+...
diff --git a/dts/Bindings/clock/imx8mm-clock.yaml b/dts/Bindings/clock/imx8mm-clock.yaml
deleted file mode 100644
index ec830db136..0000000000
--- a/dts/Bindings/clock/imx8mm-clock.yaml
+++ /dev/null
@@ -1,68 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Mini Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description: |
- NXP i.MX8M Mini clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mm-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 24m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: osc_32k
- - const: osc_24m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
- for the full list of i.MX8M Mini clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mm-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8mn-clock.yaml b/dts/Bindings/clock/imx8mn-clock.yaml
deleted file mode 100644
index bdaa29616a..0000000000
--- a/dts/Bindings/clock/imx8mn-clock.yaml
+++ /dev/null
@@ -1,70 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Nano Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description: |
- NXP i.MX8M Nano clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mn-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 24m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: osc_32k
- - const: osc_24m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
- for the full list of i.MX8M Nano clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mn-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
- <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1",
- "clk_ext2", "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8mp-clock.yaml b/dts/Bindings/clock/imx8mp-clock.yaml
deleted file mode 100644
index 4351a1dbb4..0000000000
--- a/dts/Bindings/clock/imx8mp-clock.yaml
+++ /dev/null
@@ -1,70 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Plus Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description:
- NXP i.MX8M Plus clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mp-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 24m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: osc_32k
- - const: osc_24m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
- for the full list of i.MX8M Plus clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mp-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
- <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1",
- "clk_ext2", "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8mq-clock.yaml b/dts/Bindings/clock/imx8mq-clock.yaml
deleted file mode 100644
index 05d7d1471e..0000000000
--- a/dts/Bindings/clock/imx8mq-clock.yaml
+++ /dev/null
@@ -1,72 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Quad Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description: |
- NXP i.MX8M Quad clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mq-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 25m osc
- - description: 27m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: ckil
- - const: osc_25m
- - const: osc_27m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
- for the full list of i.MX8M Quad clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mq-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
- <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "ckil", "osc_25m", "osc_27m",
- "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8qxp-lpcg.yaml b/dts/Bindings/clock/imx8qxp-lpcg.yaml
index 1d5e9bcce4..33f3010f48 100644
--- a/dts/Bindings/clock/imx8qxp-lpcg.yaml
+++ b/dts/Bindings/clock/imx8qxp-lpcg.yaml
@@ -62,7 +62,7 @@ examples:
};
mmc@5b010000 {
- compatible = "fsl,imx8qxp-usdhc";
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
diff --git a/dts/Bindings/clock/intel,cgu-lgm.yaml b/dts/Bindings/clock/intel,cgu-lgm.yaml
index 6dc1414bfb..f3e1a700a2 100644
--- a/dts/Bindings/clock/intel,cgu-lgm.yaml
+++ b/dts/Bindings/clock/intel,cgu-lgm.yaml
@@ -33,6 +33,8 @@ required:
- reg
- '#clock-cells'
+additionalProperties: false
+
examples:
- |
cgu: clock-controller@e0200000 {
diff --git a/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml b/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml
new file mode 100644
index 0000000000..0cdf53f41f
--- /dev/null
+++ b/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+
+maintainers:
+ - Jonathan Marek <jonathan@marek.ca>
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on SM8150 and SM8250.
+
+ See also:
+ dt-bindings/clock/qcom,dispcc-sm8150.h
+ dt-bindings/clock/qcom,dispcc-sm8250.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm8150-dispcc
+ - qcom,sm8250-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dsi1_phy_pll_out_byteclk
+ - const: dsi1_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm8250-dispcc";
+ reg = <0x0af00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi1_phy 0>,
+ <&dsi1_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc-sm8250.yaml b/dts/Bindings/clock/qcom,gcc-sm8250.yaml
index a5766ff890..80bd6caf5b 100644
--- a/dts/Bindings/clock/qcom,gcc-sm8250.yaml
+++ b/dts/Bindings/clock/qcom,gcc-sm8250.yaml
@@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/Bindings/clock/qcom,sc7180-videocc.yaml b/dts/Bindings/clock/qcom,sc7180-videocc.yaml
deleted file mode 100644
index 2feea2b91a..0000000000
--- a/dts/Bindings/clock/qcom,sc7180-videocc.yaml
+++ /dev/null
@@ -1,65 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Video Clock & Reset Controller Binding for SC7180
-
-maintainers:
- - Taniya Das <tdas@codeaurora.org>
-
-description: |
- Qualcomm video clock control module which supports the clocks, resets and
- power domains on SC7180.
-
- See also dt-bindings/clock/qcom,videocc-sc7180.h.
-
-properties:
- compatible:
- const: qcom,sc7180-videocc
-
- clocks:
- items:
- - description: Board XO source
-
- clock-names:
- items:
- - const: bi_tcxo
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,rpmh.h>
- clock-controller@ab00000 {
- compatible = "qcom,sc7180-videocc";
- reg = <0x0ab00000 0x10000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "bi_tcxo";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-...
diff --git a/dts/Bindings/clock/qcom,sdm845-videocc.yaml b/dts/Bindings/clock/qcom,videocc.yaml
index f7a0cf53d5..567202942b 100644
--- a/dts/Bindings/clock/qcom,sdm845-videocc.yaml
+++ b/dts/Bindings/clock/qcom,videocc.yaml
@@ -1,23 +1,31 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Video Clock & Reset Controller Binding for SDM845
+title: Qualcomm Video Clock & Reset Controller Binding
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm video clock control module which supports the clocks, resets and
- power domains on SDM845.
+ power domains on SDM845/SC7180/SM8150/SM8250.
- See also dt-bindings/clock/qcom,videocc-sdm845.h.
+ See also:
+ dt-bindings/clock/qcom,videocc-sc7180.h
+ dt-bindings/clock/qcom,videocc-sdm845.h
+ dt-bindings/clock/qcom,videocc-sm8150.h
+ dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:
- const: qcom,sdm845-videocc
+ enum:
+ - qcom,sc7180-videocc
+ - qcom,sdm845-videocc
+ - qcom,sm8150-videocc
+ - qcom,sm8250-videocc
clocks:
items:
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.yaml b/dts/Bindings/clock/renesas,cpg-mssr.yaml
index e13aee8ab6..9b414fbde6 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.yaml
+++ b/dts/Bindings/clock/renesas,cpg-mssr.yaml
@@ -47,6 +47,7 @@ properties:
- renesas,r8a77980-cpg-mssr # R-Car V3H
- renesas,r8a77990-cpg-mssr # R-Car E3
- renesas,r8a77995-cpg-mssr # R-Car D3
+ - renesas,r8a779a0-cpg-mssr # R-Car V3U
reg:
maxItems: 1
diff --git a/dts/Bindings/clock/sifive/fu540-prci.txt b/dts/Bindings/clock/sifive/fu540-prci.txt
deleted file mode 100644
index 349808f4fb..0000000000
--- a/dts/Bindings/clock/sifive/fu540-prci.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-SiFive FU540 PRCI bindings
-
-On the FU540 family of SoCs, most system-wide clock and reset integration
-is via the PRCI IP block.
-
-Required properties:
-- compatible: Should be "sifive,<chip>-prci". Only one value is
- supported: "sifive,fu540-c000-prci"
-- reg: Should describe the PRCI's register target physical address region
-- clocks: Should point to the hfclk device tree node and the rtcclk
- device tree node. The RTC clock here is not a time-of-day clock,
- but is instead a high-stability clock source for system timers
- and cycle counters.
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock via the clock ID
-macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
-These macros begin with PRCI_CLK_.
-
-The hfclk and rtcclk nodes are required, and represent physical
-crystals or resonators located on the PCB. These nodes should be present
-underneath /, rather than /soc.
-
-Examples:
-
-/* under /, in PCB-specific DT data */
-hfclk: hfclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <33333333>;
- clock-output-names = "hfclk";
-};
-rtcclk: rtcclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1000000>;
- clock-output-names = "rtcclk";
-};
-
-/* under /soc, in SoC-specific DT data */
-prci: clock-controller@10000000 {
- compatible = "sifive,fu540-c000-prci";
- reg = <0x0 0x10000000 0x0 0x1000>;
- clocks = <&hfclk>, <&rtcclk>;
- #clock-cells = <1>;
-};
diff --git a/dts/Bindings/clock/sifive/fu540-prci.yaml b/dts/Bindings/clock/sifive/fu540-prci.yaml
new file mode 100644
index 0000000000..c3be1b6000
--- /dev/null
+++ b/dts/Bindings/clock/sifive/fu540-prci.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
+
+maintainers:
+ - Sagar Kadam <sagar.kadam@sifive.com>
+ - Paul Walmsley <paul.walmsley@sifive.com>
+
+description:
+ On the FU540 family of SoCs, most system-wide clock and reset integration
+ is via the PRCI IP block.
+ The clock consumer should specify the desired clock via the clock ID
+ macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
+ These macros begin with PRCI_CLK_.
+
+ The hfclk and rtcclk nodes are required, and represent physical
+ crystals or resonators located on the PCB. These nodes should be present
+ underneath /, rather than /soc.
+
+properties:
+ compatible:
+ const: sifive,fu540-c000-prci
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: high frequency clock.
+ - description: RTL clock.
+
+ clock-names:
+ items:
+ - const: hfclk
+ - const: rtcclk
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x10000000 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/sprd,sc9863a-clk.yaml b/dts/Bindings/clock/sprd,sc9863a-clk.yaml
index c6d0915186..4069e09cb6 100644
--- a/dts/Bindings/clock/sprd,sc9863a-clk.yaml
+++ b/dts/Bindings/clock/sprd,sc9863a-clk.yaml
@@ -73,6 +73,8 @@ else:
The 'reg' property for the clock node is also required if there is a sub
range of registers for the clocks.
+additionalProperties: false
+
examples:
- |
ap_clk: clock-controller@21500000 {
diff --git a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
index 869b18ac88..6b419a9878 100644
--- a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
+++ b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
@@ -26,6 +26,8 @@ required:
- "#clock-cells"
- reg
+additionalProperties: false
+
examples:
- |
ehrpwm_tbclk: syscon@4140 {