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authorSascha Hauer <s.hauer@pengutronix.de>2019-10-15 10:55:58 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-10-15 10:55:58 +0200
commit2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch)
tree468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/Bindings/clock
parent785f926d4527184194b6424bc39ce367e2cea7d8 (diff)
downloadbarebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz
barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock')
-rw-r--r--dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml1
-rw-r--r--dts/Bindings/clock/amlogic,axg-audio-clkc.txt1
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-clkc.txt1
-rw-r--r--dts/Bindings/clock/brcm,bcm2835-cprman.txt4
-rw-r--r--dts/Bindings/clock/imx8mn-clock.yaml112
-rw-r--r--dts/Bindings/clock/qcom,gcc.txt21
-rw-r--r--dts/Bindings/clock/qcom,rpmh-clk.txt7
-rw-r--r--dts/Bindings/clock/renesas,emev2-smu.txt (renamed from dts/Bindings/clock/emev2-clock.txt)0
-rw-r--r--dts/Bindings/clock/rockchip,rk3308-cru.txt60
-rw-r--r--dts/Bindings/clock/ti,cdce925.txt4
10 files changed, 209 insertions, 2 deletions
diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
index fa4d143a73..64938fdaea 100644
--- a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -31,6 +31,7 @@ properties:
- allwinner,sun8i-h3-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun8i-r40-ccu
+ - allwinner,sun8i-v3-ccu
- allwinner,sun8i-v3s-ccu
- allwinner,sun9i-a80-ccu
- allwinner,sun50i-a64-ccu
diff --git a/dts/Bindings/clock/amlogic,axg-audio-clkc.txt b/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
index 0f777749f4..b3957d10d2 100644
--- a/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
+++ b/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
@@ -22,6 +22,7 @@ Required Properties:
components.
- resets : phandle of the internal reset line
- #clock-cells : should be 1.
+- #reset-cells : should be 1 on the g12a (and following) soc family
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
diff --git a/dts/Bindings/clock/amlogic,gxbb-clkc.txt b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
index 6eaa520923..7ccecd5c02 100644
--- a/dts/Bindings/clock/amlogic,gxbb-clkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
@@ -11,6 +11,7 @@ Required Properties:
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
+ "amlogic,sm1-clkc" for SM1 SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
diff --git a/dts/Bindings/clock/brcm,bcm2835-cprman.txt b/dts/Bindings/clock/brcm,bcm2835-cprman.txt
index dd906db34b..9e0b03a651 100644
--- a/dts/Bindings/clock/brcm,bcm2835-cprman.txt
+++ b/dts/Bindings/clock/brcm,bcm2835-cprman.txt
@@ -12,7 +12,9 @@ clock generators, but a few (like the ARM or HDMI) will source from
the PLL dividers directly.
Required properties:
-- compatible: Should be "brcm,bcm2835-cprman"
+- compatible: should be one of the following,
+ "brcm,bcm2711-cprman"
+ "brcm,bcm2835-cprman"
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835.h
- reg: Specifies base physical address and size of the registers
diff --git a/dts/Bindings/clock/imx8mn-clock.yaml b/dts/Bindings/clock/imx8mn-clock.yaml
new file mode 100644
index 0000000000..622f3658bd
--- /dev/null
+++ b/dts/Bindings/clock/imx8mn-clock.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Nano Clock Control Module Binding
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+description: |
+ NXP i.MX8M Nano clock control module is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+ const: fsl,imx8mn-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+ items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+ '#clock-cells':
+ const: 1
+ description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
+ for the full list of i.MX8M Nano clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+examples:
+ # Clock Control Module node:
+ - |
+ clk: clock-controller@30380000 {
+ compatible = "fsl,imx8mn-ccm";
+ reg = <0x0 0x30380000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
+ <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4";
+ };
+
+ # Required external clocks for Clock Control Module node:
+ - |
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext2";
+ };
+
+ clk_ext3: clock-ext3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext3";
+ };
+
+ clk_ext4: clock-ext4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <133000000>;
+ clock-output-names = "clk_ext4";
+ };
+
+...
diff --git a/dts/Bindings/clock/qcom,gcc.txt b/dts/Bindings/clock/qcom,gcc.txt
index 8661c3cd3c..d14362ad41 100644
--- a/dts/Bindings/clock/qcom,gcc.txt
+++ b/dts/Bindings/clock/qcom,gcc.txt
@@ -23,6 +23,7 @@ Required properties :
"qcom,gcc-sdm630"
"qcom,gcc-sdm660"
"qcom,gcc-sdm845"
+ "qcom,gcc-sm8150"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
- protected-clocks : Protected clock specifier list as per common clock
binding.
+For SM8150 only:
+ - clocks: a list of phandles and clock-specifier pairs,
+ one for each entry in clock-names.
+ - clock-names: "bi_tcxo" (required)
+ "sleep_clk" (optional)
+ "aud_ref_clock" (optional)
+
Example:
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
+
+Example of GCC with clocks
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sm8150";
+ reg = <0x00100000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo",
+ "sleep_clk";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>;
+ };
diff --git a/dts/Bindings/clock/qcom,rpmh-clk.txt b/dts/Bindings/clock/qcom,rpmh-clk.txt
index 3c007653da..365bbde599 100644
--- a/dts/Bindings/clock/qcom,rpmh-clk.txt
+++ b/dts/Bindings/clock/qcom,rpmh-clk.txt
@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
other hardware subsystems via RSC to control clocks.
Required properties :
-- compatible : shall contain "qcom,sdm845-rpmh-clk"
+- compatible : must be one of:
+ "qcom,sdm845-rpmh-clk"
+ "qcom,sm8150-rpmh-clk"
- #clock-cells : must contain 1
+- clocks: a list of phandles and clock-specifier pairs,
+ one for each entry in clock-names.
+- clock-names: Parent board clock: "xo".
Example :
diff --git a/dts/Bindings/clock/emev2-clock.txt b/dts/Bindings/clock/renesas,emev2-smu.txt
index 268ca61545..268ca61545 100644
--- a/dts/Bindings/clock/emev2-clock.txt
+++ b/dts/Bindings/clock/renesas,emev2-smu.txt
diff --git a/dts/Bindings/clock/rockchip,rk3308-cru.txt b/dts/Bindings/clock/rockchip,rk3308-cru.txt
new file mode 100644
index 0000000000..9b151c5b0c
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3308-cru.txt
@@ -0,0 +1,60 @@
+* Rockchip RK3308 Clock and Reset Unit
+
+The RK3308 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: CRU should be "rockchip,rk3308-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
+ "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
+ "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
+ - "mac_clkin" - external MAC clock - optional
+
+Example: Clock controller node:
+
+ cru: clock-controller@ff500000 {
+ compatible = "rockchip,rk3308-cru";
+ reg = <0x0 0xff500000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@ff0a0000 {
+ compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff0a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/clock/ti,cdce925.txt b/dts/Bindings/clock/ti,cdce925.txt
index 0d01f2d5cc..26544c8520 100644
--- a/dts/Bindings/clock/ti,cdce925.txt
+++ b/dts/Bindings/clock/ti,cdce925.txt
@@ -24,6 +24,8 @@ Required properties:
Optional properties:
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
board, or to compensate for external influences.
+- vdd-supply: A regulator node for Vdd
+- vddout-supply: A regulator node for Vddout
For all PLL1, PLL2, ... an optional child node can be used to specify spread
spectrum clocking parameters for a board.
@@ -41,6 +43,8 @@ Example:
clocks = <&xtal_27Mhz>;
#clock-cells = <1>;
xtal-load-pf = <5>;
+ vdd-supply = <&1v8-reg>;
+ vddout-supply = <&3v3-reg>;
/* PLL options to get SSC 1% centered */
PLL2 {
spread-spectrum = <4>;