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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-06-13 07:30:56 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-06-13 07:30:56 +0200 |
| commit | 6e6cb6c407a220b61d66e957713a919f4afbc54a (patch) | |
| tree | 7fc2edda7824021c5cfb5af2ee5fa541c526d577 /dts/Bindings/clock | |
| parent | a4f4bc65b33164eb8c19bcff9834cc87bcc845bb (diff) | |
| download | barebox-6e6cb6c407a220b61d66e957713a919f4afbc54a.tar.gz barebox-6e6cb6c407a220b61d66e957713a919f4afbc54a.tar.xz | |
dts: update to v4.6-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock')
| -rw-r--r-- | dts/Bindings/clock/qca,ath79-pll.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/dts/Bindings/clock/qca,ath79-pll.txt b/dts/Bindings/clock/qca,ath79-pll.txt index e0fc2c11dd..241fb0545b 100644 --- a/dts/Bindings/clock/qca,ath79-pll.txt +++ b/dts/Bindings/clock/qca,ath79-pll.txt @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. Required Properties: -- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following +- compatible: has to be "qca,<soctype>-pll" and one of the following fallbacks: - "qca,ar7100-pll" - "qca,ar7240-pll" @@ -21,8 +21,8 @@ Optional properties: Example: - memory-controller@18050000 { - compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; + pll-controller@18050000 { + compatible = "qca,ar9132-pll", "qca,ar9130-pll"; reg = <0x18050000 0x20>; clock-names = "ref"; |