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authorSascha Hauer <s.hauer@pengutronix.de>2022-05-05 10:26:19 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-05-05 10:26:19 +0200
commit7d72033412f8dc9e5a31a1f87f469d9627897fe6 (patch)
tree34577e6eafb0a257653c2c9e399a9f32cc9cd338 /dts/Bindings/clock
parent30d9267f2e7cb9f25968084f15d1ae117c7fa7a2 (diff)
downloadbarebox-7d72033412f8dc9e5a31a1f87f469d9627897fe6.tar.gz
barebox-7d72033412f8dc9e5a31a1f87f469d9627897fe6.tar.xz
dts: update to v5.18-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock')
-rw-r--r--dts/Bindings/clock/microchip,mpfs.yaml13
1 files changed, 11 insertions, 2 deletions
diff --git a/dts/Bindings/clock/microchip,mpfs.yaml b/dts/Bindings/clock/microchip,mpfs.yaml
index 0c15afa221..016a4f378b 100644
--- a/dts/Bindings/clock/microchip,mpfs.yaml
+++ b/dts/Bindings/clock/microchip,mpfs.yaml
@@ -22,7 +22,16 @@ properties:
const: microchip,mpfs-clkcfg
reg:
- maxItems: 1
+ items:
+ - description: |
+ clock config registers:
+ These registers contain enable, reset & divider tables for the, cpu,
+ axi, ahb and rtc/mtimer reference clocks as well as enable and reset
+ for the peripheral clocks.
+ - description: |
+ mss pll dri registers:
+ Block of registers responsible for dynamic reconfiguration of the mss
+ pll
clocks:
maxItems: 1
@@ -51,7 +60,7 @@ examples:
#size-cells = <2>;
clkcfg: clock-controller@20002000 {
compatible = "microchip,mpfs-clkcfg";
- reg = <0x0 0x20002000 0x0 0x1000>;
+ reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&ref>;
#clock-cells = <1>;
};