diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-14 09:05:53 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-18 08:32:25 +0100 |
| commit | 81ce4a7dec8ba066c73692e10634091b14c1e494 (patch) | |
| tree | d61574b25fda47711e3efab57c7a5739de477565 /dts/Bindings/clock | |
| parent | 84b7f86bef670f6751d67131738555fa53ca3f6b (diff) | |
| download | barebox-81ce4a7dec8ba066c73692e10634091b14c1e494.tar.gz barebox-81ce4a7dec8ba066c73692e10634091b14c1e494.tar.xz | |
dts: update to v5.6-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock')
74 files changed, 3901 insertions, 607 deletions
diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml new file mode 100644 index 0000000000..558db4b6ed --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AHB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-ahb-clk + - allwinner,sun6i-a31-ahb1-clk + - allwinner,sun8i-h3-ahb2-clk + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-ahb-clk + + then: + properties: + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-ahb1-clk + + then: + properties: + clocks: + maxItems: 4 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-ahb2-clk + + then: + properties: + clocks: + maxItems: 2 + +examples: + - | + ahb@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + clock-output-names = "ahb"; + }; + + - | + ahb1@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + - | + ahb2_clk@1c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6d2>; + clock-output-names = "ahb2"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml new file mode 100644 index 0000000000..b1e3d739be --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 APB0 Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-apb0-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + apb0@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml new file mode 100644 index 0000000000..51b7a6d4ea --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 APB1 Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-apb1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml new file mode 100644 index 0000000000..d801158e15 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AXI Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-axi-clk + - allwinner,sun8i-a23-axi-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + axi@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + - | + axi_clk@1c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml new file mode 100644 index 0000000000..0dfafba1a1 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 CPU Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-cpu-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + cpu@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml new file mode 100644 index 0000000000..7484a7ab7d --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-display-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml new file mode 100644 index 0000000000..ed1b2126a8 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Bus Gates Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + compatible: + oneOf: + - const: allwinner,sun4i-a10-gates-clk + - const: allwinner,sun4i-a10-axi-gates-clk + - const: allwinner,sun4i-a10-ahb-gates-clk + - const: allwinner,sun5i-a10s-ahb-gates-clk + - const: allwinner,sun5i-a13-ahb-gates-clk + - const: allwinner,sun7i-a20-ahb-gates-clk + - const: allwinner,sun6i-a31-ahb1-gates-clk + - const: allwinner,sun8i-a23-ahb1-gates-clk + - const: allwinner,sun9i-a80-ahb0-gates-clk + - const: allwinner,sun9i-a80-ahb1-gates-clk + - const: allwinner,sun9i-a80-ahb2-gates-clk + - const: allwinner,sun4i-a10-apb0-gates-clk + - const: allwinner,sun5i-a10s-apb0-gates-clk + - const: allwinner,sun5i-a13-apb0-gates-clk + - const: allwinner,sun7i-a20-apb0-gates-clk + - const: allwinner,sun9i-a80-apb0-gates-clk + - const: allwinner,sun8i-a83t-apb0-gates-clk + - const: allwinner,sun4i-a10-apb1-gates-clk + - const: allwinner,sun5i-a13-apb1-gates-clk + - const: allwinner,sun5i-a10s-apb1-gates-clk + - const: allwinner,sun6i-a31-apb1-gates-clk + - const: allwinner,sun7i-a20-apb1-gates-clk + - const: allwinner,sun8i-a23-apb1-gates-clk + - const: allwinner,sun9i-a80-apb1-gates-clk + - const: allwinner,sun6i-a31-apb2-gates-clk + - const: allwinner,sun8i-a23-apb2-gates-clk + - const: allwinner,sun8i-a83t-bus-gates-clk + - const: allwinner,sun9i-a80-apbs-gates-clk + - const: allwinner,sun4i-a10-dram-gates-clk + + - items: + - const: allwinner,sun5i-a13-dram-gates-clk + - const: allwinner,sun4i-a10-gates-clk + + - items: + - const: allwinner,sun8i-h3-apb0-gates-clk + - const: allwinner,sun4i-a10-gates-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-indices: + minItems: 1 + maxItems: 64 + + clock-output-names: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-indices + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-indices = <0>; + clock-output-names = "axi_dram"; + }; + + - | + clk@1c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <3>, + <4>, <5>, <6>, + <7>, <8>, <9>, + <10>, <11>, <12>, + <13>, <14>, <16>, + <17>, <18>, <20>, + <21>, <22>, <23>, + <24>, <25>, <26>, + <32>, <33>, <34>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <45>, + <46>, <47>, + <50>, <52>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", + "ahb_ohci1", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", + "ahb_nand", "ahb_sdram", "ahb_ace", + "ahb_emac", "ahb_ts", "ahb_spi0", + "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", + "ahb_ve", "ahb_tvd", "ahb_tve0", + "ahb_tve1", "ahb_lcd0", "ahb_lcd1", + "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", + "ahb_de_fe0", "ahb_de_fe1", + "ahb_mp", "ahb_mali400"; + }; + + + - | + clk@1c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-indices = <0>, <1>, + <2>, <3>, + <5>, <6>, + <7>, <10>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis", + "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml new file mode 100644 index 0000000000..18f131e262 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 MBUS Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun5i-a13-mbus-clk + - allwinner,sun8i-a23-mbus-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + + - | + clk@1c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml new file mode 100644 index 0000000000..5199285a66 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 1 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + There is three different outputs: the main clock, with the ID 0, + and the output and sample clocks, with the IDs 1 and 2, + respectively. + + compatible: + enum: + - allwinner,sun4i-a10-mmc-clk + - allwinner,sun9i-a80-mmc-clk + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 3 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-mmc-clk + +then: + properties: + clocks: + maxItems: 3 + +else: + properties: + clocks: + maxItems: 2 + +examples: + - | + clk@1c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + - | + clk@6000410 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x06000410 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc0", "mmc0_output", + "mmc0_sample"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml new file mode 100644 index 0000000000..3e2abe3e67 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 0 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +select: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun9i-a80-mod0-clk + + # The PRCM on the A31 and A23 will have the reg property missing, + # since it's set at the upper level node, and will be validated by + # PRCM's schema. Make sure we only validate standalone nodes. + required: + - compatible + - reg + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun9i-a80-mod0-clk + + reg: + maxItems: 1 + + clocks: + # On the A80, the PRCM mod0 clocks have 2 parents. + minItems: 2 + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + - | + clk@8001454 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x08001454 0x4>; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_ir"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml new file mode 100644 index 0000000000..7ddb55c75c --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 1 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-mod1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun4i-a10-pll2.h> + + clk@1c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml new file mode 100644 index 0000000000..69cfa4a3d5 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Gatable Oscillator Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-osc-clk + + reg: + maxItems: 1 + + clock-frequency: + description: > + Frequency of the main oscillator. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clock-frequency + - clock-output-names + +additionalProperties: false + +examples: + - | + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml new file mode 100644 index 0000000000..e9c4cf834a --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 CPU PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-pll1-clk + - allwinner,sun6i-a31-pll1-clk + - allwinner,sun8i-a23-pll1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "osc24M"; + }; + + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml new file mode 100644 index 0000000000..4b80a42fb3 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-pll3-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml new file mode 100644 index 0000000000..415bd77de5 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 DRAM PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the DRAM clock output, the second is meant + for peripherals on the SoC. + + compatible: + const: allwinner,sun4i-a10-pll5-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 2 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml new file mode 100644 index 0000000000..ec5652f760 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Peripheral PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the SATA clock output, the second is the + regular PLL output, the third is a PLL output at twice the rate. + + compatible: + const: allwinner,sun4i-a10-pll6-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 3 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml new file mode 100644 index 0000000000..0a335c615e --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-tcon-ch0-clk + - allwinner,sun4i-a10-tcon-ch1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-tcon-ch0-clk + +then: + required: + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clk@1c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + - | + clk@1c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml new file mode 100644 index 0000000000..cd95d25bfe --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 USB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-usb-clk + - allwinner,sun5i-a13-usb-clk + - allwinner,sun6i-a31-usb-clk + - allwinner,sun8i-a23-usb-clk + - allwinner,sun8i-h3-usb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + minItems: 2 + maxItems: 8 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-usb-clk + + then: + properties: + clock-output-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: allwinner,sun5i-a13-usb-clk + + then: + properties: + clock-output-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-usb-clk + + then: + properties: + clock-output-names: + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-a23-usb-clk + + then: + properties: + clock-output-names: + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-usb-clk + + then: + properties: + clock-output-names: + maxItems: 8 + +examples: + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", + "usb_ohci0", "usb_ohci1", + "usb_ohci2"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-a23-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", + "usb_hsic_12M", "usb_ohci0"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml new file mode 100644 index 0000000000..5dfd0c1c27 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ve-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video Engine Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-ve-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2013c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-ve-clk"; + reg = <0x01c2013c 0x4>; + clocks = <&pll4>; + clock-output-names = "ve"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml b/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml new file mode 100644 index 0000000000..99add7991c --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A13 AHB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun5i-a13-ahb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + ahb@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml b/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml new file mode 100644 index 0000000000..5f377205af --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Peripheral PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the regular PLL output, the second is a PLL + output at twice the rate. + + compatible: + const: allwinner,sun6i-a31-pll6-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 2 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml b/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml new file mode 100644 index 0000000000..59e5dce1b6 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A20 GMAC TX Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun7i-a20-gmac-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + description: > + The parent clocks shall be fixed rate dummy clocks at 25 MHz and + 125 MHz, respectively. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml b/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml new file mode 100644 index 0000000000..c745733bcf --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-out-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A20 Output Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun7i-a20-out-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c201f0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f0 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_a"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml new file mode 100644 index 0000000000..3f995d2b30 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t Display Engine 2/3 Clock Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + oneOf: + - const: allwinner,sun8i-a83t-de2-clk + - const: allwinner,sun8i-h3-de2-clk + - const: allwinner,sun8i-v3s-de2-clk + - const: allwinner,sun50i-a64-de2-clk + - const: allwinner,sun50i-h5-de2-clk + - const: allwinner,sun50i-h6-de2-clk + - items: + - const: allwinner,sun8i-r40-de2-clk + - const: allwinner,sun8i-h3-de2-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun8i-h3-ccu.h> + #include <dt-bindings/reset/sun8i-h3-ccu.h> + + de2_clocks: clock@1000000 { + compatible = "allwinner,sun8i-h3-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml b/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml new file mode 100644 index 0000000000..3eb2bf65b2 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Bus Gates Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + compatible: + const: allwinner,sun8i-h3-bus-gates-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-indices: + minItems: 1 + maxItems: 64 + + clock-output-names: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-indices + - clock-names + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, + <116>, <128>, <135>; + clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", + "bus_mmc1", "bus_mmc2", "bus_nand", + "bus_sdram", "bus_gmac", "bus_ts", + "bus_hstimer", "bus_spi0", + "bus_spi1", "bus_otg", + "bus_otg_ehci0", "bus_ehci1", + "bus_ehci2", "bus_ehci3", + "bus_otg_ohci0", "bus_ohci1", + "bus_ohci2", "bus_ohci3", "bus_ve", + "bus_lcd0", "bus_lcd1", "bus_deint", + "bus_csi", "bus_tve", "bus_hdmi", + "bus_de", "bus_gpu", "bus_msgbox", + "bus_spinlock", "bus_codec", + "bus_spdif", "bus_pio", "bus_ths", + "bus_i2s0", "bus_i2s1", "bus_i2s2", + "bus_i2c0", "bus_i2c1", "bus_i2c2", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_scr", "bus_ephy", "bus_dbg"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml new file mode 100644 index 0000000000..d178da90aa --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 AHB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-ahb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@6000060 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-ahb-clk"; + reg = <0x06000060 0x4>; + clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "ahb0"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml new file mode 100644 index 0000000000..0351c79bd2 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 APB0 Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun9i-a80-apb0-clk + - allwinner,sun9i-a80-apb1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@6000070 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb0-clk"; + reg = <0x06000070 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb0"; + }; + + - | + clk@6000074 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb1-clk"; + reg = <0x06000074 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb1"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml new file mode 100644 index 0000000000..24d5b2f1a3 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 CPUS Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-cpus-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@8001410 { + compatible = "allwinner,sun9i-a80-cpus-clk"; + reg = <0x08001410 0x4>; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; + clock-output-names = "cpus"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml new file mode 100644 index 0000000000..a82c7c7e94 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-de-clks + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: RAM Bus Clock + - description: Module Clock + + clock-names: + items: + - const: mod + - const: dram + - const: bus + + resets: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun9i-a80-ccu.h> + #include <dt-bindings/reset/sun9i-a80-ccu.h> + + de_clocks: clock@3000000 { + compatible = "allwinner,sun9i-a80-de-clks"; + reg = <0x03000000 0x30>; + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; + clock-names = "mod", "dram", "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml new file mode 100644 index 0000000000..07f38def7d --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 GT Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-gt-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@0600005c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-gt-clk"; + reg = <0x0600005c 0x4>; + clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "gt"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml new file mode 100644 index 0000000000..20dc115fa2 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 MMC Configuration Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +description: > + There is one clock/reset output per mmc controller. The number of + outputs is determined by the size of the address block, which is + related to the overall mmc block. + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-mmc-config-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + clock-output-names: + maxItems: 4 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c13000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-config-clk"; + reg = <0x01c13000 0x10>; + clocks = <&ahb0_gates 8>; + resets = <&ahb0_resets 8>; + clock-output-names = "mmc0_config", "mmc1_config", + "mmc2_config", "mmc3_config"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml new file mode 100644 index 0000000000..b76bab6a30 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Peripheral PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-pll4-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@600000c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pll4-clk"; + reg = <0x0600000c 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml new file mode 100644 index 0000000000..fa0ee03a52 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB Clock Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-clocks + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + + clock-names: + items: + - const: bus + - const: hosc + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun9i-a80-ccu.h> + + usb_clocks: clock@a08000 { + compatible = "allwinner,sun9i-a80-usb-clks"; + reg = <0x00a08000 0x8>; + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; + clock-names = "bus", "hosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml new file mode 100644 index 0000000000..15218d10e7 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-mod-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB Module Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-mod-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 6 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@a08000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-mod-clk"; + reg = <0x00a08000 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb0_ahb", "usb_ohci0", + "usb1_ahb", "usb_ohci1", + "usb2_ahb", "usb_ohci2"; + }; + +... diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml new file mode 100644 index 0000000000..2569041684 --- /dev/null +++ b/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB PHY Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-phy-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 6 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@a08004 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-phy-clk"; + reg = <0x00a08004 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb_phy0", "usb_hsic1_480M", + "usb_phy1", "usb_hsic2_480M", + "usb_phy2", "usb_hsic_12M"; + }; + +... diff --git a/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml b/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 0000000000..4b8669f870 --- /dev/null +++ b/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller Device Tree Bindings + +maintainers: + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/amlogic,meson8b-clkc.txt b/dts/Bindings/clock/amlogic,meson8b-clkc.txt index 4d94091c1d..cc51e4746b 100644 --- a/dts/Bindings/clock/amlogic,meson8b-clkc.txt +++ b/dts/Bindings/clock/amlogic,meson8b-clkc.txt @@ -11,6 +11,11 @@ Required Properties: - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - #clock-cells: should be 1. - #reset-cells: should be 1. +- clocks: list of clock phandles, one for each entry in clock-names +- clock-names: should contain the following: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) Parent node should have the following properties : - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" diff --git a/dts/Bindings/clock/bitmain,bm1880-clk.yaml b/dts/Bindings/clock/bitmain,bm1880-clk.yaml index e63827399c..8559fe8f7e 100644 --- a/dts/Bindings/clock/bitmain,bm1880-clk.yaml +++ b/dts/Bindings/clock/bitmain,bm1880-clk.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml# +$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Bitmain BM1880 Clock Controller diff --git a/dts/Bindings/clock/fsl,plldig.yaml b/dts/Bindings/clock/fsl,plldig.yaml new file mode 100644 index 0000000000..c8350030b3 --- /dev/null +++ b/dts/Bindings/clock/fsl,plldig.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding + +maintainers: + - Wen He <wen.he_1@nxp.com> + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + fsl,vco-hz: + description: Optional for VCO frequency of the PLL in Hertz. + The VCO frequency of this PLL cannot be changed during runtime + only at startup. Therefore, the output frequencies are very + limited and might not even closely match the requested frequency. + To work around this restriction the user may specify its own + desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... diff --git a/dts/Bindings/clock/fsl,sai-clock.yaml b/dts/Bindings/clock/fsl,sai-clock.yaml new file mode 100644 index 0000000000..fc3bdfdc09 --- /dev/null +++ b/dts/Bindings/clock/fsl,sai-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SAI bitclock-as-a-clock binding + +maintainers: + - Michael Walle <michael@walle.cc> + +description: | + It is possible to use the BCLK pin of a SAI module as a generic clock + output. Some SoC are very constrained in their pin multiplexer + configuration. Eg. pins can only be changed groups. For example, on the + LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, + the second pins are wasted. Using this binding it is possible to use the + clock of the second SAI as a MCLK clock for an audio codec, for example. + + This is a composite of a gated clock and a divider clock. + +properties: + compatible: + const: fsl,vf610-sai-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mclk: clock-mclk@f130080 { + compatible = "fsl,vf610-sai-clock"; + reg = <0x0 0xf130080 0x0 0x80>; + #clock-cells = <0>; + clocks = <&parentclk>; + }; + }; diff --git a/dts/Bindings/clock/imx8mn-clock.yaml b/dts/Bindings/clock/imx8mn-clock.yaml index 622f3658bd..cd0b8a3413 100644 --- a/dts/Bindings/clock/imx8mn-clock.yaml +++ b/dts/Bindings/clock/imx8mn-clock.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml# +$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX8M Nano Clock Control Module Binding diff --git a/dts/Bindings/clock/imx8mp-clock.yaml b/dts/Bindings/clock/imx8mp-clock.yaml new file mode 100644 index 0000000000..89aee63c90 --- /dev/null +++ b/dts/Bindings/clock/imx8mp-clock.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Plus Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + NXP i.MX8M Plus clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: fsl,imx8mp-ccm + + reg: + maxItems: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h + for the full list of i.MX8M Plus clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, + <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", + "clk_ext2", "clk_ext3", "clk_ext4"; + }; + +... diff --git a/dts/Bindings/clock/milbeaut-clock.yaml b/dts/Bindings/clock/milbeaut-clock.yaml index 5cf0b81182..f0b804a7f0 100644 --- a/dts/Bindings/clock/milbeaut-clock.yaml +++ b/dts/Bindings/clock/milbeaut-clock.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml# +$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Milbeaut SoCs Clock Controller Binding diff --git a/dts/Bindings/clock/qcom,dispcc.txt b/dts/Bindings/clock/qcom,dispcc.txt deleted file mode 100644 index d639e18d0b..0000000000 --- a/dts/Bindings/clock/qcom,dispcc.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm Technologies, Inc. Display Clock Controller Binding ------------------------------------------------------------- - -Required properties : - -- compatible : shall contain "qcom,sdm845-dispcc" -- reg : shall contain base register location and length. -- #clock-cells : from common clock binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Example: - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x100000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/dts/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/Bindings/clock/qcom,gcc-apq8064.yaml new file mode 100644 index 0000000000..17f87178f6 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-apq8064.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on APQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-msm8960.h + - dt-bindings/reset/qcom,gcc-msm8960.h + +properties: + compatible: + const: qcom,gcc-apq8064 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + nvmem-cells: + minItems: 1 + maxItems: 2 + description: + Qualcomm TSENS (thermal sensor device) on some devices can + be part of GCC and hence the TSENS properties can also be part + of the GCC/clock-controller node. + For more details on the TSENS properties please refer + Documentation/devicetree/bindings/thermal/qcom-tsens.txt + + nvmem-cell-names: + minItems: 1 + maxItems: 2 + items: + - const: calib + - const: calib_backup + + '#thermal-sensor-cells': + const: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + - nvmem-cells + - nvmem-cell-names + - '#thermal-sensor-cells' + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + #thermal-sensor-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-ipq8074.yaml b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml new file mode 100644 index 0000000000..89c6e070e7 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8074. + + See also: + - dt-bindings/clock/qcom,gcc-ipq8074.h + +properties: + compatible: + const: qcom,gcc-ipq8074 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-msm8996.yaml b/dts/Bindings/clock/qcom,gcc-msm8996.yaml new file mode 100644 index 0000000000..18e4e77b8c --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8996.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8996 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8996. + + See also: + - dt-bindings/clock/qcom,gcc-msm8996.h + +properties: + compatible: + const: qcom,gcc-msm8996 + + clocks: + items: + - description: XO source + - description: Second XO source + - description: Sleep clock source + + clock-names: + items: + - const: cxo + - const: cxo2 + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x300000 0x90000>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-msm8998.yaml b/dts/Bindings/clock/qcom,gcc-msm8998.yaml new file mode 100644 index 0000000000..1d3cae9804 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8998.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8998 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8998. + + See also: + - dt-bindings/clock/qcom,gcc-msm8998.h + +properties: + compatible: + const: qcom,gcc-msm8998 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: USB 3.0 phy pipe clock + - description: UFS phy rx symbol clock for pipe 0 + - description: UFS phy rx symbol clock for pipe 1 + - description: UFS phy tx symbol clock + - description: PCIE phy pipe clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: usb3_pipe + - const: ufs_rx_symbol0 + - const: ufs_rx_symbol1 + - const: ufs_tx_symbol0 + - const: pcie0_pipe + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@100000 { + compatible = "qcom,gcc-msm8998"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x00100000 0xb0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "usb3_pipe", + "ufs_rx_symbol0", + "ufs_rx_symbol1", + "ufs_tx_symbol0", + "pcie0_pipe"; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-qcs404.yaml b/dts/Bindings/clock/qcom,gcc-qcs404.yaml new file mode 100644 index 0000000000..8cdece395e --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-qcs404.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on QCS404. + + See also: + - dt-bindings/clock/qcom,gcc-qcs404.h + +properties: + compatible: + const: qcom,gcc-qcs404 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-sc7180.yaml b/dts/Bindings/clock/qcom,gcc-sc7180.yaml new file mode 100644 index 0000000000..ee4f968e29 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-sc7180.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SC7180 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,gcc-sc7180.h + +properties: + compatible: + const: qcom,gcc-sc7180 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-sm8150.yaml b/dts/Bindings/clock/qcom,gcc-sm8150.yaml new file mode 100644 index 0000000000..888e9a7083 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-sm8150.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8150 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8150. + + See also: + - dt-bindings/clock/qcom,gcc-sm8150.h + +properties: + compatible: + const: qcom,gcc-sm8150 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8150"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc.yaml b/dts/Bindings/clock/qcom,gcc.yaml index e73a56fb60..d18f8ab9ee 100644 --- a/dts/Bindings/clock/qcom,gcc.yaml +++ b/dts/Bindings/clock/qcom,gcc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/qcom,gcc.yaml# +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller Binding @@ -14,46 +14,42 @@ description: | Qualcomm global clock control module which supports the clocks, resets and power domains. + See also: + - dt-bindings/clock/qcom,gcc-apq8084.h + - dt-bindings/reset/qcom,gcc-apq8084.h + - dt-bindings/clock/qcom,gcc-ipq4019.h + - dt-bindings/clock/qcom,gcc-ipq6018.h + - dt-bindings/reset/qcom,gcc-ipq6018.h + - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + - dt-bindings/clock/qcom,gcc-msm8660.h + - dt-bindings/reset/qcom,gcc-msm8660.h + - dt-bindings/clock/qcom,gcc-msm8974.h + - dt-bindings/reset/qcom,gcc-msm8974.h + - dt-bindings/clock/qcom,gcc-msm8994.h + - dt-bindings/clock/qcom,gcc-mdm9615.h + - dt-bindings/reset/qcom,gcc-mdm9615.h + - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) + - dt-bindings/clock/qcom,gcc-sdm845.h + properties: - compatible : + compatible: enum: - - qcom,gcc-apq8064 - - qcom,gcc-apq8084 - - qcom,gcc-ipq8064 - - qcom,gcc-ipq4019 - - qcom,gcc-ipq8074 - - qcom,gcc-msm8660 - - qcom,gcc-msm8916 - - qcom,gcc-msm8960 - - qcom,gcc-msm8974 - - qcom,gcc-msm8974pro - - qcom,gcc-msm8974pro-ac - - qcom,gcc-msm8994 - - qcom,gcc-msm8996 - - qcom,gcc-msm8998 - - qcom,gcc-mdm9615 - - qcom,gcc-qcs404 - - qcom,gcc-sc7180 - - qcom,gcc-sdm630 - - qcom,gcc-sdm660 - - qcom,gcc-sdm845 - - qcom,gcc-sm8150 - - clocks: - minItems: 1 - maxItems: 3 - items: - - description: Board XO source - - description: Board active XO source - - description: Sleep clock source - - clock-names: - minItems: 1 - maxItems: 3 - items: - - const: bi_tcxo - - const: bi_tcxo_ao - - const: sleep_clk + - qcom,gcc-apq8084 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq6018 + - qcom,gcc-ipq8064 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-msm8994 + - qcom,gcc-mdm9615 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - qcom,gcc-sdm845 '#clock-cells': const: 1 @@ -67,31 +63,9 @@ properties: reg: maxItems: 1 - nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Qualcomm TSENS (thermal sensor device) on some devices can - be part of GCC and hence the TSENS properties can also be part - of the GCC/clock-controller node. - For more details on the TSENS properties please refer - Documentation/devicetree/bindings/thermal/qcom-tsens.txt - - nvmem-cell-names: - minItems: 1 - maxItems: 2 - description: - Names for each nvmem-cells specified. - items: - - const: calib - - const: calib_backup - - 'thermal-sensor-cells': - const: 1 - protected-clocks: description: - Protected clock specifier list as per common clock binding + Protected clock specifier list as per common clock binding. required: - compatible @@ -100,32 +74,6 @@ required: - '#reset-cells' - '#power-domain-cells' -if: - properties: - compatible: - contains: - const: qcom,gcc-apq8064 - -then: - required: - - nvmem-cells - - nvmem-cell-names - - '#thermal-sensor-cells' - -else: - if: - properties: - compatible: - contains: - enum: - - qcom,gcc-sm8150 - - qcom,gcc-sc7180 - then: - required: - - clocks - - clock-names - - examples: # Example for GCC for MSM8960: - | @@ -136,53 +84,4 @@ examples: #reset-cells = <1>; #power-domain-cells = <1>; }; - - - # Example of GCC with TSENS properties: - - | - clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - #thermal-sensor-cells = <1>; - }; - - # Example of GCC with protected-clocks properties: - - | - clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; - protected-clocks = <187>, <188>, <189>, <190>, <191>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - # Example of GCC with clock node properties for SM8150: - - | - clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x00100000 0x1f0000>; - clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - # Example of GCC with clock nodes properties for SC7180: - - | - clock-controller@100000 { - compatible = "qcom,gcc-sc7180"; - reg = <0x100000 0x1f0000>; - clocks = <&rpmhcc 0>, <&rpmhcc 1>; - clock-names = "bi_tcxo", "bi_tcxo_ao"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; ... diff --git a/dts/Bindings/clock/qcom,gpucc.txt b/dts/Bindings/clock/qcom,gpucc.txt deleted file mode 100644 index 269afe8a75..0000000000 --- a/dts/Bindings/clock/qcom,gpucc.txt +++ /dev/null @@ -1,24 +0,0 @@ -Qualcomm Graphics Clock & Reset Controller Binding --------------------------------------------------- - -Required properties : -- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1 -- #reset-cells : from common reset binding, shall contain 1 -- #power-domain-cells : from generic power domain binding, shall contain 1 -- clocks : shall contain the XO clock - shall contain the gpll0 out main clock (msm8998) -- clock-names : shall be "xo" - shall be "gpll0" (msm8998) - -Example: - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - }; diff --git a/dts/Bindings/clock/qcom,mmcc.txt b/dts/Bindings/clock/qcom,mmcc.txt deleted file mode 100644 index 8b0f7841af..0000000000 --- a/dts/Bindings/clock/qcom,mmcc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Qualcomm Multimedia Clock & Reset Controller Binding ----------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,mmcc-apq8064" - "qcom,mmcc-apq8084" - "qcom,mmcc-msm8660" - "qcom,mmcc-msm8960" - "qcom,mmcc-msm8974" - "qcom,mmcc-msm8996" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Optional properties : -- #power-domain-cells : shall contain 1 - -Example: - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/dts/Bindings/clock/qcom,mmcc.yaml b/dts/Bindings/clock/qcom,mmcc.yaml new file mode 100644 index 0000000000..85518494ce --- /dev/null +++ b/dts/Bindings/clock/qcom,mmcc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multimedia Clock & Reset Controller Binding + +maintainers: + - Jeffrey Hugo <jhugo@codeaurora.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm multimedia clock control module which supports the clocks, resets and + power domains. + +properties: + compatible : + enum: + - qcom,mmcc-apq8064 + - qcom,mmcc-apq8084 + - qcom,mmcc-msm8660 + - qcom,mmcc-msm8960 + - qcom,mmcc-msm8974 + - qcom,mmcc-msm8996 + - qcom,mmcc-msm8998 + + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: Global PLL 0 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: DisplayPort phy PLL vco clock + - description: DisplayPort phy PLL link clock + + clock-names: + items: + - const: xo + - const: sleep + - const: gpll0 + - const: dsi0dsi + - const: dsi0byte + - const: dsi1dsi + - const: dsi1byte + - const: hdmipll + - const: dpvco + - const: dplink + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8998 + +then: + required: + - clocks + - clock-names + +examples: + # Example for MMCC for MSM8960: + - | + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,msm8998-gpucc.yaml b/dts/Bindings/clock/qcom,msm8998-gpucc.yaml new file mode 100644 index 0000000000..7d853c1a85 --- /dev/null +++ b/dts/Bindings/clock/qcom,msm8998-gpucc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on MSM8998. + + See also dt-bindings/clock/qcom,gpucc-msm8998.h. + +properties: + compatible: + const: qcom,msm8998-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) + + clock-names: + items: + - const: xo + - const: gpll0 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@5065000 { + compatible = "qcom,msm8998-gpucc"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x05065000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>; + clock-names = "xo", "gpll0"; + }; +... diff --git a/dts/Bindings/clock/qcom,rpmhcc.yaml b/dts/Bindings/clock/qcom,rpmhcc.yaml index 94e2f14eb9..2cd158f13b 100644 --- a/dts/Bindings/clock/qcom,rpmhcc.yaml +++ b/dts/Bindings/clock/qcom,rpmhcc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/qcom,rpmhcc.yaml# +$id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. RPMh Clocks Bindings diff --git a/dts/Bindings/clock/qcom,sc7180-dispcc.yaml b/dts/Bindings/clock/qcom,sc7180-dispcc.yaml new file mode 100644 index 0000000000..0429062f15 --- /dev/null +++ b/dts/Bindings/clock/qcom,sc7180-dispcc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,dispcc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi_phy 0>, + <&dsi_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sc7180-gpucc.yaml b/dts/Bindings/clock/qcom,sc7180-gpucc.yaml new file mode 100644 index 0000000000..5785192cc4 --- /dev/null +++ b/dts/Bindings/clock/qcom,sc7180-gpucc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,gpucc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk_src + - const: gcc_gpu_gpll0_div_clk_src + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sc7180-videocc.yaml b/dts/Bindings/clock/qcom,sc7180-videocc.yaml new file mode 100644 index 0000000000..31df901884 --- /dev/null +++ b/dts/Bindings/clock/qcom,sc7180-videocc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm video clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,videocc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-videocc + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sdm845-dispcc.yaml b/dts/Bindings/clock/qcom,sdm845-dispcc.yaml new file mode 100644 index 0000000000..89269ddfbd --- /dev/null +++ b/dts/Bindings/clock/qcom,sdm845-dispcc.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SDM845 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SDM845. + + See also dt-bindings/clock/qcom,dispcc-sdm845.h. + +properties: + compatible: + const: qcom,sdm845-dispcc + + # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. + # The code had to use hardcoded mechanisms to find the input clocks. + # New dts files should have these clocks. + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: GPLL0 div source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk_src + - const: gcc_disp_gpll0_div_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dsi1_phy_pll_out_byteclk + - const: dsi1_phy_pll_out_dsiclk + - const: dp_link_clk_divsel_ten + - const: dp_vco_divided_clk_src_mux + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sdm845-gpucc.yaml b/dts/Bindings/clock/qcom,sdm845-gpucc.yaml new file mode 100644 index 0000000000..bac04f1c5d --- /dev/null +++ b/dts/Bindings/clock/qcom,sdm845-gpucc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on SDM845. + + See also dt-bindings/clock/qcom,gpucc-sdm845.h. + +properties: + compatible: + const: qcom,sdm845-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk_src + - const: gcc_gpu_gpll0_div_clk_src + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sdm845-videocc.yaml b/dts/Bindings/clock/qcom,sdm845-videocc.yaml new file mode 100644 index 0000000000..9d216c0f11 --- /dev/null +++ b/dts/Bindings/clock/qcom,sdm845-videocc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller Binding for SDM845 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm video clock control module which supports the clocks, resets and + power domains on SDM845. + + See also dt-bindings/clock/qcom,videocc-sdm845.h. + +properties: + compatible: + const: qcom,sdm845-videocc + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,videocc.txt b/dts/Bindings/clock/qcom,videocc.txt deleted file mode 100644 index 8a8622c65c..0000000000 --- a/dts/Bindings/clock/qcom,videocc.txt +++ /dev/null @@ -1,18 +0,0 @@ -Qualcomm Video Clock & Reset Controller Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain "qcom,sdm845-videocc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. - -Example: - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - }; diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt index c7674d0267..f4d153f24a 100644 --- a/dts/Bindings/clock/renesas,cpg-mssr.txt +++ b/dts/Bindings/clock/renesas,cpg-mssr.txt @@ -19,7 +19,7 @@ Required Properties: - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N) + - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N) - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) diff --git a/dts/Bindings/clock/st,stm32mp1-rcc.txt b/dts/Bindings/clock/st,stm32mp1-rcc.txt deleted file mode 100644 index fb9495ea58..0000000000 --- a/dts/Bindings/clock/st,stm32mp1-rcc.txt +++ /dev/null @@ -1,60 +0,0 @@ -STMicroelectronics STM32 Peripheral Reset Clock Controller -========================================================== - -The RCC IP is both a reset and a clock controller. - -RCC makes also power management (resume/supend and wakeup interrupt). - -Please also refer to reset.txt for common reset controller binding usage. - -Please also refer to clock-bindings.txt for common clock controller -binding usage. - - -Required properties: -- compatible: "st,stm32mp1-rcc", "syscon" -- reg: should be register base and length as documented in the datasheet -- #clock-cells: 1, device nodes should specify the clock in their - "clocks" property, containing a phandle to the clock device node, - an index specifying the clock to use. -- #reset-cells: Shall be 1 -- interrupts: Should contain a general interrupt line and a interrupt line - to the wake-up of processor (CSTOP). - -Example: - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>, - <GIC_SPI 145 IRQ_TYPE_NONE>; - }; - -Specifying clocks -================= - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/stm32mp1-clks.h header and can be used in device -tree sources. - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example on STM32MP1, for LTDC reset: - ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset - = 0x180 / 4 * 32 + 0 = 3072 - -The list of valid indices for STM32MP1 is available in: -include/dt-bindings/reset-controller/stm32mp1-resets.h - -This file implements defines like: -#define LTDC_R 3072 diff --git a/dts/Bindings/clock/st,stm32mp1-rcc.yaml b/dts/Bindings/clock/st,stm32mp1-rcc.yaml new file mode 100644 index 0000000000..4e385508f5 --- /dev/null +++ b/dts/Bindings/clock/st,stm32mp1-rcc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Reset Clock Controller Binding + +maintainers: + - Gabriel Fernandez <gabriel.fernandez@st.com> + +description: | + The RCC IP is both a reset and a clock controller. + RCC makes also power management (resume/supend and wakeup interrupt). + Please also refer to reset.txt for common reset controller binding usage. + + This binding uses common clock bindings + Documentation/devicetree/bindings/clock/clock-bindings.txt + + Specifying clocks + ================= + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/stm32mp1-clks.h header and can be used in device + tree sources. + + Specifying softreset control of devices + ======================================= + + Device nodes should specify the reset channel required in their "resets" + property, containing a phandle to the reset device node and an index specifying + which channel to use. + The index is the bit number within the RCC registers bank, starting from RCC + base address. + It is calculated as: index = register_offset / 4 * 32 + bit_offset. + Where bit_offset is the bit offset within the register. + + For example on STM32MP1, for LTDC reset: + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset + = 0x180 / 4 * 32 + 0 = 3072 + + The list of valid indices for STM32MP1 is available in: + include/dt-bindings/reset-controller/stm32mp1-resets.h + + This file implements defines like: + #define LTDC_R 3072 + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + items: + - const: st,stm32mp1-rcc + - const: syscon + + reg: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/sun8i-de2.txt b/dts/Bindings/clock/sun8i-de2.txt deleted file mode 100644 index 41a52c2acf..0000000000 --- a/dts/Bindings/clock/sun8i-de2.txt +++ /dev/null @@ -1,34 +0,0 @@ -Allwinner Display Engine 2.0/3.0 Clock Control Binding ------------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun8i-a83t-de2-clk" - - "allwinner,sun8i-h3-de2-clk" - - "allwinner,sun8i-v3s-de2-clk" - - "allwinner,sun50i-a64-de2-clk" - - "allwinner,sun50i-h5-de2-clk" - - "allwinner,sun50i-h6-de3-clk" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock (on A83T it's the DE PLL) - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de2_clocks: clock@1000000 { - compatible = "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/clock/sun9i-de.txt b/dts/Bindings/clock/sun9i-de.txt deleted file mode 100644 index fb18f327b9..0000000000 --- a/dts/Bindings/clock/sun9i-de.txt +++ /dev/null @@ -1,28 +0,0 @@ -Allwinner A80 Display Engine Clock Control Binding --------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-de-clks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock - - "dram": the DRAM bus clock for the system - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; - clock-names = "mod", "dram", "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/clock/sun9i-usb.txt b/dts/Bindings/clock/sun9i-usb.txt deleted file mode 100644 index 3564bd4f2a..0000000000 --- a/dts/Bindings/clock/sun9i-usb.txt +++ /dev/null @@ -1,24 +0,0 @@ -Allwinner A80 USB Clock Control Binding ---------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-usb-clocks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: - - "bus": the bus clock for the whole USB subsystem - - "hosc": the high frequency oscillator (usually at 24MHz) -- clock-names: Must contain the clock names described just above -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -usb_clocks: clock@a08000 { - compatible = "allwinner,sun9i-a80-usb-clks"; - reg = <0x00a08000 0x8>; - clocks = <&ccu CLK_BUS_USB>, <&osc24M>; - clock-names = "bus", "hosc"; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/clock/sunxi.txt b/dts/Bindings/clock/sunxi.txt deleted file mode 100644 index 1a042e20b1..0000000000 --- a/dts/Bindings/clock/sunxi.txt +++ /dev/null @@ -1,225 +0,0 @@ -Device Tree Clock bindings for arch-sunxi - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator - "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 - "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 - "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 - "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10 - "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 - "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock - "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock - "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 - "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 - "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock - "allwinner,sun4i-a10-axi-clk" - for the AXI clock - "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 - "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs - "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates - "allwinner,sun4i-a10-ahb-clk" - for the AHB clock - "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 - "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 - "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 - "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 - "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s - "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 - "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 - "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 - "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 - "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 - "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 - "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 - "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 - "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 - "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 - "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock - "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 - "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 - "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 - "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T - "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 - "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 - "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s - "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 - "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 - "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 - "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 - "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 - "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock - "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 - "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 - "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 - "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s - "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 - "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 - "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 - "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 - "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 - "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 - "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T - "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 - "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 - "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10 - "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 - "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13 - "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 - "allwinner,sun4i-a10-mmc-clk" - for the MMC clock - "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 - "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 - "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks - "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 - "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 - "allwinner,sun7i-a20-out-clk" - for the external output clocks - "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 - "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10 - "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10 - "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 - "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 - "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 - "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 - "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 - "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 - "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 - "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock - "allwinner,sun6i-a31-display-clk" - for the display clocks - -Required properties for all clocks: -- reg : shall be the control register address for the clock. -- clocks : shall be the input parent clock(s) phandle for the clock. For - multiplexed clocks, the list order must match the hardware - programming order. -- #clock-cells : from common clock binding; shall be set to 0 except for - the following compatibles where it shall be set to 1: - "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", - "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", - "allwinner,*-usb-clk", "allwinner,*-mmc-clk", - "allwinner,*-mmc-config-clk" -- clock-output-names : shall be the corresponding names of the outputs. - If the clock module only has one output, the name shall be the - module name. - -And "allwinner,*-usb-clk" clocks also require: -- reset-cells : shall be set to 1 - -The "allwinner,sun4i-a10-ve-clk" clock also requires: -- reset-cells : shall be set to 0 - -The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: -- #reset-cells : shall be set to 1 -- resets : shall be the reset control phandle for the mmc block. - -For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate -dummy clocks at 25 MHz and 125 MHz, respectively. See example. - -Clock consumers should specify the desired clocks they use with a -"clocks" phandle cell. Consumers that are using a gated clock should -provide an additional ID in their clock property. This ID is the -offset of the bit controlling this particular gate in the register. -For the other clocks with "#clock-cells" = 1, the additional ID shall -refer to the index of the output. - -For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output -is the normal PLL6 output, or "pll6". The second output is rate doubled -PLL6, or "pll6x2". - -The "allwinner,*-mmc-clk" clocks have three different outputs: the -main clock, with the ID 0, and the output and sample clocks, with the -IDs 1 and 2, respectively. - -The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output -per mmc controller. The number of outputs is determined by the size of -the address block, which is related to the overall mmc block. - -For example: - -osc24M: clk@1c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M_fixed>; - clock-output-names = "osc24M"; -}; - -pll1: clk@1c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; -}; - -pll5: clk@1c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; -}; - -pll6: clk@1c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; -}; - -cpu: cpu@1c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>; - clock-output-names = "cpu"; -}; - -mmc0_clk: clk@1c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; -}; - -mii_phy_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; -}; - -gmac_int_tx_clk: clk@3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; -}; - -gmac_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - /* - * The first clock must be fixed at 25MHz; - * the second clock must be fixed at 125MHz - */ - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac"; -}; - -mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ahb0_gates 8>; - clock-names = "ahb"; - resets = <&ahb0_resets 8>; - reset-names = "ahb"; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; -}; diff --git a/dts/Bindings/clock/ti-clkctrl.txt b/dts/Bindings/clock/ti-clkctrl.txt index 48ee6991f2..18af6b9409 100644 --- a/dts/Bindings/clock/ti-clkctrl.txt +++ b/dts/Bindings/clock/ti-clkctrl.txt @@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at Documentation/devicetree/bindings/clock/clock-bindings.txt. Required properties : -- compatible : shall be "ti,clkctrl" +- compatible : shall be "ti,clkctrl" or a clock domain specific name: + "ti,clkctrl-l4-cfg" + "ti,clkctrl-l4-per" + "ti,clkctrl-l4-secure" + "ti,clkctrl-l4-wkup" - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index +- reg : clock registers Example: Clock controller node on omap 4430: &cm2 { l4per: cm@1400 { cm_l4per@0 { - cm_l4per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; + cm_l4per_clkctrl: clock@20 { + compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; diff --git a/dts/Bindings/clock/ti/dra7-atl.txt b/dts/Bindings/clock/ti/dra7-atl.txt index 10f7047755..21c002d28b 100644 --- a/dts/Bindings/clock/ti/dra7-atl.txt +++ b/dts/Bindings/clock/ti/dra7-atl.txt @@ -43,7 +43,7 @@ Configuration of ATL instances: - aws : Audio word select signal selection }; -For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include +For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include file. Examples: @@ -83,7 +83,7 @@ atl: atl@4843c000 { clock-names = "fck"; }; -#include <dt-bindings/clk/ti-dra7-atl.h> +#include <dt-bindings/clock/ti-dra7-atl.h> &atl { diff --git a/dts/Bindings/clock/xlnx,versal-clk.yaml b/dts/Bindings/clock/xlnx,versal-clk.yaml new file mode 100644 index 0000000000..229af98b1d --- /dev/null +++ b/dts/Bindings/clock/xlnx,versal-clk.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal clock controller + +maintainers: + - Michal Simek <michal.simek@xilinx.com> + - Jolly Shah <jolly.shah@xilinx.com> + - Rajan Vaja <rajan.vaja@xilinx.com> + +description: | + The clock controller is a hardware block of Xilinx versal clock tree. It + reads required input clock frequencies from the devicetree and acts as clock + provider for all clock consumers of PS clocks. + +select: false + +properties: + compatible: + const: xlnx,versal-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + items: + - description: reference clock + - description: alternate reference clock + - description: alternate reference clock for programmable logic + + clock-names: + items: + - const: ref + - const: alt_ref + - const: pl_alt_ref + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + versal_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,versal-clk"; + clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>; + clock-names = "ref", "alt_ref", "pl_alt_ref"; + }; + }; + }; +... |