diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-08-09 21:17:51 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-08-09 21:17:51 +0200 |
| commit | 6187b17da4b277417f34fe0b0b90bbaddcbc599e (patch) | |
| tree | 51cbbaa0fa325c592d084eb7d197a5df0e7a43bb /dts/Bindings/cpufreq | |
| parent | c53e1fc545e686e1f48c8efb9057fc72e158f183 (diff) | |
| download | barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.gz barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.xz | |
dts: update to v5.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/cpufreq')
| -rw-r--r-- | dts/Bindings/cpufreq/cpufreq-mediatek.txt | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt index ea4994b352..ef68711716 100644 --- a/dts/Bindings/cpufreq/cpufreq-mediatek.txt +++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt @@ -202,11 +202,11 @@ Example 2 (MT8173 SoC): cpu2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a57"; + compatible = "arm,cortex-a72"; reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, + clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table_b>; @@ -214,11 +214,11 @@ Example 2 (MT8173 SoC): cpu3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a57"; + compatible = "arm,cortex-a72"; reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, + clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table_b>; |