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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-07 08:12:03 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-07 08:12:03 +0100 |
commit | d299ff7dc2b85b0ddef999da5f3f1351e5a9e597 (patch) | |
tree | 6d1843fe3ed97e6246bc6dace205bb02c25ad9bc /dts/Bindings/cpufreq | |
parent | 7d24838f5cc96b6fbe23b32411e31a6cc00b152c (diff) | |
download | barebox-d299ff7dc2b85b0ddef999da5f3f1351e5a9e597.tar.gz barebox-d299ff7dc2b85b0ddef999da5f3f1351e5a9e597.tar.xz |
dts: update to v4.20-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/cpufreq')
-rw-r--r-- | dts/Bindings/cpufreq/arm_big_little_dt.txt | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/dts/Bindings/cpufreq/arm_big_little_dt.txt b/dts/Bindings/cpufreq/arm_big_little_dt.txt deleted file mode 100644 index 2aa06ac0fa..0000000000 --- a/dts/Bindings/cpufreq/arm_big_little_dt.txt +++ /dev/null @@ -1,65 +0,0 @@ -Generic ARM big LITTLE cpufreq driver's DT glue ------------------------------------------------ - -This is DT specific glue layer for generic cpufreq driver for big LITTLE -systems. - -Both required and optional properties listed below must be defined -under node /cpus/cpu@x. Where x is the first cpu inside a cluster. - -FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster -must be present contiguously. Generic DT driver will check only node 'x' for -cpu:x. - -Required properties: -- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt - for details - -Optional properties: -- clock-latency: Specify the possible maximum transition latency for clock, - in unit of nanoseconds. - -Examples: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@100 { - compatible = "arm,cortex-a7"; - reg = <100>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 950000 - 396000 750000 - 198000 450000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - }; - - cpu@101 { - compatible = "arm,cortex-a7"; - reg = <101>; - next-level-cache = <&L2>; - }; -}; |