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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-18 11:24:12 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-20 08:41:39 +0200 |
commit | 32e2176ba05083b66b7585d4ca81bcb5c5d72f84 (patch) | |
tree | 51b8628d96eb6415b11e2875dc6158f695af6573 /dts/Bindings/crypto | |
parent | 044294bdbee9e7ef8ffc5c3a9ef7841a09a84ff7 (diff) | |
download | barebox-32e2176ba05083b66b7585d4ca81bcb5c5d72f84.tar.gz barebox-32e2176ba05083b66b7585d4ca81bcb5c5d72f84.tar.xz |
dts: update to v6.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/crypto')
-rw-r--r-- | dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/crypto/aspeed,ast2500-hace.yaml | 53 | ||||
-rw-r--r-- | dts/Bindings/crypto/intel,keembay-ocs-aes.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/crypto/samsung-slimsss.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/crypto/ti,sa2ul.yaml | 13 | ||||
-rw-r--r-- | dts/Bindings/crypto/xlnx,zynqmp-aes.yaml | 2 |
8 files changed, 58 insertions, 19 deletions
diff --git a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml index dedc99e34e..0401c11da8 100644 --- a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Security System Device Tree Bindings +title: Allwinner A10 Security System maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/crypto/aspeed,ast2500-hace.yaml b/dts/Bindings/crypto/aspeed,ast2500-hace.yaml new file mode 100644 index 0000000000..a772d232de --- /dev/null +++ b/dts/Bindings/crypto/aspeed,ast2500-hace.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED HACE hash and crypto Hardware Accelerator Engines + +maintainers: + - Neal Liu <neal_liu@aspeedtech.com> + +description: | + The Hash and Crypto Engine (HACE) is designed to accelerate the throughput + of hash data digest, encryption, and decryption. Basically, HACE can be + divided into two independently engines - Hash Engine and Crypto Engine. + +properties: + compatible: + enum: + - aspeed,ast2500-hace + - aspeed,ast2600-hace + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ast2600-clock.h> + hace: crypto@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = <4>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; diff --git a/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml b/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml index ee2c099981..fedd8be56a 100644 --- a/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml +++ b/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay OCS AES Device Tree Bindings +title: Intel Keem Bay OCS AES maintainers: - Daniele Alessandrelli <daniele.alessandrelli@intel.com> diff --git a/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml index a3c16451b1..2bb95247b6 100644 --- a/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml +++ b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay OCS ECC Device Tree Bindings +title: Intel Keem Bay OCS ECC maintainers: - Daniele Alessandrelli <daniele.alessandrelli@intel.com> diff --git a/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml b/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml index acb92706d2..46e2853ab8 100644 --- a/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml +++ b/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay OCS HCU Device Tree Bindings +title: Intel Keem Bay OCS HCU maintainers: - Declan Murphy <declan.murphy@intel.com> diff --git a/dts/Bindings/crypto/samsung-slimsss.yaml b/dts/Bindings/crypto/samsung-slimsss.yaml index 676950bb7b..5b31891c97 100644 --- a/dts/Bindings/crypto/samsung-slimsss.yaml +++ b/dts/Bindings/crypto/samsung-slimsss.yaml @@ -24,7 +24,6 @@ properties: maxItems: 1 clocks: - minItems: 2 maxItems: 2 clock-names: diff --git a/dts/Bindings/crypto/ti,sa2ul.yaml b/dts/Bindings/crypto/ti,sa2ul.yaml index 02f47c2e79..0c15fefb66 100644 --- a/dts/Bindings/crypto/ti,sa2ul.yaml +++ b/dts/Bindings/crypto/ti,sa2ul.yaml @@ -35,8 +35,6 @@ properties: - const: rx1 - const: rx2 - dma-coherent: true - "#address-cells": const: 2 @@ -72,16 +70,6 @@ required: - dmas - dma-names -if: - properties: - compatible: - enum: - - ti,j721e-sa2ul - - ti,am654-sa2ul -then: - required: - - dma-coherent - additionalProperties: false examples: @@ -95,5 +83,4 @@ examples: dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; dma-names = "tx", "rx1", "rx2"; - dma-coherent; }; diff --git a/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml b/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml index 55dd6e3d27..9e8fbd02b1 100644 --- a/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml +++ b/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings +title: Xilinx ZynqMP AES-GCM Hardware Accelerator maintainers: - Kalyani Akula <kalyani.akula@xilinx.com> |