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authorSascha Hauer <s.hauer@pengutronix.de>2018-09-11 08:26:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-09-11 17:23:13 +0200
commit35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch)
treedd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/Bindings/crypto
parent625eea2765d94aee016cf25d9cabecde8eae0775 (diff)
downloadbarebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/crypto')
-rw-r--r--dts/Bindings/crypto/amd-ccp.txt2
-rw-r--r--dts/Bindings/crypto/arm-cryptocell.txt2
-rw-r--r--dts/Bindings/crypto/fsl-sec2.txt5
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt21
-rw-r--r--dts/Bindings/crypto/hisilicon,hip07-sec.txt67
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt15
-rw-r--r--dts/Bindings/crypto/picochip-spacc.txt2
-rw-r--r--dts/Bindings/crypto/qcom,prng.txt19
8 files changed, 98 insertions, 35 deletions
diff --git a/dts/Bindings/crypto/amd-ccp.txt b/dts/Bindings/crypto/amd-ccp.txt
index 8c61183..d87579d 100644
--- a/dts/Bindings/crypto/amd-ccp.txt
+++ b/dts/Bindings/crypto/amd-ccp.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: Should be "amd,ccp-seattle-v1a"
- reg: Address and length of the register set for the device
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- interrupts: Should contain the CCP interrupt
Optional properties:
diff --git a/dts/Bindings/crypto/arm-cryptocell.txt b/dts/Bindings/crypto/arm-cryptocell.txt
index c2598ab..999fb2a 100644
--- a/dts/Bindings/crypto/arm-cryptocell.txt
+++ b/dts/Bindings/crypto/arm-cryptocell.txt
@@ -7,8 +7,6 @@ Required properties:
- interrupts: Interrupt number for the device.
Optional properties:
-- interrupt-parent: The phandle for the interrupt controller that services
- interrupts for this device.
- clocks: Reference to the crypto engine clock.
- dma-coherent: Present if dma operations are coherent.
diff --git a/dts/Bindings/crypto/fsl-sec2.txt b/dts/Bindings/crypto/fsl-sec2.txt
index f0d926b..125f155 100644
--- a/dts/Bindings/crypto/fsl-sec2.txt
+++ b/dts/Bindings/crypto/fsl-sec2.txt
@@ -50,11 +50,6 @@ remaining bits are reserved for future SEC EUs.
..and so on and so forth.
-Optional properties:
-
-- interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
-
Example:
/* MPC8548E */
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 3c1f3a2..2fe245c 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -99,13 +99,6 @@ PROPERTIES
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
- clocks
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <prop_encoded-array>
@@ -199,13 +192,6 @@ Job Ring (JR) Node
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
EXAMPLE
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
@@ -370,13 +356,6 @@ Secure Non-Volatile Storage (SNVS) Node
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
EXAMPLE
sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon";
diff --git a/dts/Bindings/crypto/hisilicon,hip07-sec.txt b/dts/Bindings/crypto/hisilicon,hip07-sec.txt
new file mode 100644
index 0000000..78d2db9
--- /dev/null
+++ b/dts/Bindings/crypto/hisilicon,hip07-sec.txt
@@ -0,0 +1,67 @@
+* Hisilicon hip07 Security Accelerator (SEC)
+
+Required properties:
+- compatible: Must contain one of
+ - "hisilicon,hip06-sec"
+ - "hisilicon,hip07-sec"
+- reg: Memory addresses and lengths of the memory regions through which
+ this device is controlled.
+ Region 0 has registers to control the backend processing engines.
+ Region 1 has registers for functionality common to all queues.
+ Regions 2-18 have registers for the 16 individual queues which are isolated
+ both in hardware and within the driver.
+- interrupts: Interrupt specifiers.
+ Refer to interrupt-controller/interrupts.txt for generic interrupt client node
+ bindings.
+ Interrupt 0 is for the SEC unit error queue.
+ Interrupt 2N + 1 is the completion interrupt for queue N.
+ Interrupt 2N + 2 is the error interrupt for queue N.
+- dma-coherent: The driver assumes coherent dma is possible.
+
+Optional properties:
+- iommus: The SEC units are behind smmu-v3 iommus.
+ Refer to iommu/arm,smmu-v3.txt for more information.
+
+Example:
+
+p1_sec_a: crypto@400,d2000000 {
+ compatible = "hisilicon,hip07-sec";
+ reg = <0x400 0xd0000000 0x0 0x10000
+ 0x400 0xd2000000 0x0 0x10000
+ 0x400 0xd2010000 0x0 0x10000
+ 0x400 0xd2020000 0x0 0x10000
+ 0x400 0xd2030000 0x0 0x10000
+ 0x400 0xd2040000 0x0 0x10000
+ 0x400 0xd2050000 0x0 0x10000
+ 0x400 0xd2060000 0x0 0x10000
+ 0x400 0xd2070000 0x0 0x10000
+ 0x400 0xd2080000 0x0 0x10000
+ 0x400 0xd2090000 0x0 0x10000
+ 0x400 0xd20a0000 0x0 0x10000
+ 0x400 0xd20b0000 0x0 0x10000
+ 0x400 0xd20c0000 0x0 0x10000
+ 0x400 0xd20d0000 0x0 0x10000
+ 0x400 0xd20e0000 0x0 0x10000
+ 0x400 0xd20f0000 0x0 0x10000
+ 0x400 0xd2100000 0x0 0x10000>;
+ interrupt-parent = <&p1_mbigen_sec_a>;
+ iommus = <&p1_smmu_alg_a 0x600>;
+ dma-coherent;
+ interrupts = <576 4>,
+ <577 1>, <578 4>,
+ <579 1>, <580 4>,
+ <581 1>, <582 4>,
+ <583 1>, <584 4>,
+ <585 1>, <586 4>,
+ <587 1>, <588 4>,
+ <589 1>, <590 4>,
+ <591 1>, <592 4>,
+ <593 1>, <594 4>,
+ <595 1>, <596 4>,
+ <597 1>, <598 4>,
+ <599 1>, <600 4>,
+ <601 1>, <602 4>,
+ <603 1>, <604 4>,
+ <605 1>, <606 4>,
+ <607 1>, <608 4>;
+};
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
index 5dba55c..3bbf144 100644
--- a/dts/Bindings/crypto/inside-secure-safexcel.txt
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -1,8 +1,9 @@
Inside Secure SafeXcel cryptographic engine
Required properties:
-- compatible: Should be "inside-secure,safexcel-eip197" or
- "inside-secure,safexcel-eip97".
+- compatible: Should be "inside-secure,safexcel-eip197b",
+ "inside-secure,safexcel-eip197d" or
+ "inside-secure,safexcel-eip97ies".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt numbers for the rings and engine.
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
@@ -14,10 +15,18 @@ Optional properties:
name must be "core" for the first clock and "reg" for
the second one.
+Backward compatibility:
+Two compatibles are kept for backward compatibility, but shouldn't be used for
+new submissions:
+- "inside-secure,safexcel-eip197" is equivalent to
+ "inside-secure,safexcel-eip197b".
+- "inside-secure,safexcel-eip97" is equivalent to
+ "inside-secure,safexcel-eip97ies".
+
Example:
crypto: crypto@800000 {
- compatible = "inside-secure,safexcel-eip197";
+ compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/Bindings/crypto/picochip-spacc.txt b/dts/Bindings/crypto/picochip-spacc.txt
index d8609ec..df1151f 100644
--- a/dts/Bindings/crypto/picochip-spacc.txt
+++ b/dts/Bindings/crypto/picochip-spacc.txt
@@ -7,8 +7,6 @@ Required properties:
- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
- reg : Offset and length of the register set for this device
- - interrupt-parent : The interrupt controller that controls the SPAcc
- interrupt.
- interrupts : The interrupt line from the SPAcc.
- ref-clock : The input clock that drives the SPAcc.
diff --git a/dts/Bindings/crypto/qcom,prng.txt b/dts/Bindings/crypto/qcom,prng.txt
new file mode 100644
index 0000000..7ee0e9e
--- /dev/null
+++ b/dts/Bindings/crypto/qcom,prng.txt
@@ -0,0 +1,19 @@
+Qualcomm MSM pseudo random number generator.
+
+Required properties:
+
+- compatible : should be "qcom,prng" for 8916 etc
+ : should be "qcom,prng-ee" for 8996 and later using EE
+ (Execution Environment) slice of prng
+- reg : specifies base physical address and size of the registers map
+- clocks : phandle to clock-controller plus clock-specifier pair
+- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
+
+Example:
+
+ rng@f9bff000 {
+ compatible = "qcom,prng";
+ reg = <0xf9bff000 0x200>;
+ clocks = <&clock GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };