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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-11-17 07:36:09 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-11-17 07:36:09 +0100 |
| commit | 3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 (patch) | |
| tree | eb5a7bfce811d20e58dd0eb1add0f6cf0e6b86e0 /dts/Bindings/crypto | |
| parent | 81ceab95360295cef146e89a1cd1cd5e590aa75e (diff) | |
| download | barebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.gz barebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.xz | |
dts: update to v5.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/crypto')
| -rw-r--r-- | dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml | 47 | ||||
| -rw-r--r-- | dts/Bindings/crypto/st,stm32-crc.yaml | 2 | ||||
| -rw-r--r-- | dts/Bindings/crypto/st,stm32-cryp.yaml | 2 | ||||
| -rw-r--r-- | dts/Bindings/crypto/st,stm32-hash.yaml | 2 |
4 files changed, 50 insertions, 3 deletions
diff --git a/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml new file mode 100644 index 0000000000..a3c16451b1 --- /dev/null +++ b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay OCS ECC Device Tree Bindings + +maintainers: + - Daniele Alessandrelli <daniele.alessandrelli@intel.com> + - Prabhjot Khurana <prabhjot.khurana@intel.com> + +description: + The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve + Cryptography (ECC) device provides hardware acceleration for elliptic curve + cryptography using the NIST P-256 and NIST P-384 elliptic curves. + +properties: + compatible: + const: intel,keembay-ocs-ecc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + crypto@30001000 { + compatible = "intel,keembay-ocs-ecc"; + reg = <0x30001000 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk 95>; + }; diff --git a/dts/Bindings/crypto/st,stm32-crc.yaml b/dts/Bindings/crypto/st,stm32-crc.yaml index cee624c14f..b72e4858f9 100644 --- a/dts/Bindings/crypto/st,stm32-crc.yaml +++ b/dts/Bindings/crypto/st,stm32-crc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRC bindings maintainers: - - Lionel Debieve <lionel.debieve@st.com> + - Lionel Debieve <lionel.debieve@foss.st.com> properties: compatible: diff --git a/dts/Bindings/crypto/st,stm32-cryp.yaml b/dts/Bindings/crypto/st,stm32-cryp.yaml index a457455250..ed23bf94a8 100644 --- a/dts/Bindings/crypto/st,stm32-cryp.yaml +++ b/dts/Bindings/crypto/st,stm32-cryp.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRYP bindings maintainers: - - Lionel Debieve <lionel.debieve@st.com> + - Lionel Debieve <lionel.debieve@foss.st.com> properties: compatible: diff --git a/dts/Bindings/crypto/st,stm32-hash.yaml b/dts/Bindings/crypto/st,stm32-hash.yaml index 6dd658f091..10ba94792d 100644 --- a/dts/Bindings/crypto/st,stm32-hash.yaml +++ b/dts/Bindings/crypto/st,stm32-hash.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 HASH bindings maintainers: - - Lionel Debieve <lionel.debieve@st.com> + - Lionel Debieve <lionel.debieve@foss.st.com> properties: compatible: |