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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-09 14:49:17 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-17 09:37:13 +0100 |
| commit | f826d85b7ab0924d5bf1a5458c49e7f7d8207a23 (patch) | |
| tree | dd6354e00da0aa143d1db6164e1a455dddb9b892 /dts/Bindings/crypto | |
| parent | 0e37f94fbe1bd189f35b3e1718549ec2f4a710ee (diff) | |
| download | barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.gz barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.xz | |
dts: update to v5.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/crypto')
| -rw-r--r-- | dts/Bindings/crypto/allwinner,sun8i-ce.yaml | 3 | ||||
| -rw-r--r-- | dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml | 46 | ||||
| -rw-r--r-- | dts/Bindings/crypto/samsung-slimsss.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/crypto/samsung-sss.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/crypto/ti,sa2ul.yaml | 2 |
5 files changed, 48 insertions, 5 deletions
diff --git a/dts/Bindings/crypto/allwinner,sun8i-ce.yaml b/dts/Bindings/crypto/allwinner,sun8i-ce.yaml index 7a60d84289..6ab07eba77 100644 --- a/dts/Bindings/crypto/allwinner,sun8i-ce.yaml +++ b/dts/Bindings/crypto/allwinner,sun8i-ce.yaml @@ -46,8 +46,7 @@ properties: if: properties: compatible: - items: - const: allwinner,sun50i-h6-crypto + const: allwinner,sun50i-h6-crypto then: properties: clocks: diff --git a/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml b/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml new file mode 100644 index 0000000000..acb92706d2 --- /dev/null +++ b/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay OCS HCU Device Tree Bindings + +maintainers: + - Declan Murphy <declan.murphy@intel.com> + - Daniele Alessandrelli <daniele.alessandrelli@intel.com> + +description: + The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU) + provides hardware-accelerated hashing and HMAC. + +properties: + compatible: + const: intel,keembay-ocs-hcu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + crypto@3000b000 { + compatible = "intel,keembay-ocs-hcu"; + reg = <0x3000b000 0x1000>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk 94>; + }; diff --git a/dts/Bindings/crypto/samsung-slimsss.yaml b/dts/Bindings/crypto/samsung-slimsss.yaml index 7743eae049..676950bb7b 100644 --- a/dts/Bindings/crypto/samsung-slimsss.yaml +++ b/dts/Bindings/crypto/samsung-slimsss.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos SoC SlimSSS (Slim Security SubSystem) module maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - - Kamil Konieczny <k.konieczny@partner.samsung.com> description: |+ The SlimSSS module in Exynos5433 SoC supports the following: diff --git a/dts/Bindings/crypto/samsung-sss.yaml b/dts/Bindings/crypto/samsung-sss.yaml index cf1c47a81d..6d62b0e42f 100644 --- a/dts/Bindings/crypto/samsung-sss.yaml +++ b/dts/Bindings/crypto/samsung-sss.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos SoC SSS (Security SubSystem) module maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - - Kamil Konieczny <k.konieczny@partner.samsung.com> description: |+ The SSS module in S5PV210 SoC supports the following: diff --git a/dts/Bindings/crypto/ti,sa2ul.yaml b/dts/Bindings/crypto/ti,sa2ul.yaml index 1465c9ebaf..1d48ac712b 100644 --- a/dts/Bindings/crypto/ti,sa2ul.yaml +++ b/dts/Bindings/crypto/ti,sa2ul.yaml @@ -66,7 +66,7 @@ examples: #include <dt-bindings/soc/ti,sci_pm_domain.h> main_crypto: crypto@4e00000 { - compatible = "ti,j721-sa2ul"; + compatible = "ti,j721e-sa2ul"; reg = <0x4e00000 0x1200>; power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, |