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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-03-10 08:56:15 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-03-10 08:56:15 +0100 |
commit | 957bb6b6bcebc4c36f5f284dfb58d489e81016c6 (patch) | |
tree | 593d098617017987daaf8ce339e0eb29ea09fdde /dts/Bindings/devfreq | |
parent | cc2392cf4f2d5208be427e9ffdeafba192f05cbe (diff) | |
download | barebox-957bb6b6bcebc4c36f5f284dfb58d489e81016c6.tar.gz barebox-957bb6b6bcebc4c36f5f284dfb58d489e81016c6.tar.xz |
dts: update to v4.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/devfreq')
-rw-r--r-- | dts/Bindings/devfreq/exynos-bus.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/dts/Bindings/devfreq/exynos-bus.txt b/dts/Bindings/devfreq/exynos-bus.txt index d3ec8e676b..d085ef90d2 100644 --- a/dts/Bindings/devfreq/exynos-bus.txt +++ b/dts/Bindings/devfreq/exynos-bus.txt @@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: |--- FSYS |--- FSYS2 +- In case of Exynos5433, there is VDD_INT power line as following: + VDD_INT |--- G2D (parent device) + |--- MSCL + |--- GSCL + |--- JPEG + |--- MFC + |--- HEVC + |--- BUS0 + |--- BUS1 + |--- BUS2 + |--- PERIS (Fixed clock rate) + |--- PERIC (Fixed clock rate) + |--- FSYS (Fixed clock rate) + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to |