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authorSascha Hauer <s.hauer@pengutronix.de>2018-09-11 08:26:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-09-11 17:23:13 +0200
commit35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch)
treedd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/Bindings/dma/nvidia,tegra210-adma.txt
parent625eea2765d94aee016cf25d9cabecde8eae0775 (diff)
downloadbarebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/dma/nvidia,tegra210-adma.txt')
-rw-r--r--dts/Bindings/dma/nvidia,tegra210-adma.txt1
1 files changed, 0 insertions, 1 deletions
diff --git a/dts/Bindings/dma/nvidia,tegra210-adma.txt b/dts/Bindings/dma/nvidia,tegra210-adma.txt
index 1e1dc8f..2f35b04 100644
--- a/dts/Bindings/dma/nvidia,tegra210-adma.txt
+++ b/dts/Bindings/dma/nvidia,tegra210-adma.txt
@@ -8,7 +8,6 @@ Required properties:
- reg: Should contain DMA registers location and length. This should be
a single entry that includes all of the per-channel registers in one
contiguous bank.
-- interrupt-parent: Phandle to the interrupt parent controller.
- interrupts: Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
- clocks: Must contain one entry for the ADMA module clock