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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-05 14:51:50 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-08 10:16:55 +0200 |
commit | 1dc748b3b202cadf9b799874d9af8d441ee556bc (patch) | |
tree | 58fd3c90a40e2d0128b0c7f36d63d7fc126bb20d /dts/Bindings/edac | |
parent | 9688b49cd3bc0b61a019e8e1311236c9975a0777 (diff) | |
download | barebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.gz barebox-1dc748b3b202cadf9b799874d9af8d441ee556bc.tar.xz |
dts: update to v5.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/edac')
-rw-r--r-- | dts/Bindings/edac/aspeed-sdram-edac.txt | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/dts/Bindings/edac/aspeed-sdram-edac.txt b/dts/Bindings/edac/aspeed-sdram-edac.txt new file mode 100644 index 0000000000..6a0f3d90d6 --- /dev/null +++ b/dts/Bindings/edac/aspeed-sdram-edac.txt @@ -0,0 +1,25 @@ +Aspeed AST2500 SoC EDAC node + +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +correction check). + +The memory controller supports SECDED (single bit error correction, double bit +error detection) and single bit error auto scrubbing by reserving 8 bits for +every 64 bit word (effectively reducing available memory to 8/9). + +Note, the bootloader must configure ECC mode in the memory controller. + + +Required properties: +- compatible: should be "aspeed,ast2500-sdram-edac" +- reg: sdram controller register set should be <0x1e6e0000 0x174> +- interrupts: should be AVIC interrupt #0 + + +Example: + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + }; |