path: root/dts/Bindings/firmware/nvidia,tegra210-bpmp.txt
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authorSascha Hauer <>2019-04-05 14:51:50 +0200
committerSascha Hauer <>2019-04-08 10:16:55 +0200
commit1dc748b3b202cadf9b799874d9af8d441ee556bc (patch)
tree58fd3c90a40e2d0128b0c7f36d63d7fc126bb20d /dts/Bindings/firmware/nvidia,tegra210-bpmp.txt
parent9688b49cd3bc0b61a019e8e1311236c9975a0777 (diff)
dts: update to v5.1-rc1
Signed-off-by: Sascha Hauer <>
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+NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
+The Boot and Power Management Processor (BPMP) is a co-processor found
+in Tegra210 SoC. It is designed to handle the early stages of the boot
+process as well as to assisting in entering deep low power state
+(suspend to ram), and also offloading DRAM memory clock scaling on
+some platforms. The binding document defines the resources that would
+be used by the BPMP T210 firmware driver, which can create the
+interprocessor communication (IPC) between the CPU and BPMP.
+Required properties:
+- compatible
+ Array of strings
+ One of:
+ - "nvidia,tegra210-bpmp"
+- reg: physical base address and length for HW synchornization primitives
+ 1) base address and length to Tegra 'atomics' hardware
+ 2) base address and length to Tegra 'semaphore' hardware
+- interrupts: specifies the interrupt number for receiving messages ("rx")
+ and for triggering messages ("tx")
+Optional properties:
+- #clock-cells : Should be 1 for platforms where DRAM clock control is
+ offloaded to bpmp.
+bpmp@70016000 {
+ compatible = "nvidia,tegra210-bpmp";
+ reg = <0x0 0x70016000 0x0 0x2000
+ 0x0 0x60001000 0x0 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ interrupt-names = "tx", "rx";