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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:26:15 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:48:45 +0100 |
commit | a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab (patch) | |
tree | 35f886d87a77df7bac8a587a04647691db541a2e /dts/Bindings/fpga/altera-hps2fpga-bridge.txt | |
parent | 81462901ce3d677ce318150f7027e2ce1cf97c41 (diff) | |
download | barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.gz barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.xz |
dts: update to v4.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/fpga/altera-hps2fpga-bridge.txt')
-rw-r--r-- | dts/Bindings/fpga/altera-hps2fpga-bridge.txt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/dts/Bindings/fpga/altera-hps2fpga-bridge.txt b/dts/Bindings/fpga/altera-hps2fpga-bridge.txt new file mode 100644 index 0000000000..6406f9337e --- /dev/null +++ b/dts/Bindings/fpga/altera-hps2fpga-bridge.txt @@ -0,0 +1,39 @@ +Altera FPGA/HPS Bridge Driver + +Required properties: +- regs : base address and size for AXI bridge module +- compatible : Should contain one of: + "altr,socfpga-lwhps2fpga-bridge", + "altr,socfpga-hps2fpga-bridge", or + "altr,socfpga-fpga2hps-bridge" +- resets : Phandle and reset specifier for this bridge's reset +- clocks : Clocks used by this module. + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup. + 1 if driver should enable bridge at startup. + Default is to leave bridge in its current state. + +Example: + fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + bridge-enable = <0>; + }; + + fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + bridge-enable = <1>; + }; + + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + }; |