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authorSascha Hauer <s.hauer@pengutronix.de>2017-01-10 08:26:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-01-10 08:48:45 +0100
commita40531fb3c11dc4ee8cca43c91b471da1fd3c1ab (patch)
tree35f886d87a77df7bac8a587a04647691db541a2e /dts/Bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
parent81462901ce3d677ce318150f7027e2ce1cf97c41 (diff)
downloadbarebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.gz
dts: update to v4.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/fpga/altera-socfpga-a10-fpga-mgr.txt')
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diff --git a/dts/Bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/dts/Bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
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+Altera SOCFPGA Arria10 FPGA Manager
+
+Required properties:
+- compatible : should contain "altr,socfpga-a10-fpga-mgr"
+- reg : base address and size for memory mapped io.
+ - The first index is for FPGA manager register access.
+ - The second index is for writing FPGA configuration data.
+- resets : Phandle and reset specifier for the device's reset.
+- clocks : Clocks used by the device.
+
+Example:
+
+ fpga_mgr: fpga-mgr@ffd03000 {
+ compatible = "altr,socfpga-a10-fpga-mgr";
+ reg = <0xffd03000 0x100
+ 0xffcfe400 0x20>;
+ clocks = <&l4_mp_clk>;
+ resets = <&rst FPGAMGR_RESET>;
+ };